Searched refs:dsgcr (Results 1 – 15 of 15) sorted by relevance
| /external/arm-trusted-firmware/include/drivers/st/ |
| D | stm32mp1_ddr.h | 116 uint32_t dsgcr; member
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| D | stm32mp1_ddr_regs.h | 155 uint32_t dsgcr; /* 0x2C DDR System General Configuration */ member
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| /external/u-boot/arch/arm/mach-sunxi/ |
| D | dram_sun6i.c | 148 writel(MCTL_DSGCR, &mctl_phy->dsgcr); in mctl_channel_init()
283 clrbits_le32(&mctl_phy1->dsgcr, MCTL_DSGCR_ENABLE); in mctl_com_init()
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| D | dram_sun9i.c | 630 clrbits_le32(&mctl_phy->dsgcr, (3 << 6)); in mctl_channel_init()
733 setbits_le32(&mctl_phy->dsgcr, 0xf << 24); /* unclear what this is... */ in mctl_channel_init()
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| D | dram_sun50i_h6.c | 434 clrsetbits_le32(&mctl_phy->dsgcr, BIT(0), 0x440060); in mctl_channel_init()
571 clrsetbits_le32(&mctl_phy->dsgcr, 0xc0, 0x40); in mctl_channel_init()
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| /external/u-boot/drivers/ram/stm32mp1/ |
| D | stm32mp1_ddr.h | 120 u32 dsgcr; member
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| D | stm32mp1_ddr_regs.h | 152 u32 dsgcr; /* 0x2C DDR System General Configuration*/ member
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| D | stm32mp1_ddr.c | 152 DDRPHY_REG_REG(dsgcr),
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| /external/u-boot/arch/arm/include/asm/arch-sunxi/ |
| D | dram_sun9i.h | 104 u32 dsgcr; /* 0x84 DRAM system general config register */ member
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| D | dram_sun50i_h6.h | 175 u32 dsgcr; /* 0x090 */ member
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| D | dram_sun8i_a23.h | 179 u32 dsgcr; /* 0x40 dram system general config register */ member
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| D | dram_sun6i.h | 168 u32 dsgcr; /* 0x2c dram system general config register */ member
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| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| D | ddr_rk3288.h | 176 u32 dsgcr; member
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| /external/arm-trusted-firmware/drivers/st/ddr/ |
| D | stm32mp1_ddr.c | 132 DDRPHY_REG_REG(dsgcr),
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| /external/u-boot/drivers/ram/rockchip/ |
| D | sdram_rk3288.c | 335 clrsetbits_le32(&publ->dsgcr, in phy_cfg()
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