1 /*
2 * H6 dram controller register and constant defines
3 *
4 * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #ifndef _SUNXI_DRAM_SUN50I_H6_H
10 #define _SUNXI_DRAM_SUN50I_H6_H
11
12 #include <stdbool.h>
13
14 enum sunxi_dram_type {
15 SUNXI_DRAM_TYPE_DDR3 = 3,
16 SUNXI_DRAM_TYPE_DDR4,
17 SUNXI_DRAM_TYPE_LPDDR2 = 6,
18 SUNXI_DRAM_TYPE_LPDDR3,
19 };
20
sunxi_dram_is_lpddr(int type)21 static inline bool sunxi_dram_is_lpddr(int type)
22 {
23 return type >= SUNXI_DRAM_TYPE_LPDDR2;
24 }
25
26 /*
27 * The following information is mainly retrieved by disassembly and some FPGA
28 * test code of sun50iw3 platform.
29 */
30 struct sunxi_mctl_com_reg {
31 u32 cr; /* 0x000 control register */
32 u8 reserved_0x004[4]; /* 0x004 */
33 u32 unk_0x008; /* 0x008 */
34 u32 tmr; /* 0x00c timer register */
35 u8 reserved_0x010[4]; /* 0x010 */
36 u32 unk_0x014; /* 0x014 */
37 u8 reserved_0x018[8]; /* 0x018 */
38 u32 maer0; /* 0x020 master enable register 0 */
39 u32 maer1; /* 0x024 master enable register 1 */
40 u32 maer2; /* 0x028 master enable register 2 */
41 u8 reserved_0x02c[468]; /* 0x02c */
42 u32 bwcr; /* 0x200 bandwidth control register */
43 u8 reserved_0x204[12]; /* 0x204 */
44 /*
45 * The last master configured by BSP libdram is at 0x49x, so the
46 * size of this struct array is set to 41 (0x29) now.
47 */
48 struct {
49 u32 cfg0; /* 0x0 */
50 u32 cfg1; /* 0x4 */
51 u8 reserved_0x8[8]; /* 0x8 */
52 } master[41]; /* 0x210 + index * 0x10 */
53 };
54 check_member(sunxi_mctl_com_reg, master[40].reserved_0x8, 0x498);
55
56 /*
57 * The following register information are retrieved from some similar DRAM
58 * controllers, including the DRAM controllers in Allwinner A23/A80 SoCs,
59 * Rockchip RK3328 SoC, NXP i.MX7 SoCs and Xilinx Zynq UltraScale+ SoCs.
60 *
61 * The DRAM controller in Allwinner A23/A80 SoCs and NXP i.MX7 SoCs seems
62 * to be older than the one in Allwinner H6, as the DRAMTMG9 register
63 * is missing in these SoCs. (From the product specifications of these
64 * SoCs they're not capable of DDR4)
65 *
66 * Information sources:
67 * - dram_sun9i.h and dram_sun8i_a23.h in the same directory.
68 * - sdram_rk3328.h from the RK3328 TPL DRAM patchset
69 * - i.MX 7Solo Applications Processor Reference Manual (IMX7SRM)
70 * - Zynq UltraScale+ MPSoC Register Reference (UG1087)
71 */
72 struct sunxi_mctl_ctl_reg {
73 u32 mstr; /* 0x000 */
74 u32 statr; /* 0x004 unused */
75 u32 mstr1; /* 0x008 unused */
76 u32 unk_0x00c; /* 0x00c */
77 u32 mrctrl0; /* 0x010 unused */
78 u32 mrctrl1; /* 0x014 unused */
79 u32 mrstatr; /* 0x018 unused */
80 u32 mrctrl2; /* 0x01c unused */
81 u32 derateen; /* 0x020 unused */
82 u32 derateint; /* 0x024 unused */
83 u8 reserved_0x028[8]; /* 0x028 */
84 u32 pwrctl; /* 0x030 unused */
85 u32 pwrtmg; /* 0x034 unused */
86 u32 hwlpctl; /* 0x038 unused */
87 u8 reserved_0x03c[20]; /* 0x03c */
88 u32 rfshctl0; /* 0x050 unused */
89 u32 rfshctl1; /* 0x054 unused */
90 u8 reserved_0x058[8]; /* 0x05c */
91 u32 rfshctl3; /* 0x060 */
92 u32 rfshtmg; /* 0x064 */
93 u8 reserved_0x068[104]; /* 0x068 reserved for ECC&CRC (from ZynqMP) */
94 u32 init[8]; /* 0x0d0 */
95 u32 dimmctl; /* 0x0f0 unused */
96 u32 rankctl; /* 0x0f4 */
97 u8 reserved_0x0f8[8]; /* 0x0f8 */
98 u32 dramtmg[17]; /* 0x100 */
99 u8 reserved_0x144[60]; /* 0x144 */
100 u32 zqctl[3]; /* 0x180 */
101 u32 zqstat; /* 0x18c unused */
102 u32 dfitmg0; /* 0x190 */
103 u32 dfitmg1; /* 0x194 */
104 u32 dfilpcfg[2]; /* 0x198 unused */
105 u32 dfiupd[3]; /* 0x1a0 */
106 u32 reserved_0x1ac; /* 0x1ac */
107 u32 dfimisc; /* 0x1b0 */
108 u32 dfitmg2; /* 0x1b4 unused, may not exist */
109 u8 reserved_0x1b8[8]; /* 0x1b8 */
110 u32 dbictl; /* 0x1c0 */
111 u8 reserved_0x1c4[60]; /* 0x1c4 */
112 u32 addrmap[12]; /* 0x200 */
113 u8 reserved_0x230[16]; /* 0x230 */
114 u32 odtcfg; /* 0x240 */
115 u32 odtmap; /* 0x244 */
116 u8 reserved_0x248[8]; /* 0x248 */
117 u32 sched[2]; /* 0x250 */
118 u8 reserved_0x258[180]; /* 0x258 */
119 u32 dbgcmd; /* 0x30c unused */
120 u32 dbgstat; /* 0x310 unused */
121 u8 reserved_0x314[12]; /* 0x314 */
122 u32 swctl; /* 0x320 */
123 u32 swstat; /* 0x324 */
124 };
125 check_member(sunxi_mctl_ctl_reg, swstat, 0x324);
126
127 #define MSTR_DEVICETYPE_DDR3 BIT(0)
128 #define MSTR_DEVICETYPE_LPDDR2 BIT(2)
129 #define MSTR_DEVICETYPE_LPDDR3 BIT(3)
130 #define MSTR_DEVICETYPE_DDR4 BIT(4)
131 #define MSTR_DEVICETYPE_MASK GENMASK(5, 0)
132 #define MSTR_2TMODE BIT(10)
133 #define MSTR_BUSWIDTH_FULL (0 << 12)
134 #define MSTR_BUSWIDTH_HALF (1 << 12)
135 #define MSTR_ACTIVE_RANKS(x) (((x == 2) ? 3 : 1) << 24)
136 #define MSTR_BURST_LENGTH(x) (((x) >> 1) << 16)
137
138 /*
139 * The following register information is based on Zynq UltraScale+
140 * MPSoC Register Reference, as it's the currently only known
141 * DDR PHY similar to the one used in H6; however although the
142 * map is similar, the bit fields definitions are different.
143 *
144 * Other DesignWare DDR PHY's have similar register names, but the
145 * offset and definitions are both different.
146 */
147 struct sunxi_mctl_phy_reg {
148 u32 ver; /* 0x000 guess based on similar PHYs */
149 u32 pir; /* 0x004 */
150 u8 reserved_0x008[8]; /* 0x008 */
151 /*
152 * The ZynqMP manual didn't document PGCR1, however this register
153 * exists on H6 and referenced by libdram.
154 */
155 u32 pgcr[8]; /* 0x010 */
156 /*
157 * By comparing the hardware and the ZynqMP manual, the PGSR seems
158 * to start at 0x34 on H6.
159 */
160 u8 reserved_0x030[4]; /* 0x030 */
161 u32 pgsr[3]; /* 0x034 */
162 u32 ptr[7]; /* 0x040 */
163 /*
164 * According to ZynqMP reference there's PLLCR0~6 in this area,
165 * but they're tagged "Type B PLL Only" and H6 seems to have
166 * no them.
167 * 0x080 is not present in ZynqMP reference but it seems to be
168 * present on H6.
169 */
170 u8 reserved_0x05c[36]; /* 0x05c */
171 u32 unk_0x080; /* 0x080 */
172 u8 reserved_0x084[4]; /* 0x084 */
173 u32 dxccr; /* 0x088 */
174 u8 reserved_0x08c[4]; /* 0x08c */
175 u32 dsgcr; /* 0x090 */
176 u8 reserved_0x094[4]; /* 0x094 */
177 u32 odtcr; /* 0x098 */
178 u8 reserved_0x09c[4]; /* 0x09c */
179 u32 aacr; /* 0x0a0 */
180 u8 reserved_0x0a4[32]; /* 0x0a4 */
181 u32 gpr1; /* 0x0c4 */
182 u8 reserved_0x0c8[56]; /* 0x0c8 */
183 u32 dcr; /* 0x100 */
184 u8 reserved_0x104[12]; /* 0x104 */
185 u32 dtpr[7]; /* 0x110 */
186 u8 reserved_0x12c[20]; /* 0x12c */
187 u32 rdimmgcr[3]; /* 0x140 */
188 u8 reserved_0x14c[4]; /* 0x14c */
189 u32 rdimmcr[5]; /* 0x150 */
190 u8 reserved_0x164[4]; /* 0x164 */
191 u32 schcr[2]; /* 0x168 */
192 u8 reserved_0x170[16]; /* 0x170 */
193 /*
194 * The ZynqMP manual documents MR0~7, 11~14 and 22.
195 */
196 u32 mr[23]; /* 0x180 */
197 u8 reserved_0x1dc[36]; /* 0x1dc */
198 u32 dtcr[2]; /* 0x200 */
199 u32 dtar[3]; /* 0x208 */
200 u8 reserved_0x214[4]; /* 0x214 */
201 u32 dtdr[2]; /* 0x218 */
202 u8 reserved_0x220[16]; /* 0x220 */
203 u32 dtedr0; /* 0x230 */
204 u32 dtedr1; /* 0x234 */
205 u32 dtedr2; /* 0x238 */
206 u32 vtdr; /* 0x23c */
207 u32 catr[2]; /* 0x240 */
208 u8 reserved_0x248[8];
209 u32 dqsdr[3]; /* 0x250 */
210 u32 dtedr3; /* 0x25c */
211 u8 reserved_0x260[160]; /* 0x260 */
212 u32 dcuar; /* 0x300 */
213 u32 dcudr; /* 0x304 */
214 u32 dcurr; /* 0x308 */
215 u32 dculr; /* 0x30c */
216 u32 dcugcr; /* 0x310 */
217 u32 dcutpr; /* 0x314 */
218 u32 dcusr[2]; /* 0x318 */
219 u8 reserved_0x320[444]; /* 0x320 */
220 u32 rankidr; /* 0x4dc */
221 u32 riocr[6]; /* 0x4e0 */
222 u8 reserved_0x4f8[8]; /* 0x4f8 */
223 u32 aciocr[6]; /* 0x500 */
224 u8 reserved_0x518[8]; /* 0x518 */
225 u32 iovcr[2]; /* 0x520 */
226 u32 vtcr[2]; /* 0x528 */
227 u8 reserved_0x530[16]; /* 0x530 */
228 u32 acbdlr[17]; /* 0x540 */
229 u32 aclcdlr; /* 0x584 */
230 u8 reserved_0x588[24]; /* 0x588 */
231 u32 acmdlr[2]; /* 0x5a0 */
232 u8 reserved_0x5a8[216]; /* 0x5a8 */
233 struct {
234 u32 zqcr; /* 0x00 only the first one valid */
235 u32 zqpr[2]; /* 0x04 */
236 u32 zqdr[2]; /* 0x0c */
237 u32 zqor[2]; /* 0x14 */
238 u32 zqsr; /* 0x1c */
239 } zq[2]; /* 0x680, 0x6a0 */
240 u8 reserved_0x6c0[64]; /* 0x6c0 */
241 struct {
242 u32 gcr[7]; /* 0x00 */
243 u8 reserved_0x1c[36]; /* 0x1c */
244 u32 bdlr0; /* 0x40 */
245 u32 bdlr1; /* 0x44 */
246 u32 bdlr2; /* 0x48 */
247 u8 reserved_0x4c[4]; /* 0x4c */
248 u32 bdlr3; /* 0x50 */
249 u32 bdlr4; /* 0x54 */
250 u32 bdlr5; /* 0x58 */
251 u8 reserved_0x5c[4]; /* 0x5c */
252 u32 bdlr6; /* 0x60 */
253 u8 reserved_0x64[28]; /* 0x64 */
254 u32 lcdlr[6]; /* 0x80 */
255 u8 reserved_0x98[8]; /* 0x98 */
256 u32 mdlr[2]; /* 0xa0 */
257 u8 reserved_0xa8[24]; /* 0xa8 */
258 u32 gtr0; /* 0xc0 */
259 u8 reserved_0xc4[12]; /* 0xc4 */
260 /*
261 * DXnRSR0 is not documented in ZynqMP manual but
262 * it's used in libdram.
263 */
264 u32 rsr[4]; /* 0xd0 */
265 u32 gsr[4]; /* 0xe0 */
266 u8 reserved_0xf0[16]; /* 0xf0 */
267 } dx[4]; /* 0x700, 0x800, 0x900, 0xa00 */
268 };
269 check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0);
270
271 #define PIR_INIT BIT(0)
272 #define PIR_ZCAL BIT(1)
273 #define PIR_CA BIT(2)
274 #define PIR_PLLINIT BIT(4)
275 #define PIR_DCAL BIT(5)
276 #define PIR_PHYRST BIT(6)
277 #define PIR_DRAMRST BIT(7)
278 #define PIR_DRAMINIT BIT(8)
279 #define PIR_WL BIT(9)
280 #define PIR_QSGATE BIT(10)
281 #define PIR_WLADJ BIT(11)
282 #define PIR_RDDSKW BIT(12)
283 #define PIR_WRDSKW BIT(13)
284 #define PIR_RDEYE BIT(14)
285 #define PIR_WREYE BIT(15)
286 #define PIR_VREF BIT(17)
287 #define PIR_CTLDINIT BIT(18)
288 #define PIR_DQS2DQ BIT(20)
289 #define PIR_DCALPSE BIT(29)
290 #define PIR_ZCALBYP BIT(30)
291
292 #define DCR_LPDDR3 (1 << 0)
293 #define DCR_DDR3 (3 << 0)
294 #define DCR_DDR4 (4 << 0)
295 #define DCR_DDR8BANK BIT(3)
296 #define DCR_DDR2T BIT(28)
297
298 /*
299 * The delay parameters allow to allegedly specify delay times of some
300 * unknown unit for each individual bit trace in each of the four data bytes
301 * the 32-bit wide access consists of. Also three control signals can be
302 * adjusted individually.
303 */
304 #define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
305 /* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable and DQSN */
306 #define WR_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 4)
307 /*
308 * The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable, DQSN,
309 * Termination and Power down
310 */
311 #define RD_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 6)
312 struct dram_para {
313 u32 clk;
314 enum sunxi_dram_type type;
315 u8 cols;
316 u8 rows;
317 u8 ranks;
318 u8 bus_full_width;
319 const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE];
320 const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
321 };
322
323
ns_to_t(int nanoseconds)324 static inline int ns_to_t(int nanoseconds)
325 {
326 const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
327
328 return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
329 }
330
331 void mctl_set_timing_params(struct dram_para *para);
332
333 #endif /* _SUNXI_DRAM_SUN50I_H6_H */
334