| /external/arm-trusted-firmware/services/std_svc/sdei/ |
| D | sdei_intr_mgmt.c | 37 uint64_t elr_el3; member
173 disp_ctx->elr_el3 = read_ctx_reg(tgt_el3, CTX_ELR_EL3); in save_event_ctx()
193 write_ctx_reg(tgt_el3, CTX_ELR_EL3, disp_ctx->elr_el3); in restore_event_ctx()
256 SMC_SET_GP(ctx, CTX_GPREG_X2, disp_ctx->elr_el3); in setup_ns_dispatch()
669 write_elr_el2(disp_ctx->elr_el3); in sdei_event_complete()
673 write_elr_el1(disp_ctx->elr_el3); in sdei_event_complete()
|
| /external/arm-trusted-firmware/bl32/tsp/ |
| D | tsp_interrupt.c | 29 void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3) in tsp_update_sync_sel1_intr_stats() argument
40 read_mpidr(), elr_el3); in tsp_update_sync_sel1_intr_stats()
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| D | tsp_private.h | 100 void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3);
|
| /external/arm-trusted-firmware/plat/nvidia/tegra/common/ |
| D | tegra_fiq_glue.c | 78 fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3)); in tegra_fiq_interrupt_handler()
166 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3)); in tegra_fiq_get_intr_context()
|
| /external/arm-trusted-firmware/lib/cpus/aarch64/ |
| D | wa_cve_2017_5715_bpiall.S | 58 mrs x7, elr_el3
85 msr elr_el3, x11
277 msr elr_el3, x7
|
| D | neoverse_n1.S | 545 mrs x3, elr_el3
547 msr elr_el3, x3
|
| /external/arm-trusted-firmware/bl31/aarch64/ |
| D | runtime_exceptions.S | 144 mrs x1, elr_el3
401 mrs x17, elr_el3
490 mrs x4, elr_el3
|
| D | ea_delegate.S | 244 mrs x3, elr_el3
297 msr elr_el3, x2
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| D | crash_reporting.S | 285 mrs x15, elr_el3
|
| /external/u-boot/arch/arm/cpu/armv8/ |
| D | exceptions.S | 79 mrs x2, elr_el3
103 3: msr elr_el3, x2
|
| D | psci.S | 113 mrs x15, elr_el3
120 msr elr_el3, x15
|
| /external/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/ |
| D | tegra_gic.h | 17 uint64_t elr_el3; member
|
| /external/arm-trusted-firmware/bl1/aarch64/ |
| D | bl1_exceptions.S | 182 msr elr_el3, x0
271 mrs x17, elr_el3
|
| /external/arm-trusted-firmware/bl2/aarch64/ |
| D | bl2_el3_entrypoint.S | 99 msr elr_el3, x0
|
| /external/u-boot/arch/arm/include/asm/ |
| D | macro.h | 207 msr elr_el3, \ep
226 msr elr_el3, \ep
|
| /external/arm-trusted-firmware/plat/hisilicon/hikey/aarch64/ |
| D | hikey_helpers.S | 117 mrs x4, elr_el3
|
| /external/arm-trusted-firmware/plat/hisilicon/hikey960/aarch64/ |
| D | hikey960_helpers.S | 121 mrs x4, elr_el3
|
| /external/arm-trusted-firmware/plat/renesas/rcar/aarch64/ |
| D | plat_helpers.S | 190 msr elr_el3, x0
|
| /external/arm-trusted-firmware/include/arch/aarch64/ |
| D | arch_helpers.h | 248 DEFINE_SYSREG_RW_FUNCS(elr_el3) in DEFINE_SYSREG_READ_FUNC()
|
| /external/arm-trusted-firmware/lib/el3_runtime/aarch64/ |
| D | context.S | 506 msr elr_el3, x17
|
| /external/capstone/suite/MC/AArch64/ |
| D | basic-a64-instructions.s.cs | 1562 0x2c,0x40,0x1e,0xd5 = msr elr_el3, x12
1874 0x29,0x40,0x3e,0xd5 = mrs x9, elr_el3
|
| /external/arm-trusted-firmware/docs/design/ |
| D | interrupt-framework-design.rst | 786 now be handled by the SP. ``x1`` is written with the value of ``elr_el3``
|
| D | firmware-design.rst | 1218 elr_el3 :0x000000000400C0CC
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | basic-a64-instructions.txt | 3288 # CHECK: msr {{elr_el3|ELR_EL3}}, x12
3580 # CHECK: mrs x9, {{elr_el3|ELR_EL3}}
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | basic-a64-instructions.txt | 3272 # CHECK: msr {{elr_el3|ELR_EL3}}, x12
3565 # CHECK: mrs x9, {{elr_el3|ELR_EL3}}
|