| /external/arm-trusted-firmware/drivers/arm/gic/v3/ |
| D | arm_gicv3_common.c | 30 uintptr_t gicr_base = 0; in arm_gicv3_distif_pre_save() local
41 gicr_base = gicv3_driver_data->rdistif_base_addrs[i]; in arm_gicv3_distif_pre_save()
42 assert(gicr_base); in arm_gicv3_distif_pre_save()
43 assert(gicr_read_waker(gicr_base) & WAKER_CA_BIT); in arm_gicv3_distif_pre_save()
44 assert(gicr_read_waker(gicr_base) & WAKER_PS_BIT); in arm_gicv3_distif_pre_save()
47 gicr_base = gicv3_driver_data->rdistif_base_addrs[rdist_proc_num]; in arm_gicv3_distif_pre_save()
61 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_SL_BIT); in arm_gicv3_distif_pre_save()
64 while (!(gicr_read_waker(gicr_base) & WAKER_QSC_BIT)) in arm_gicv3_distif_pre_save()
74 uintptr_t gicr_base; in arm_gicv3_distif_post_restore() local
84 gicr_base = gicv3_driver_data->rdistif_base_addrs[rdist_proc_num]; in arm_gicv3_distif_post_restore()
[all …]
|
| D | gicv3_main.c | 97 if (plat_driver_data->gicr_base != 0U) { in gicv3_driver_init()
106 plat_driver_data->gicr_base, in gicv3_driver_init()
186 uintptr_t gicr_base; in gicv3_rdistif_init() local
203 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in gicv3_rdistif_init()
204 assert(gicr_base != 0U); in gicv3_rdistif_init()
207 gicv3_ppi_sgi_config_defaults(gicr_base); in gicv3_rdistif_init()
209 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base, in gicv3_rdistif_init()
237 uintptr_t gicr_base; in gicv3_cpuif_enable() local
247 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in gicv3_cpuif_enable()
248 gicv3_rdistif_mark_core_awake(gicr_base); in gicv3_cpuif_enable()
[all …]
|
| D | gicv3_helpers.c | 279 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base) in gicv3_rdistif_mark_core_awake() argument
285 assert((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U); in gicv3_rdistif_mark_core_awake()
288 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT); in gicv3_rdistif_mark_core_awake()
291 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U) in gicv3_rdistif_mark_core_awake()
300 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base) in gicv3_rdistif_mark_core_asleep() argument
303 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT); in gicv3_rdistif_mark_core_asleep()
306 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U) in gicv3_rdistif_mark_core_asleep()
318 uintptr_t gicr_base, in gicv3_rdistif_base_addrs_probe() argument
324 uintptr_t rdistif_base = gicr_base; in gicv3_rdistif_base_addrs_probe()
444 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base) in gicv3_ppi_sgi_config_defaults() argument
[all …]
|
| D | gic600.c | 111 uintptr_t gicr_base; in gicv3_rdistif_off() local
117 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in gicv3_rdistif_off()
118 assert(gicr_base); in gicv3_rdistif_off()
121 gic600_pwr_off(gicr_base); in gicv3_rdistif_off()
129 uintptr_t gicr_base; in gicv3_rdistif_on() local
135 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in gicv3_rdistif_on()
136 assert(gicr_base); in gicv3_rdistif_on()
139 gic600_pwr_on(gicr_base); in gicv3_rdistif_on()
|
| D | gicv3_private.h | 99 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base);
100 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
108 uintptr_t gicr_base,
110 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base);
111 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base);
200 static inline void gicr_wait_for_pending_write(uintptr_t gicr_base) in gicr_wait_for_pending_write() argument
202 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) != 0U) in gicr_wait_for_pending_write()
206 static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base) in gicr_wait_for_upstream_pending_write() argument
208 while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT) != 0U) in gicr_wait_for_upstream_pending_write()
|
| /external/arm-trusted-firmware/plat/mediatek/mt8183/ |
| D | plat_mt_gic.c | 34 .gicr_base = MT_GIC_RDIST_BASE,
85 uintptr_t gicr_base; in mt_gic_rdistif_init() local
88 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in mt_gic_rdistif_init()
91 mmio_write_32(gicr_base + GICR_IGROUPR0, ~0U); in mt_gic_rdistif_init()
92 mmio_write_32(gicr_base + GICR_IGRPMODR0, 0x0); in mt_gic_rdistif_init()
96 gicr_write_ipriorityr(gicr_base, index, in mt_gic_rdistif_init()
113 uintptr_t gicr_base; in mt_gic_rdistif_save() local
116 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; in mt_gic_rdistif_save()
118 gic_data.saved_group = mmio_read_32(gicr_base + GICR_IGROUPR0); in mt_gic_rdistif_save()
119 gic_data.saved_enable = mmio_read_32(gicr_base + GICR_ISENABLER0); in mt_gic_rdistif_save()
[all …]
|
| /external/arm-trusted-firmware/plat/ti/k3/common/ |
| D | k3_gicv3.c | 45 uintptr_t gicr_base = 0; in k3_gic_driver_init() local
52 gicr_base = gicr_check; in k3_gic_driver_init()
57 assert(gicr_base != 0); in k3_gic_driver_init()
66 k3_gic_data.gicr_base = gicr_base; in k3_gic_driver_init()
|
| /external/arm-trusted-firmware/plat/socionext/uniphier/ |
| D | uniphier_gicv3.c | 62 .gicr_base = 0x5fe40000,
71 .gicr_base = 0x5fe80000,
80 .gicr_base = 0x5fe80000,
|
| /external/arm-trusted-firmware/plat/qemu/common/ |
| D | qemu_gicv3.c | 26 .gicr_base = GICR_BASE,
|
| /external/arm-trusted-firmware/plat/rockchip/common/ |
| D | rockchip_gicv3.c | 40 .gicr_base = PLAT_RK_GICR_BASE,
|
| /external/arm-trusted-firmware/plat/socionext/synquacer/ |
| D | sq_gicv3.c | 61 .gicr_base = PLAT_SQ_GICR_BASE,
|
| /external/arm-trusted-firmware/plat/marvell/common/ |
| D | marvell_gicv3.c | 66 .gicr_base = PLAT_MARVELL_GICR_BASE,
|
| /external/arm-trusted-firmware/plat/xilinx/versal/ |
| D | versal_gicv3.c | 64 .gicr_base = PLAT_VERSAL_GICR_BASE,
|
| /external/arm-trusted-firmware/plat/imx/common/ |
| D | plat_imx8_gic.c | 34 .gicr_base = PLAT_GICR_BASE,
|
| /external/arm-trusted-firmware/plat/arm/common/ |
| D | arm_gicv3.c | 79 .gicr_base = 0U,
|
| /external/arm-trusted-firmware/include/drivers/arm/ |
| D | gicv3.h | 313 uintptr_t gicr_base; member
|