| /external/u-boot/drivers/ddr/marvell/axp/ |
| D | ddr3_init.c | 1143 u32 tmp, hclk; in get_target_freq() local
1147 hclk = 84; in get_target_freq()
1160 hclk = 150; in get_target_freq()
1166 hclk = 165; in get_target_freq()
1170 hclk = 180; in get_target_freq()
1177 hclk = 200; in get_target_freq()
1182 hclk = 222; in get_target_freq()
1188 hclk = 250; in get_target_freq()
1194 hclk = 267; in get_target_freq()
1200 hclk = 300; in get_target_freq()
[all …]
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| D | ddr3_dfs.c | 126 u32 hclk; in ddr3_dfs_high_2_low() local
128 get_target_freq(cpu_freq, &tmp, &hclk); in ddr3_dfs_high_2_low()
782 u32 hclk; in ddr3_dfs_low_2_high() local
784 get_target_freq(cpu_freq, &tmp, &hclk); in ddr3_dfs_low_2_high()
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| /external/u-boot/drivers/mtd/nand/raw/ |
| D | lpc32xx_nand_slc.c | 112 uint32_t hclk = get_hclk_clk_rate(); in lpc32xx_nand_init() local
127 TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) | in lpc32xx_nand_init()
128 TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) | in lpc32xx_nand_init()
129 TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) | in lpc32xx_nand_init()
131 TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) | in lpc32xx_nand_init()
132 TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) | in lpc32xx_nand_init()
133 TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP), in lpc32xx_nand_init()
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| /external/u-boot/arch/arm/mach-s5pc1xx/ |
| D | clock.c | 217 unsigned long hclk; in get_hclk_sys() local
236 hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1); in get_hclk_sys()
238 return hclk; in get_hclk_sys()
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| /external/u-boot/arch/arm/dts/ |
| D | zynqmp-clk-ccf.dtsi | 178 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
184 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
190 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
196 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
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| D | at91sam9261.dtsi | 78 clock-names = "ohci_clk", "hclk", "uhpck";
89 clock-names = "lcdc_clk", "hclk";
131 clock-names = "pclk", "hclk";
714 hclk0: hclk@16 {
720 hclk1: hclk@17 {
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| D | at91sam9x5_macb1.dtsi | 50 clock-names = "hclk", "pclk";
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| D | sama5d3_emac.dtsi | 50 clock-names = "hclk", "pclk";
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| D | at91sam9x5_macb0.dtsi | 62 clock-names = "hclk", "pclk";
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| D | mt8518.dtsi | 84 clock-names = "source", "hclk", "source_cg";
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| D | mt8516.dtsi | 122 clock-names = "source", "hclk", "source_cg";
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| D | zynq-7000.dtsi | 249 clock-names = "pclk", "hclk", "tx_clk";
260 clock-names = "pclk", "hclk", "tx_clk";
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| D | mt7623.dtsi | 238 clock-names = "source", "hclk";
248 clock-names = "source", "hclk";
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| D | sama5d3_gmac.dtsi | 83 clock-names = "hclk", "pclk";
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| D | at91sam9263.dtsi | 874 clock-names = "hclk", "pclk";
883 clock-names = "pclk", "hclk";
1008 clock-names = "lcdc_clk", "hclk";
1035 clock-names = "ohci_clk", "hclk", "uhpck";
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| D | zynqmp.dtsi | 575 clock-names = "pclk", "hclk", "tx_clk";
589 clock-names = "pclk", "hclk", "tx_clk";
603 clock-names = "pclk", "hclk", "tx_clk";
617 clock-names = "pclk", "hclk", "tx_clk";
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| D | at91sam9g45.dtsi | 984 clock-names = "hclk", "pclk";
1168 clock-names = "pclk", "hclk";
1280 clock-names = "hclk", "lcdc_clk";
1308 clock-names = "ohci_clk", "hclk", "uhpck";
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| D | at91sam9260.dtsi | 868 clock-names = "hclk", "pclk";
877 clock-names = "pclk", "hclk";
1030 clock-names = "ohci_clk", "hclk", "uhpck";
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| D | sama5d2.dtsi | 39 clock-names = "ohci_clk", "hclk", "uhpck";
637 clock-names = "hclk", "pclk";
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| D | sam9x60.dtsi | 91 clock-names = "hclk", "pclk";
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| /external/u-boot/board/menlo/m53menlo/ |
| D | m53menlo.c | 168 static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk) in enable_lvds_clock() argument
180 ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK); in enable_lvds_clock()
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| /external/u-boot/doc/device-tree-bindings/clock/ |
| D | nvidia,tegra20-car.txt | 140 109 hclk
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| /external/arm-trusted-firmware/drivers/st/fmc/ |
| D | stm32_fmc2_nand.c | 157 unsigned long hclk = stm32mp_clk_get_rate(stm32_fmc2.clock_id); in stm32_fmc2_nand_setup_timing() local
158 unsigned long hclkp = FMC2_PSEC_PER_MSEC / (hclk / 1000U); in stm32_fmc2_nand_setup_timing()
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| /external/u-boot/arch/mips/dts/ |
| D | mt7628a.dtsi | 401 clock-names = "source", "hclk";
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| /external/u-boot/arch/riscv/dts/ |
| D | fu540-c000.dtsi | 224 clock-names = "pclk", "hclk";
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