1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Menlosystems M53Menlo board
4 *
5 * Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
6 * Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
7 */
8
9 #include <common.h>
10 #include <dm.h>
11 #include <init.h>
12 #include <asm/io.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/arch/crm_regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/iomux-mx53.h>
18 #include <asm/mach-imx/mx5_video.h>
19 #include <asm/mach-imx/video.h>
20 #include <asm/gpio.h>
21 #include <asm/spl.h>
22 #include <env.h>
23 #include <fdt_support.h>
24 #include <fsl_esdhc_imx.h>
25 #include <gzip.h>
26 #include <i2c.h>
27 #include <ipu_pixfmt.h>
28 #include <linux/errno.h>
29 #include <linux/fb.h>
30 #include <mmc.h>
31 #include <netdev.h>
32 #include <spl.h>
33 #include <splash.h>
34 #include <usb/ehci-ci.h>
35 #include <video_console.h>
36
37 DECLARE_GLOBAL_DATA_PTR;
38
39 static u32 mx53_dram_size[2];
40
board_get_usable_ram_top(ulong total_size)41 ulong board_get_usable_ram_top(ulong total_size)
42 {
43 /*
44 * WARNING: We must override get_effective_memsize() function here
45 * to report only the size of the first DRAM bank. This is to make
46 * U-Boot relocator place U-Boot into valid memory, that is, at the
47 * end of the first DRAM bank. If we did not override this function
48 * like so, U-Boot would be placed at the address of the first DRAM
49 * bank + total DRAM size - sizeof(uboot), which in the setup where
50 * each DRAM bank contains 512MiB of DRAM would result in placing
51 * U-Boot into invalid memory area close to the end of the first
52 * DRAM bank.
53 */
54 return PHYS_SDRAM_2 + mx53_dram_size[1];
55 }
56
dram_init(void)57 int dram_init(void)
58 {
59 mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
60 mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
61
62 gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
63
64 return 0;
65 }
66
dram_init_banksize(void)67 int dram_init_banksize(void)
68 {
69 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
70 gd->bd->bi_dram[0].size = mx53_dram_size[0];
71
72 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
73 gd->bd->bi_dram[1].size = mx53_dram_size[1];
74
75 return 0;
76 }
77
setup_iomux_uart(void)78 static void setup_iomux_uart(void)
79 {
80 static const iomux_v3_cfg_t uart_pads[] = {
81 MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
82 MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
83 };
84
85 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
86 }
87
setup_iomux_fec(void)88 static void setup_iomux_fec(void)
89 {
90 static const iomux_v3_cfg_t fec_pads[] = {
91 /* MDIO pads */
92 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
93 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
94 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
95
96 /* FEC 0 pads */
97 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
98 PAD_CTL_HYS | PAD_CTL_PKE),
99 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
100 PAD_CTL_HYS | PAD_CTL_PKE),
101 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
102 PAD_CTL_HYS | PAD_CTL_PKE),
103 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
104 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
105 PAD_CTL_HYS | PAD_CTL_PKE),
106 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
107 PAD_CTL_HYS | PAD_CTL_PKE),
108 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
109 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
110
111 /* FEC 1 pads */
112 NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
113 PAD_CTL_HYS | PAD_CTL_PKE),
114 NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
115 PAD_CTL_HYS | PAD_CTL_PKE),
116 NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
117 PAD_CTL_HYS | PAD_CTL_PKE),
118 NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
119 PAD_CTL_HYS | PAD_CTL_PKE),
120 NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
121 PAD_CTL_HYS | PAD_CTL_PKE),
122 NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
123 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
124 PAD_CTL_HYS | PAD_CTL_PKE),
125 NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
126 };
127
128 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
129 }
130
131 #ifdef CONFIG_FSL_ESDHC_IMX
132 struct fsl_esdhc_cfg esdhc_cfg = {
133 MMC_SDHC1_BASE_ADDR,
134 };
135
board_mmc_getcd(struct mmc * mmc)136 int board_mmc_getcd(struct mmc *mmc)
137 {
138 imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
139 gpio_direction_input(IMX_GPIO_NR(1, 1));
140
141 return !gpio_get_value(IMX_GPIO_NR(1, 1));
142 }
143
144 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
145 PAD_CTL_PUS_100K_UP)
146 #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
147 PAD_CTL_DSE_HIGH)
148
board_mmc_init(bd_t * bis)149 int board_mmc_init(bd_t *bis)
150 {
151 static const iomux_v3_cfg_t sd1_pads[] = {
152 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
153 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
154 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
155 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
156 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
157 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
158 };
159
160 esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
161
162 imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
163
164 return fsl_esdhc_initialize(bis, &esdhc_cfg);
165 }
166 #endif
167
enable_lvds_clock(struct display_info_t const * dev,const u8 hclk)168 static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
169 {
170 static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
171 int ret;
172
173 /* For ETM0430G0DH6 model, this must be enabled before the clock. */
174 gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
175
176 /*
177 * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
178 * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
179 */
180 ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
181 if (ret)
182 puts("IPU: Failed to configure LDB clock\n");
183
184 /* Configure CCM_CSCMR2 */
185 clrsetbits_le32(&mxc_ccm->cscmr2,
186 (0x7 << 26) | BIT(10) | BIT(8),
187 (0x5 << 26) | BIT(10) | BIT(8));
188
189 /* Configure LDB_CTRL */
190 writel(0x201, 0x53fa8008);
191 }
192
enable_lvds_etm0430g0dh6(struct display_info_t const * dev)193 static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
194 {
195 gpio_request(IMX_GPIO_NR(6, 0), "LCD");
196
197 /* For ETM0430G0DH6 model, this must be enabled before the clock. */
198 gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
199
200 /*
201 * Set LVDS clock to 9 MHz for the display. The PLL4 is set to
202 * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
203 */
204 enable_lvds_clock(dev, 63);
205 }
206
enable_lvds_etm0700g0dh6(struct display_info_t const * dev)207 static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
208 {
209 gpio_request(IMX_GPIO_NR(6, 0), "LCD");
210
211 /*
212 * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
213 * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
214 */
215 enable_lvds_clock(dev, 233);
216
217 /* For ETM0700G0DH6 model, this may be enabled after the clock. */
218 gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
219 }
220
221 static const char *lvds_compat_string;
222
detect_lvds(struct display_info_t const * dev)223 static int detect_lvds(struct display_info_t const *dev)
224 {
225 u8 touchid[23];
226 u8 *touchptr = &touchid[0];
227 int ret;
228
229 ret = i2c_set_bus_num(0);
230 if (ret)
231 return 0;
232
233 /* Touchscreen is at address 0x38, ID register is 0xbb. */
234 ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
235 if (ret)
236 return 0;
237
238 /* EP0430 prefixes the response with 0xbb, skip it. */
239 if (*touchptr == 0xbb)
240 touchptr++;
241
242 /* Skip the 'EP' prefix. */
243 touchptr += 2;
244
245 ret = !memcmp(touchptr, &dev->mode.name[7], 4);
246 if (ret)
247 lvds_compat_string = dev->mode.name;
248
249 return ret;
250 }
251
board_preboot_os(void)252 void board_preboot_os(void)
253 {
254 /* Power off the LCD to prevent awful color flicker */
255 gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
256 }
257
ft_board_setup(void * blob,bd_t * bd)258 int ft_board_setup(void *blob, bd_t *bd)
259 {
260 if (lvds_compat_string)
261 do_fixup_by_path_string(blob, "/panel", "compatible",
262 lvds_compat_string);
263
264 return 0;
265 }
266
267 struct display_info_t const displays[] = {
268 {
269 .bus = 0,
270 .addr = 0,
271 .detect = detect_lvds,
272 .enable = enable_lvds_etm0430g0dh6,
273 .pixfmt = IPU_PIX_FMT_RGB666,
274 .mode = {
275 .name = "edt,etm0430g0dh6",
276 .refresh = 60,
277 .xres = 480,
278 .yres = 272,
279 .pixclock = 111111, /* picosecond (9 MHz) */
280 .left_margin = 2,
281 .right_margin = 2,
282 .upper_margin = 2,
283 .lower_margin = 2,
284 .hsync_len = 41,
285 .vsync_len = 10,
286 .sync = 0x40000000,
287 .vmode = FB_VMODE_NONINTERLACED
288 }
289 }, {
290 .bus = 0,
291 .addr = 0,
292 .detect = detect_lvds,
293 .enable = enable_lvds_etm0700g0dh6,
294 .pixfmt = IPU_PIX_FMT_RGB666,
295 .mode = {
296 .name = "edt,etm0700g0dh6",
297 .refresh = 60,
298 .xres = 800,
299 .yres = 480,
300 .pixclock = 30048, /* picosecond (33.28 MHz) */
301 .left_margin = 40,
302 .right_margin = 88,
303 .upper_margin = 10,
304 .lower_margin = 33,
305 .hsync_len = 128,
306 .vsync_len = 2,
307 .sync = FB_SYNC_EXT,
308 .vmode = FB_VMODE_NONINTERLACED
309 }
310 }
311 };
312
313 size_t display_count = ARRAY_SIZE(displays);
314
315 #ifdef CONFIG_SPLASH_SCREEN
316 static struct splash_location default_splash_locations[] = {
317 {
318 .name = "mmc_fs",
319 .storage = SPLASH_STORAGE_MMC,
320 .flags = SPLASH_STORAGE_FS,
321 .devpart = "0:1",
322 },
323 };
324
splash_screen_prepare(void)325 int splash_screen_prepare(void)
326 {
327 return splash_source_load(default_splash_locations,
328 ARRAY_SIZE(default_splash_locations));
329 }
330 #endif
331
board_late_init(void)332 int board_late_init(void)
333 {
334 #if defined(CONFIG_VIDEO_IPUV3)
335 struct udevice *dev;
336 int xpos, ypos, ret;
337 char *s;
338 void *dst;
339 ulong addr, len;
340
341 splash_get_pos(&xpos, &ypos);
342
343 s = env_get("splashimage");
344 if (!s)
345 return 0;
346
347 addr = simple_strtoul(s, NULL, 16);
348 dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
349 if (!dst)
350 return -ENOMEM;
351
352 ret = splash_screen_prepare();
353 if (ret < 0)
354 return ret;
355
356 len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
357 ret = gunzip(dst + 2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE - 2,
358 (uchar *)addr, &len);
359 if (ret) {
360 printf("Error: no valid bmp or bmp.gz image at %lx\n", addr);
361 free(dst);
362 return ret;
363 }
364
365 ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
366 if (ret)
367 return ret;
368
369 ret = video_bmp_display(dev, (ulong)dst + 2, xpos, ypos, true);
370 if (ret)
371 return ret;
372 #endif
373 return 0;
374 }
375
376 #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
377 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
378
setup_iomux_i2c(void)379 static void setup_iomux_i2c(void)
380 {
381 static const iomux_v3_cfg_t i2c_pads[] = {
382 /* I2C1 */
383 NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
384 NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
385 /* I2C2 */
386 NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
387 NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
388 };
389
390 imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
391 }
392
setup_iomux_video(void)393 static void setup_iomux_video(void)
394 {
395 static const iomux_v3_cfg_t lcd_pads[] = {
396 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
397 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
398 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
399 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
400 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
401 };
402
403 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
404 }
405
setup_iomux_nand(void)406 static void setup_iomux_nand(void)
407 {
408 static const iomux_v3_cfg_t nand_pads[] = {
409 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
410 PAD_CTL_DSE_HIGH),
411 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
412 PAD_CTL_DSE_HIGH),
413 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
414 PAD_CTL_DSE_HIGH),
415 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
416 PAD_CTL_DSE_HIGH),
417 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
418 PAD_CTL_PUS_100K_UP),
419 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
420 PAD_CTL_PUS_100K_UP),
421 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
422 PAD_CTL_DSE_HIGH),
423 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
424 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
425 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
426 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
427 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
428 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
429 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
430 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
431 NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
432 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
433 NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
434 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
435 NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
436 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
437 NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
438 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
439 };
440
441 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
442 }
443
m53_set_clock(void)444 static void m53_set_clock(void)
445 {
446 int ret;
447 const u32 ref_clk = MXC_HCLK;
448 const u32 dramclk = 400;
449 u32 cpuclk;
450
451 gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK");
452
453 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
454 PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
455 gpio_direction_input(IMX_GPIO_NR(4, 0));
456
457 /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
458 cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
459
460 ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
461 if (ret)
462 printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk);
463
464 ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
465 if (ret) {
466 printf("CPU: Switch peripheral clock to %dMHz failed\n",
467 dramclk);
468 }
469
470 ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
471 if (ret)
472 printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);
473 }
474
m53_set_nand(void)475 static void m53_set_nand(void)
476 {
477 u32 i;
478
479 /* NAND flash is muxed on ATA pins */
480 setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
481
482 /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
483 for (i = 0x4; i < 0x94; i += 0x18) {
484 clrbits_le32(WEIM_BASE_ADDR + i,
485 WEIM_GCR2_MUX16_BYP_GRANT_MASK);
486 }
487
488 mxc_set_clock(0, 33, MXC_NFC_CLK);
489 enable_nfc_clk(1);
490 }
491
board_early_init_f(void)492 int board_early_init_f(void)
493 {
494 setup_iomux_uart();
495 setup_iomux_fec();
496 setup_iomux_i2c();
497 setup_iomux_nand();
498 setup_iomux_video();
499
500 m53_set_clock();
501
502 mxc_set_sata_internal_clock();
503
504 /* NAND clock @ 33MHz */
505 m53_set_nand();
506
507 return 0;
508 }
509
board_init(void)510 int board_init(void)
511 {
512 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
513
514 return 0;
515 }
516
checkboard(void)517 int checkboard(void)
518 {
519 puts("Board: Menlosystems M53Menlo\n");
520
521 return 0;
522 }
523
524 /*
525 * NAND SPL
526 */
527 #ifdef CONFIG_SPL_BUILD
spl_board_init(void)528 void spl_board_init(void)
529 {
530 setup_iomux_nand();
531 m53_set_clock();
532 m53_set_nand();
533 }
534
spl_boot_device(void)535 u32 spl_boot_device(void)
536 {
537 return BOOT_DEVICE_NAND;
538 }
539 #endif
540