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Searched refs:io_base (Results 1 – 10 of 10) sorted by relevance

/external/u-boot/drivers/video/meson/
Dmeson_vpu_init.c26 writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL)); in meson_vpp_setup_mux()
48 priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX)); in meson_vpp_write_scaling_filter_coefs()
51 priv->io_base + _REG(VPP_OSD_SCALE_COEF)); in meson_vpp_write_scaling_filter_coefs()
73 priv->io_base + _REG(VPP_SCALE_COEF_IDX)); in meson_vpp_write_vd_scaling_filter_coefs()
76 priv->io_base + _REG(VPP_SCALE_COEF)); in meson_vpp_write_vd_scaling_filter_coefs()
122 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
124 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
126 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF00_01)); in meson_viu_set_g12a_osd1_matrix()
128 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF02_10)); in meson_viu_set_g12a_osd1_matrix()
130 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12)); in meson_viu_set_g12a_osd1_matrix()
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Dmeson_venc.c844 priv->io_base + _REG(VENC_VDAC_SETTING)); in meson_venc_hdmi_mode_set()
846 writel(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in meson_venc_hdmi_mode_set()
847 writel(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in meson_venc_hdmi_mode_set()
857 priv->io_base + _REG(ENCI_CFILT_CTRL)); in meson_venc_hdmi_mode_set()
860 priv->io_base + _REG(ENCI_CFILT_CTRL2)); in meson_venc_hdmi_mode_set()
863 writel(0, priv->io_base + _REG(VENC_DVI_SETTING)); in meson_venc_hdmi_mode_set()
866 writel(0, priv->io_base + _REG(ENCI_VIDEO_MODE)); in meson_venc_hdmi_mode_set()
867 writel(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); in meson_venc_hdmi_mode_set()
871 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN)); in meson_venc_hdmi_mode_set()
873 priv->io_base + _REG(ENCI_SYNC_HSO_END)); in meson_venc_hdmi_mode_set()
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Dmeson_plane.c61 priv->io_base + _REG(VPP_OSD_SC_CTRL0)); in meson_vpp_setup_interlace_vscaler_osd1()
64 priv->io_base + _REG(VPP_OSD_SCI_WH_M1)); in meson_vpp_setup_interlace_vscaler_osd1()
67 priv->io_base + _REG(VPP_OSD_SCO_H_START_END)); in meson_vpp_setup_interlace_vscaler_osd1()
69 priv->io_base + _REG(VPP_OSD_SCO_V_START_END)); in meson_vpp_setup_interlace_vscaler_osd1()
72 writel(BIT(16), priv->io_base + _REG(VPP_OSD_VSC_INI_PHASE)); in meson_vpp_setup_interlace_vscaler_osd1()
73 writel(BIT(25), priv->io_base + _REG(VPP_OSD_VSC_PHASE_STEP)); in meson_vpp_setup_interlace_vscaler_osd1()
75 writel(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0)); in meson_vpp_setup_interlace_vscaler_osd1()
84 priv->io_base + _REG(VPP_OSD_VSC_CTRL0)); in meson_vpp_setup_interlace_vscaler_osd1()
90 writel(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0)); in meson_vpp_disable_interlace_vscaler_osd1()
91 writel(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0)); in meson_vpp_disable_interlace_vscaler_osd1()
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Dmeson_vpu.c105 priv->io_base = dev_remap_addr_index(dev, 0); in meson_vpu_probe()
106 if (!priv->io_base) in meson_vpu_probe()
Dmeson_vpu.h36 void __iomem *io_base; member
/external/u-boot/drivers/mtd/nand/raw/
Dstm32_fmc2_nand.c163 void __iomem *io_base; member
184 u32 pcr = readl(fmc2->io_base + FMC2_PCR); in stm32_fmc2_timings_init()
205 writel(pcr, fmc2->io_base + FMC2_PCR); in stm32_fmc2_timings_init()
206 writel(pmem, fmc2->io_base + FMC2_PMEM); in stm32_fmc2_timings_init()
207 writel(patt, fmc2->io_base + FMC2_PATT); in stm32_fmc2_timings_init()
214 u32 pcr = readl(fmc2->io_base + FMC2_PCR); in stm32_fmc2_setup()
235 writel(pcr, fmc2->io_base + FMC2_PCR); in stm32_fmc2_setup()
265 u32 pcr = readl(fmc2->io_base + FMC2_PCR); in stm32_fmc2_set_buswidth_16()
270 writel(pcr, fmc2->io_base + FMC2_PCR); in stm32_fmc2_set_buswidth_16()
276 u32 pcr = readl(fmc2->io_base + FMC2_PCR); in stm32_fmc2_set_ecc()
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/external/u-boot/drivers/pci/
Dpci_ftpci100.c20 unsigned int io_base; member
64 if (priv->io_base & size_mask) in setup_pci_bar()
65 priv->io_base = (priv->io_base & ~size_mask) + \ in setup_pci_bar()
68 devs[priv->ndevs].bar[i].addr = priv->io_base; in setup_pci_bar()
73 priv->io_base); in setup_pci_bar()
77 priv->io_base, in setup_pci_bar()
78 priv->io_base + size_mask, bus, dev, func); in setup_pci_bar()
80 priv->io_base += size_mask + 1; in setup_pci_bar()
229 priv->io_base = CONFIG_FTPCI100_BASE + CONFIG_FTPCI100_IO_SIZE; in ftpci_preinit()
/external/crosvm/resources/src/
Dsystem_allocator.rs63 io_base: Option<u64>, in new()
74 io_address_space: if let (Some(b), Some(s)) = (io_base, io_size) { in new()
135 io_base: Option<u64>, field
146 io_base: None, in new()
156 self.io_base = Some(base); in add_io_addresses()
179 self.io_base, in create_allocator()
/external/u-boot/board/imgtec/malta/
Dmalta.c136 ulong io_base; in board_early_init_f() local
141 io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE); in board_early_init_f()
145 io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE); in board_early_init_f()
152 set_io_port_base(io_base); in board_early_init_f()
/external/u-boot/arch/arm/mach-bcm283x/
Dinit.c116 u64 io_base, size; in mach_cpu_init() local
126 &io_base, &size); in mach_cpu_init()
130 rpi_bcm283x_base = io_base; in mach_cpu_init()