1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) STMicroelectronics 2019
4 * Author: Christophe Kerello <christophe.kerello@st.com>
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <nand.h>
11 #include <reset.h>
12 #include <linux/iopoll.h>
13 #include <linux/ioport.h>
14
15 /* Bad block marker length */
16 #define FMC2_BBM_LEN 2
17
18 /* ECC step size */
19 #define FMC2_ECC_STEP_SIZE 512
20
21 /* Command delay */
22 #define FMC2_RB_DELAY_US 30
23
24 /* Max chip enable */
25 #define FMC2_MAX_CE 2
26
27 /* Timings */
28 #define FMC2_THIZ 1
29 #define FMC2_TIO 8000
30 #define FMC2_TSYNC 3000
31 #define FMC2_PCR_TIMING_MASK 0xf
32 #define FMC2_PMEM_PATT_TIMING_MASK 0xff
33
34 /* FMC2 Controller Registers */
35 #define FMC2_BCR1 0x0
36 #define FMC2_PCR 0x80
37 #define FMC2_SR 0x84
38 #define FMC2_PMEM 0x88
39 #define FMC2_PATT 0x8c
40 #define FMC2_HECCR 0x94
41 #define FMC2_BCHISR 0x254
42 #define FMC2_BCHICR 0x258
43 #define FMC2_BCHPBR1 0x260
44 #define FMC2_BCHPBR2 0x264
45 #define FMC2_BCHPBR3 0x268
46 #define FMC2_BCHPBR4 0x26c
47 #define FMC2_BCHDSR0 0x27c
48 #define FMC2_BCHDSR1 0x280
49 #define FMC2_BCHDSR2 0x284
50 #define FMC2_BCHDSR3 0x288
51 #define FMC2_BCHDSR4 0x28c
52
53 /* Register: FMC2_BCR1 */
54 #define FMC2_BCR1_FMC2EN BIT(31)
55
56 /* Register: FMC2_PCR */
57 #define FMC2_PCR_PWAITEN BIT(1)
58 #define FMC2_PCR_PBKEN BIT(2)
59 #define FMC2_PCR_PWID_MASK GENMASK(5, 4)
60 #define FMC2_PCR_PWID(x) (((x) & 0x3) << 4)
61 #define FMC2_PCR_PWID_BUSWIDTH_8 0
62 #define FMC2_PCR_PWID_BUSWIDTH_16 1
63 #define FMC2_PCR_ECCEN BIT(6)
64 #define FMC2_PCR_ECCALG BIT(8)
65 #define FMC2_PCR_TCLR_MASK GENMASK(12, 9)
66 #define FMC2_PCR_TCLR(x) (((x) & 0xf) << 9)
67 #define FMC2_PCR_TCLR_DEFAULT 0xf
68 #define FMC2_PCR_TAR_MASK GENMASK(16, 13)
69 #define FMC2_PCR_TAR(x) (((x) & 0xf) << 13)
70 #define FMC2_PCR_TAR_DEFAULT 0xf
71 #define FMC2_PCR_ECCSS_MASK GENMASK(19, 17)
72 #define FMC2_PCR_ECCSS(x) (((x) & 0x7) << 17)
73 #define FMC2_PCR_ECCSS_512 1
74 #define FMC2_PCR_ECCSS_2048 3
75 #define FMC2_PCR_BCHECC BIT(24)
76 #define FMC2_PCR_WEN BIT(25)
77
78 /* Register: FMC2_SR */
79 #define FMC2_SR_NWRF BIT(6)
80
81 /* Register: FMC2_PMEM */
82 #define FMC2_PMEM_MEMSET(x) (((x) & 0xff) << 0)
83 #define FMC2_PMEM_MEMWAIT(x) (((x) & 0xff) << 8)
84 #define FMC2_PMEM_MEMHOLD(x) (((x) & 0xff) << 16)
85 #define FMC2_PMEM_MEMHIZ(x) (((x) & 0xff) << 24)
86 #define FMC2_PMEM_DEFAULT 0x0a0a0a0a
87
88 /* Register: FMC2_PATT */
89 #define FMC2_PATT_ATTSET(x) (((x) & 0xff) << 0)
90 #define FMC2_PATT_ATTWAIT(x) (((x) & 0xff) << 8)
91 #define FMC2_PATT_ATTHOLD(x) (((x) & 0xff) << 16)
92 #define FMC2_PATT_ATTHIZ(x) (((x) & 0xff) << 24)
93 #define FMC2_PATT_DEFAULT 0x0a0a0a0a
94
95 /* Register: FMC2_BCHISR */
96 #define FMC2_BCHISR_DERF BIT(1)
97 #define FMC2_BCHISR_EPBRF BIT(4)
98
99 /* Register: FMC2_BCHICR */
100 #define FMC2_BCHICR_CLEAR_IRQ GENMASK(4, 0)
101
102 /* Register: FMC2_BCHDSR0 */
103 #define FMC2_BCHDSR0_DUE BIT(0)
104 #define FMC2_BCHDSR0_DEF BIT(1)
105 #define FMC2_BCHDSR0_DEN_MASK GENMASK(7, 4)
106 #define FMC2_BCHDSR0_DEN_SHIFT 4
107
108 /* Register: FMC2_BCHDSR1 */
109 #define FMC2_BCHDSR1_EBP1_MASK GENMASK(12, 0)
110 #define FMC2_BCHDSR1_EBP2_MASK GENMASK(28, 16)
111 #define FMC2_BCHDSR1_EBP2_SHIFT 16
112
113 /* Register: FMC2_BCHDSR2 */
114 #define FMC2_BCHDSR2_EBP3_MASK GENMASK(12, 0)
115 #define FMC2_BCHDSR2_EBP4_MASK GENMASK(28, 16)
116 #define FMC2_BCHDSR2_EBP4_SHIFT 16
117
118 /* Register: FMC2_BCHDSR3 */
119 #define FMC2_BCHDSR3_EBP5_MASK GENMASK(12, 0)
120 #define FMC2_BCHDSR3_EBP6_MASK GENMASK(28, 16)
121 #define FMC2_BCHDSR3_EBP6_SHIFT 16
122
123 /* Register: FMC2_BCHDSR4 */
124 #define FMC2_BCHDSR4_EBP7_MASK GENMASK(12, 0)
125 #define FMC2_BCHDSR4_EBP8_MASK GENMASK(28, 16)
126 #define FMC2_BCHDSR4_EBP8_SHIFT 16
127
128 #define FMC2_NSEC_PER_SEC 1000000000L
129
130 enum stm32_fmc2_ecc {
131 FMC2_ECC_HAM = 1,
132 FMC2_ECC_BCH4 = 4,
133 FMC2_ECC_BCH8 = 8
134 };
135
136 struct stm32_fmc2_timings {
137 u8 tclr;
138 u8 tar;
139 u8 thiz;
140 u8 twait;
141 u8 thold_mem;
142 u8 tset_mem;
143 u8 thold_att;
144 u8 tset_att;
145 };
146
147 struct stm32_fmc2_nand {
148 struct nand_chip chip;
149 struct stm32_fmc2_timings timings;
150 int ncs;
151 int cs_used[FMC2_MAX_CE];
152 };
153
to_fmc2_nand(struct nand_chip * chip)154 static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip)
155 {
156 return container_of(chip, struct stm32_fmc2_nand, chip);
157 }
158
159 struct stm32_fmc2_nfc {
160 struct nand_hw_control base;
161 struct stm32_fmc2_nand nand;
162 struct nand_ecclayout ecclayout;
163 void __iomem *io_base;
164 void __iomem *data_base[FMC2_MAX_CE];
165 void __iomem *cmd_base[FMC2_MAX_CE];
166 void __iomem *addr_base[FMC2_MAX_CE];
167 struct clk clk;
168
169 u8 cs_assigned;
170 int cs_sel;
171 };
172
to_stm32_nfc(struct nand_hw_control * base)173 static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_hw_control *base)
174 {
175 return container_of(base, struct stm32_fmc2_nfc, base);
176 }
177
178 /* Timings configuration */
stm32_fmc2_timings_init(struct nand_chip * chip)179 static void stm32_fmc2_timings_init(struct nand_chip *chip)
180 {
181 struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
182 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
183 struct stm32_fmc2_timings *timings = &nand->timings;
184 u32 pcr = readl(fmc2->io_base + FMC2_PCR);
185 u32 pmem, patt;
186
187 /* Set tclr/tar timings */
188 pcr &= ~FMC2_PCR_TCLR_MASK;
189 pcr |= FMC2_PCR_TCLR(timings->tclr);
190 pcr &= ~FMC2_PCR_TAR_MASK;
191 pcr |= FMC2_PCR_TAR(timings->tar);
192
193 /* Set tset/twait/thold/thiz timings in common bank */
194 pmem = FMC2_PMEM_MEMSET(timings->tset_mem);
195 pmem |= FMC2_PMEM_MEMWAIT(timings->twait);
196 pmem |= FMC2_PMEM_MEMHOLD(timings->thold_mem);
197 pmem |= FMC2_PMEM_MEMHIZ(timings->thiz);
198
199 /* Set tset/twait/thold/thiz timings in attribut bank */
200 patt = FMC2_PATT_ATTSET(timings->tset_att);
201 patt |= FMC2_PATT_ATTWAIT(timings->twait);
202 patt |= FMC2_PATT_ATTHOLD(timings->thold_att);
203 patt |= FMC2_PATT_ATTHIZ(timings->thiz);
204
205 writel(pcr, fmc2->io_base + FMC2_PCR);
206 writel(pmem, fmc2->io_base + FMC2_PMEM);
207 writel(patt, fmc2->io_base + FMC2_PATT);
208 }
209
210 /* Controller configuration */
stm32_fmc2_setup(struct nand_chip * chip)211 static void stm32_fmc2_setup(struct nand_chip *chip)
212 {
213 struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
214 u32 pcr = readl(fmc2->io_base + FMC2_PCR);
215
216 /* Configure ECC algorithm (default configuration is Hamming) */
217 pcr &= ~FMC2_PCR_ECCALG;
218 pcr &= ~FMC2_PCR_BCHECC;
219 if (chip->ecc.strength == FMC2_ECC_BCH8) {
220 pcr |= FMC2_PCR_ECCALG;
221 pcr |= FMC2_PCR_BCHECC;
222 } else if (chip->ecc.strength == FMC2_ECC_BCH4) {
223 pcr |= FMC2_PCR_ECCALG;
224 }
225
226 /* Set buswidth */
227 pcr &= ~FMC2_PCR_PWID_MASK;
228 if (chip->options & NAND_BUSWIDTH_16)
229 pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_BUSWIDTH_16);
230
231 /* Set ECC sector size */
232 pcr &= ~FMC2_PCR_ECCSS_MASK;
233 pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_512);
234
235 writel(pcr, fmc2->io_base + FMC2_PCR);
236 }
237
238 /* Select target */
stm32_fmc2_select_chip(struct mtd_info * mtd,int chipnr)239 static void stm32_fmc2_select_chip(struct mtd_info *mtd, int chipnr)
240 {
241 struct nand_chip *chip = mtd_to_nand(mtd);
242 struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
243 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
244
245 if (chipnr < 0 || chipnr >= nand->ncs)
246 return;
247
248 if (nand->cs_used[chipnr] == fmc2->cs_sel)
249 return;
250
251 fmc2->cs_sel = nand->cs_used[chipnr];
252 chip->IO_ADDR_R = fmc2->data_base[fmc2->cs_sel];
253 chip->IO_ADDR_W = fmc2->data_base[fmc2->cs_sel];
254
255 /* FMC2 setup routine */
256 stm32_fmc2_setup(chip);
257
258 /* Apply timings */
259 stm32_fmc2_timings_init(chip);
260 }
261
262 /* Set bus width to 16-bit or 8-bit */
stm32_fmc2_set_buswidth_16(struct stm32_fmc2_nfc * fmc2,bool set)263 static void stm32_fmc2_set_buswidth_16(struct stm32_fmc2_nfc *fmc2, bool set)
264 {
265 u32 pcr = readl(fmc2->io_base + FMC2_PCR);
266
267 pcr &= ~FMC2_PCR_PWID_MASK;
268 if (set)
269 pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_BUSWIDTH_16);
270 writel(pcr, fmc2->io_base + FMC2_PCR);
271 }
272
273 /* Enable/disable ECC */
stm32_fmc2_set_ecc(struct stm32_fmc2_nfc * fmc2,bool enable)274 static void stm32_fmc2_set_ecc(struct stm32_fmc2_nfc *fmc2, bool enable)
275 {
276 u32 pcr = readl(fmc2->io_base + FMC2_PCR);
277
278 pcr &= ~FMC2_PCR_ECCEN;
279 if (enable)
280 pcr |= FMC2_PCR_ECCEN;
281 writel(pcr, fmc2->io_base + FMC2_PCR);
282 }
283
284 /* Clear irq sources in case of bch is used */
stm32_fmc2_clear_bch_irq(struct stm32_fmc2_nfc * fmc2)285 static inline void stm32_fmc2_clear_bch_irq(struct stm32_fmc2_nfc *fmc2)
286 {
287 writel(FMC2_BCHICR_CLEAR_IRQ, fmc2->io_base + FMC2_BCHICR);
288 }
289
290 /* Send command and address cycles */
stm32_fmc2_cmd_ctrl(struct mtd_info * mtd,int cmd,unsigned int ctrl)291 static void stm32_fmc2_cmd_ctrl(struct mtd_info *mtd, int cmd,
292 unsigned int ctrl)
293 {
294 struct nand_chip *chip = mtd_to_nand(mtd);
295 struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
296
297 if (cmd == NAND_CMD_NONE)
298 return;
299
300 if (ctrl & NAND_CLE) {
301 writeb(cmd, fmc2->cmd_base[fmc2->cs_sel]);
302 return;
303 }
304
305 writeb(cmd, fmc2->addr_base[fmc2->cs_sel]);
306 }
307
308 /*
309 * Enable ECC logic and reset syndrome/parity bits previously calculated
310 * Syndrome/parity bits is cleared by setting the ECCEN bit to 0
311 */
stm32_fmc2_hwctl(struct mtd_info * mtd,int mode)312 static void stm32_fmc2_hwctl(struct mtd_info *mtd, int mode)
313 {
314 struct nand_chip *chip = mtd_to_nand(mtd);
315 struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
316
317 stm32_fmc2_set_ecc(fmc2, false);
318
319 if (chip->ecc.strength != FMC2_ECC_HAM) {
320 u32 pcr = readl(fmc2->io_base + FMC2_PCR);
321
322 if (mode == NAND_ECC_WRITE)
323 pcr |= FMC2_PCR_WEN;
324 else
325 pcr &= ~FMC2_PCR_WEN;
326 writel(pcr, fmc2->io_base + FMC2_PCR);
327
328 stm32_fmc2_clear_bch_irq(fmc2);
329 }
330
331 stm32_fmc2_set_ecc(fmc2, true);
332 }
333
334 /*
335 * ECC Hamming calculation
336 * ECC is 3 bytes for 512 bytes of data (supports error correction up to
337 * max of 1-bit)
338 */
stm32_fmc2_ham_calculate(struct mtd_info * mtd,const u8 * data,u8 * ecc)339 static int stm32_fmc2_ham_calculate(struct mtd_info *mtd, const u8 *data,
340 u8 *ecc)
341 {
342 struct nand_chip *chip = mtd_to_nand(mtd);
343 struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
344 u32 heccr, sr;
345 int ret;
346
347 ret = readl_poll_timeout(fmc2->io_base + FMC2_SR, sr,
348 sr & FMC2_SR_NWRF, 10000);
349 if (ret < 0) {
350 pr_err("Ham timeout\n");
351 return ret;
352 }
353
354 heccr = readl(fmc2->io_base + FMC2_HECCR);
355
356 ecc[0] = heccr;
357 ecc[1] = heccr >> 8;
358 ecc[2] = heccr >> 16;
359
360 /* Disable ecc */
361 stm32_fmc2_set_ecc(fmc2, false);
362
363 return 0;
364 }
365
stm32_fmc2_ham_correct(struct mtd_info * mtd,u8 * dat,u8 * read_ecc,u8 * calc_ecc)366 static int stm32_fmc2_ham_correct(struct mtd_info *mtd, u8 *dat,
367 u8 *read_ecc, u8 *calc_ecc)
368 {
369 u8 bit_position = 0, b0, b1, b2;
370 u32 byte_addr = 0, b;
371 u32 i, shifting = 1;
372
373 /* Indicate which bit and byte is faulty (if any) */
374 b0 = read_ecc[0] ^ calc_ecc[0];
375 b1 = read_ecc[1] ^ calc_ecc[1];
376 b2 = read_ecc[2] ^ calc_ecc[2];
377 b = b0 | (b1 << 8) | (b2 << 16);
378
379 /* No errors */
380 if (likely(!b))
381 return 0;
382
383 /* Calculate bit position */
384 for (i = 0; i < 3; i++) {
385 switch (b % 4) {
386 case 2:
387 bit_position += shifting;
388 case 1:
389 break;
390 default:
391 return -EBADMSG;
392 }
393 shifting <<= 1;
394 b >>= 2;
395 }
396
397 /* Calculate byte position */
398 shifting = 1;
399 for (i = 0; i < 9; i++) {
400 switch (b % 4) {
401 case 2:
402 byte_addr += shifting;
403 case 1:
404 break;
405 default:
406 return -EBADMSG;
407 }
408 shifting <<= 1;
409 b >>= 2;
410 }
411
412 /* Flip the bit */
413 dat[byte_addr] ^= (1 << bit_position);
414
415 return 1;
416 }
417
418 /*
419 * ECC BCH calculation and correction
420 * ECC is 7/13 bytes for 512 bytes of data (supports error correction up to
421 * max of 4-bit/8-bit)
422 */
423
stm32_fmc2_bch_calculate(struct mtd_info * mtd,const u8 * data,u8 * ecc)424 static int stm32_fmc2_bch_calculate(struct mtd_info *mtd, const u8 *data,
425 u8 *ecc)
426 {
427 struct nand_chip *chip = mtd_to_nand(mtd);
428 struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
429 u32 bchpbr, bchisr;
430 int ret;
431
432 /* Wait until the BCH code is ready */
433 ret = readl_poll_timeout(fmc2->io_base + FMC2_BCHISR, bchisr,
434 bchisr & FMC2_BCHISR_EPBRF, 10000);
435 if (ret < 0) {
436 pr_err("Bch timeout\n");
437 return ret;
438 }
439
440 /* Read parity bits */
441 bchpbr = readl(fmc2->io_base + FMC2_BCHPBR1);
442 ecc[0] = bchpbr;
443 ecc[1] = bchpbr >> 8;
444 ecc[2] = bchpbr >> 16;
445 ecc[3] = bchpbr >> 24;
446
447 bchpbr = readl(fmc2->io_base + FMC2_BCHPBR2);
448 ecc[4] = bchpbr;
449 ecc[5] = bchpbr >> 8;
450 ecc[6] = bchpbr >> 16;
451
452 if (chip->ecc.strength == FMC2_ECC_BCH8) {
453 ecc[7] = bchpbr >> 24;
454
455 bchpbr = readl(fmc2->io_base + FMC2_BCHPBR3);
456 ecc[8] = bchpbr;
457 ecc[9] = bchpbr >> 8;
458 ecc[10] = bchpbr >> 16;
459 ecc[11] = bchpbr >> 24;
460
461 bchpbr = readl(fmc2->io_base + FMC2_BCHPBR4);
462 ecc[12] = bchpbr;
463 }
464
465 /* Disable ecc */
466 stm32_fmc2_set_ecc(fmc2, false);
467
468 return 0;
469 }
470
471 /* BCH algorithm correction */
stm32_fmc2_bch_correct(struct mtd_info * mtd,u8 * dat,u8 * read_ecc,u8 * calc_ecc)472 static int stm32_fmc2_bch_correct(struct mtd_info *mtd, u8 *dat,
473 u8 *read_ecc, u8 *calc_ecc)
474 {
475 struct nand_chip *chip = mtd_to_nand(mtd);
476 struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
477 u32 bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4, bchisr;
478 u16 pos[8];
479 int i, ret, den, eccsize = chip->ecc.size;
480 unsigned int nb_errs = 0;
481
482 /* Wait until the decoding error is ready */
483 ret = readl_poll_timeout(fmc2->io_base + FMC2_BCHISR, bchisr,
484 bchisr & FMC2_BCHISR_DERF, 10000);
485 if (ret < 0) {
486 pr_err("Bch timeout\n");
487 return ret;
488 }
489
490 bchdsr0 = readl(fmc2->io_base + FMC2_BCHDSR0);
491 bchdsr1 = readl(fmc2->io_base + FMC2_BCHDSR1);
492 bchdsr2 = readl(fmc2->io_base + FMC2_BCHDSR2);
493 bchdsr3 = readl(fmc2->io_base + FMC2_BCHDSR3);
494 bchdsr4 = readl(fmc2->io_base + FMC2_BCHDSR4);
495
496 /* Disable ECC */
497 stm32_fmc2_set_ecc(fmc2, false);
498
499 /* No errors found */
500 if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF)))
501 return 0;
502
503 /* Too many errors detected */
504 if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE))
505 return -EBADMSG;
506
507 pos[0] = bchdsr1 & FMC2_BCHDSR1_EBP1_MASK;
508 pos[1] = (bchdsr1 & FMC2_BCHDSR1_EBP2_MASK) >> FMC2_BCHDSR1_EBP2_SHIFT;
509 pos[2] = bchdsr2 & FMC2_BCHDSR2_EBP3_MASK;
510 pos[3] = (bchdsr2 & FMC2_BCHDSR2_EBP4_MASK) >> FMC2_BCHDSR2_EBP4_SHIFT;
511 pos[4] = bchdsr3 & FMC2_BCHDSR3_EBP5_MASK;
512 pos[5] = (bchdsr3 & FMC2_BCHDSR3_EBP6_MASK) >> FMC2_BCHDSR3_EBP6_SHIFT;
513 pos[6] = bchdsr4 & FMC2_BCHDSR4_EBP7_MASK;
514 pos[7] = (bchdsr4 & FMC2_BCHDSR4_EBP8_MASK) >> FMC2_BCHDSR4_EBP8_SHIFT;
515
516 den = (bchdsr0 & FMC2_BCHDSR0_DEN_MASK) >> FMC2_BCHDSR0_DEN_SHIFT;
517 for (i = 0; i < den; i++) {
518 if (pos[i] < eccsize * 8) {
519 __change_bit(pos[i], (unsigned long *)dat);
520 nb_errs++;
521 }
522 }
523
524 return nb_errs;
525 }
526
stm32_fmc2_read_page(struct mtd_info * mtd,struct nand_chip * chip,u8 * buf,int oob_required,int page)527 static int stm32_fmc2_read_page(struct mtd_info *mtd,
528 struct nand_chip *chip, u8 *buf,
529 int oob_required, int page)
530 {
531 int i, s, stat, eccsize = chip->ecc.size;
532 int eccbytes = chip->ecc.bytes;
533 int eccsteps = chip->ecc.steps;
534 int eccstrength = chip->ecc.strength;
535 u8 *p = buf;
536 u8 *ecc_calc = chip->buffers->ecccalc;
537 u8 *ecc_code = chip->buffers->ecccode;
538 unsigned int max_bitflips = 0;
539
540 for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps;
541 s++, i += eccbytes, p += eccsize) {
542 chip->ecc.hwctl(mtd, NAND_ECC_READ);
543
544 /* Read the nand page sector (512 bytes) */
545 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, s * eccsize, -1);
546 chip->read_buf(mtd, p, eccsize);
547
548 /* Read the corresponding ECC bytes */
549 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, i, -1);
550 chip->read_buf(mtd, ecc_code, eccbytes);
551
552 /* Correct the data */
553 stat = chip->ecc.correct(mtd, p, ecc_code, ecc_calc);
554 if (stat == -EBADMSG)
555 /* Check for empty pages with bitflips */
556 stat = nand_check_erased_ecc_chunk(p, eccsize,
557 ecc_code, eccbytes,
558 NULL, 0,
559 eccstrength);
560
561 if (stat < 0) {
562 mtd->ecc_stats.failed++;
563 } else {
564 mtd->ecc_stats.corrected += stat;
565 max_bitflips = max_t(unsigned int, max_bitflips, stat);
566 }
567 }
568
569 /* Read oob */
570 if (oob_required) {
571 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
572 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
573 }
574
575 return max_bitflips;
576 }
577
578 /* Controller initialization */
stm32_fmc2_init(struct stm32_fmc2_nfc * fmc2)579 static void stm32_fmc2_init(struct stm32_fmc2_nfc *fmc2)
580 {
581 u32 pcr = readl(fmc2->io_base + FMC2_PCR);
582 u32 bcr1 = readl(fmc2->io_base + FMC2_BCR1);
583
584 /* Set CS used to undefined */
585 fmc2->cs_sel = -1;
586
587 /* Enable wait feature and nand flash memory bank */
588 pcr |= FMC2_PCR_PWAITEN;
589 pcr |= FMC2_PCR_PBKEN;
590
591 /* Set buswidth to 8 bits mode for identification */
592 pcr &= ~FMC2_PCR_PWID_MASK;
593
594 /* ECC logic is disabled */
595 pcr &= ~FMC2_PCR_ECCEN;
596
597 /* Default mode */
598 pcr &= ~FMC2_PCR_ECCALG;
599 pcr &= ~FMC2_PCR_BCHECC;
600 pcr &= ~FMC2_PCR_WEN;
601
602 /* Set default ECC sector size */
603 pcr &= ~FMC2_PCR_ECCSS_MASK;
604 pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_2048);
605
606 /* Set default tclr/tar timings */
607 pcr &= ~FMC2_PCR_TCLR_MASK;
608 pcr |= FMC2_PCR_TCLR(FMC2_PCR_TCLR_DEFAULT);
609 pcr &= ~FMC2_PCR_TAR_MASK;
610 pcr |= FMC2_PCR_TAR(FMC2_PCR_TAR_DEFAULT);
611
612 /* Enable FMC2 controller */
613 bcr1 |= FMC2_BCR1_FMC2EN;
614
615 writel(bcr1, fmc2->io_base + FMC2_BCR1);
616 writel(pcr, fmc2->io_base + FMC2_PCR);
617 writel(FMC2_PMEM_DEFAULT, fmc2->io_base + FMC2_PMEM);
618 writel(FMC2_PATT_DEFAULT, fmc2->io_base + FMC2_PATT);
619 }
620
621 /* Controller timings */
stm32_fmc2_calc_timings(struct nand_chip * chip,const struct nand_sdr_timings * sdrt)622 static void stm32_fmc2_calc_timings(struct nand_chip *chip,
623 const struct nand_sdr_timings *sdrt)
624 {
625 struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
626 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
627 struct stm32_fmc2_timings *tims = &nand->timings;
628 unsigned long hclk = clk_get_rate(&fmc2->clk);
629 unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
630 unsigned long timing, tar, tclr, thiz, twait;
631 unsigned long tset_mem, tset_att, thold_mem, thold_att;
632
633 tar = max_t(unsigned long, hclkp, sdrt->tAR_min);
634 timing = DIV_ROUND_UP(tar, hclkp) - 1;
635 tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
636
637 tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min);
638 timing = DIV_ROUND_UP(tclr, hclkp) - 1;
639 tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
640
641 tims->thiz = FMC2_THIZ;
642 thiz = (tims->thiz + 1) * hclkp;
643
644 /*
645 * tWAIT > tRP
646 * tWAIT > tWP
647 * tWAIT > tREA + tIO
648 */
649 twait = max_t(unsigned long, hclkp, sdrt->tRP_min);
650 twait = max_t(unsigned long, twait, sdrt->tWP_min);
651 twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO);
652 timing = DIV_ROUND_UP(twait, hclkp);
653 tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
654
655 /*
656 * tSETUP_MEM > tCS - tWAIT
657 * tSETUP_MEM > tALS - tWAIT
658 * tSETUP_MEM > tDS - (tWAIT - tHIZ)
659 */
660 tset_mem = hclkp;
661 if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait))
662 tset_mem = sdrt->tCS_min - twait;
663 if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait))
664 tset_mem = sdrt->tALS_min - twait;
665 if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
666 (tset_mem < sdrt->tDS_min - (twait - thiz)))
667 tset_mem = sdrt->tDS_min - (twait - thiz);
668 timing = DIV_ROUND_UP(tset_mem, hclkp);
669 tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
670
671 /*
672 * tHOLD_MEM > tCH
673 * tHOLD_MEM > tREH - tSETUP_MEM
674 * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
675 */
676 thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min);
677 if (sdrt->tREH_min > tset_mem &&
678 (thold_mem < sdrt->tREH_min - tset_mem))
679 thold_mem = sdrt->tREH_min - tset_mem;
680 if ((sdrt->tRC_min > tset_mem + twait) &&
681 (thold_mem < sdrt->tRC_min - (tset_mem + twait)))
682 thold_mem = sdrt->tRC_min - (tset_mem + twait);
683 if ((sdrt->tWC_min > tset_mem + twait) &&
684 (thold_mem < sdrt->tWC_min - (tset_mem + twait)))
685 thold_mem = sdrt->tWC_min - (tset_mem + twait);
686 timing = DIV_ROUND_UP(thold_mem, hclkp);
687 tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
688
689 /*
690 * tSETUP_ATT > tCS - tWAIT
691 * tSETUP_ATT > tCLS - tWAIT
692 * tSETUP_ATT > tALS - tWAIT
693 * tSETUP_ATT > tRHW - tHOLD_MEM
694 * tSETUP_ATT > tDS - (tWAIT - tHIZ)
695 */
696 tset_att = hclkp;
697 if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait))
698 tset_att = sdrt->tCS_min - twait;
699 if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait))
700 tset_att = sdrt->tCLS_min - twait;
701 if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait))
702 tset_att = sdrt->tALS_min - twait;
703 if (sdrt->tRHW_min > thold_mem &&
704 (tset_att < sdrt->tRHW_min - thold_mem))
705 tset_att = sdrt->tRHW_min - thold_mem;
706 if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
707 (tset_att < sdrt->tDS_min - (twait - thiz)))
708 tset_att = sdrt->tDS_min - (twait - thiz);
709 timing = DIV_ROUND_UP(tset_att, hclkp);
710 tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
711
712 /*
713 * tHOLD_ATT > tALH
714 * tHOLD_ATT > tCH
715 * tHOLD_ATT > tCLH
716 * tHOLD_ATT > tCOH
717 * tHOLD_ATT > tDH
718 * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM
719 * tHOLD_ATT > tADL - tSETUP_MEM
720 * tHOLD_ATT > tWH - tSETUP_MEM
721 * tHOLD_ATT > tWHR - tSETUP_MEM
722 * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
723 * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
724 */
725 thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min);
726 thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min);
727 thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min);
728 thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min);
729 thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min);
730 if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) &&
731 (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem))
732 thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem;
733 if (sdrt->tADL_min > tset_mem &&
734 (thold_att < sdrt->tADL_min - tset_mem))
735 thold_att = sdrt->tADL_min - tset_mem;
736 if (sdrt->tWH_min > tset_mem &&
737 (thold_att < sdrt->tWH_min - tset_mem))
738 thold_att = sdrt->tWH_min - tset_mem;
739 if (sdrt->tWHR_min > tset_mem &&
740 (thold_att < sdrt->tWHR_min - tset_mem))
741 thold_att = sdrt->tWHR_min - tset_mem;
742 if ((sdrt->tRC_min > tset_att + twait) &&
743 (thold_att < sdrt->tRC_min - (tset_att + twait)))
744 thold_att = sdrt->tRC_min - (tset_att + twait);
745 if ((sdrt->tWC_min > tset_att + twait) &&
746 (thold_att < sdrt->tWC_min - (tset_att + twait)))
747 thold_att = sdrt->tWC_min - (tset_att + twait);
748 timing = DIV_ROUND_UP(thold_att, hclkp);
749 tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
750 }
751
stm32_fmc2_setup_interface(struct mtd_info * mtd,int chipnr,const struct nand_data_interface * conf)752 static int stm32_fmc2_setup_interface(struct mtd_info *mtd, int chipnr,
753 const struct nand_data_interface *conf)
754 {
755 struct nand_chip *chip = mtd_to_nand(mtd);
756 const struct nand_sdr_timings *sdrt;
757
758 sdrt = nand_get_sdr_timings(conf);
759 if (IS_ERR(sdrt))
760 return PTR_ERR(sdrt);
761
762 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
763 return 0;
764
765 stm32_fmc2_calc_timings(chip, sdrt);
766
767 /* Apply timings */
768 stm32_fmc2_timings_init(chip);
769
770 return 0;
771 }
772
773 /* NAND callbacks setup */
stm32_fmc2_nand_callbacks_setup(struct nand_chip * chip)774 static void stm32_fmc2_nand_callbacks_setup(struct nand_chip *chip)
775 {
776 chip->ecc.hwctl = stm32_fmc2_hwctl;
777
778 /*
779 * Specific callbacks to read/write a page depending on
780 * the algo used (Hamming, BCH).
781 */
782 if (chip->ecc.strength == FMC2_ECC_HAM) {
783 /* Hamming is used */
784 chip->ecc.calculate = stm32_fmc2_ham_calculate;
785 chip->ecc.correct = stm32_fmc2_ham_correct;
786 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3;
787 chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK;
788 return;
789 }
790
791 /* BCH is used */
792 chip->ecc.read_page = stm32_fmc2_read_page;
793 chip->ecc.calculate = stm32_fmc2_bch_calculate;
794 chip->ecc.correct = stm32_fmc2_bch_correct;
795
796 if (chip->ecc.strength == FMC2_ECC_BCH8)
797 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13;
798 else
799 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
800 }
801
802 /* FMC2 caps */
stm32_fmc2_calc_ecc_bytes(int step_size,int strength)803 static int stm32_fmc2_calc_ecc_bytes(int step_size, int strength)
804 {
805 /* Hamming */
806 if (strength == FMC2_ECC_HAM)
807 return 4;
808
809 /* BCH8 */
810 if (strength == FMC2_ECC_BCH8)
811 return 14;
812
813 /* BCH4 */
814 return 8;
815 }
816
817 NAND_ECC_CAPS_SINGLE(stm32_fmc2_ecc_caps, stm32_fmc2_calc_ecc_bytes,
818 FMC2_ECC_STEP_SIZE,
819 FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);
820
821 /* FMC2 probe */
stm32_fmc2_parse_child(struct stm32_fmc2_nfc * fmc2,ofnode node)822 static int stm32_fmc2_parse_child(struct stm32_fmc2_nfc *fmc2,
823 ofnode node)
824 {
825 struct stm32_fmc2_nand *nand = &fmc2->nand;
826 u32 cs[FMC2_MAX_CE];
827 int ret, i;
828
829 if (!ofnode_get_property(node, "reg", &nand->ncs))
830 return -EINVAL;
831
832 nand->ncs /= sizeof(u32);
833 if (!nand->ncs) {
834 pr_err("Invalid reg property size\n");
835 return -EINVAL;
836 }
837
838 ret = ofnode_read_u32_array(node, "reg", cs, nand->ncs);
839 if (ret < 0) {
840 pr_err("Could not retrieve reg property\n");
841 return -EINVAL;
842 }
843
844 for (i = 0; i < nand->ncs; i++) {
845 if (cs[i] > FMC2_MAX_CE) {
846 pr_err("Invalid reg value: %d\n",
847 nand->cs_used[i]);
848 return -EINVAL;
849 }
850
851 if (fmc2->cs_assigned & BIT(cs[i])) {
852 pr_err("Cs already assigned: %d\n",
853 nand->cs_used[i]);
854 return -EINVAL;
855 }
856
857 fmc2->cs_assigned |= BIT(cs[i]);
858 nand->cs_used[i] = cs[i];
859 }
860
861 nand->chip.flash_node = ofnode_to_offset(node);
862
863 return 0;
864 }
865
stm32_fmc2_parse_dt(struct udevice * dev,struct stm32_fmc2_nfc * fmc2)866 static int stm32_fmc2_parse_dt(struct udevice *dev,
867 struct stm32_fmc2_nfc *fmc2)
868 {
869 ofnode child;
870 int ret, nchips = 0;
871
872 dev_for_each_subnode(child, dev)
873 nchips++;
874
875 if (!nchips) {
876 pr_err("NAND chip not defined\n");
877 return -EINVAL;
878 }
879
880 if (nchips > 1) {
881 pr_err("Too many NAND chips defined\n");
882 return -EINVAL;
883 }
884
885 dev_for_each_subnode(child, dev) {
886 ret = stm32_fmc2_parse_child(fmc2, child);
887 if (ret)
888 return ret;
889 }
890
891 return 0;
892 }
893
stm32_fmc2_probe(struct udevice * dev)894 static int stm32_fmc2_probe(struct udevice *dev)
895 {
896 struct stm32_fmc2_nfc *fmc2 = dev_get_priv(dev);
897 struct stm32_fmc2_nand *nand = &fmc2->nand;
898 struct nand_chip *chip = &nand->chip;
899 struct mtd_info *mtd = &chip->mtd;
900 struct nand_ecclayout *ecclayout;
901 struct resource resource;
902 struct reset_ctl reset;
903 int oob_index, chip_cs, mem_region, ret;
904 unsigned int i;
905
906 spin_lock_init(&fmc2->controller.lock);
907 init_waitqueue_head(&fmc2->controller.wq);
908
909 ret = stm32_fmc2_parse_dt(dev, fmc2);
910 if (ret)
911 return ret;
912
913 /* Get resources */
914 ret = dev_read_resource(dev, 0, &resource);
915 if (ret) {
916 pr_err("Resource io_base not found");
917 return ret;
918 }
919 fmc2->io_base = (void __iomem *)resource.start;
920
921 for (chip_cs = 0, mem_region = 1; chip_cs < FMC2_MAX_CE;
922 chip_cs++, mem_region += 3) {
923 if (!(fmc2->cs_assigned & BIT(chip_cs)))
924 continue;
925
926 ret = dev_read_resource(dev, mem_region, &resource);
927 if (ret) {
928 pr_err("Resource data_base not found for cs%d",
929 chip_cs);
930 return ret;
931 }
932 fmc2->data_base[chip_cs] = (void __iomem *)resource.start;
933
934 ret = dev_read_resource(dev, mem_region + 1, &resource);
935 if (ret) {
936 pr_err("Resource cmd_base not found for cs%d",
937 chip_cs);
938 return ret;
939 }
940 fmc2->cmd_base[chip_cs] = (void __iomem *)resource.start;
941
942 ret = dev_read_resource(dev, mem_region + 2, &resource);
943 if (ret) {
944 pr_err("Resource addr_base not found for cs%d",
945 chip_cs);
946 return ret;
947 }
948 fmc2->addr_base[chip_cs] = (void __iomem *)resource.start;
949 }
950
951 /* Enable the clock */
952 ret = clk_get_by_index(dev, 0, &fmc2->clk);
953 if (ret)
954 return ret;
955
956 ret = clk_enable(&fmc2->clk);
957 if (ret)
958 return ret;
959
960 /* Reset */
961 ret = reset_get_by_index(dev, 0, &reset);
962 if (!ret) {
963 reset_assert(&reset);
964 udelay(2);
965 reset_deassert(&reset);
966 }
967
968 /* FMC2 init routine */
969 stm32_fmc2_init(fmc2);
970
971 chip->controller = &fmc2->base;
972 chip->select_chip = stm32_fmc2_select_chip;
973 chip->setup_data_interface = stm32_fmc2_setup_interface;
974 chip->cmd_ctrl = stm32_fmc2_cmd_ctrl;
975 chip->chip_delay = FMC2_RB_DELAY_US;
976 chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
977 NAND_USE_BOUNCE_BUFFER;
978
979 /* Default ECC settings */
980 chip->ecc.mode = NAND_ECC_HW;
981 chip->ecc.size = FMC2_ECC_STEP_SIZE;
982 chip->ecc.strength = FMC2_ECC_BCH8;
983
984 /* Scan to find existence of the device */
985 ret = nand_scan_ident(mtd, nand->ncs, NULL);
986 if (ret)
987 return ret;
988
989 /*
990 * Only NAND_ECC_HW mode is actually supported
991 * Hamming => ecc.strength = 1
992 * BCH4 => ecc.strength = 4
993 * BCH8 => ecc.strength = 8
994 * ECC sector size = 512
995 */
996 if (chip->ecc.mode != NAND_ECC_HW) {
997 pr_err("Nand_ecc_mode is not well defined in the DT\n");
998 return -EINVAL;
999 }
1000
1001 ret = nand_check_ecc_caps(chip, &stm32_fmc2_ecc_caps,
1002 mtd->oobsize - FMC2_BBM_LEN);
1003 if (ret) {
1004 pr_err("No valid ECC settings set\n");
1005 return ret;
1006 }
1007
1008 if (chip->bbt_options & NAND_BBT_USE_FLASH)
1009 chip->bbt_options |= NAND_BBT_NO_OOB;
1010
1011 /* NAND callbacks setup */
1012 stm32_fmc2_nand_callbacks_setup(chip);
1013
1014 /* Define ECC layout */
1015 ecclayout = &fmc2->ecclayout;
1016 ecclayout->eccbytes = chip->ecc.bytes *
1017 (mtd->writesize / chip->ecc.size);
1018 oob_index = FMC2_BBM_LEN;
1019 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1020 ecclayout->eccpos[i] = oob_index;
1021 ecclayout->oobfree->offset = oob_index;
1022 ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
1023 chip->ecc.layout = ecclayout;
1024
1025 /* Configure bus width to 16-bit */
1026 if (chip->options & NAND_BUSWIDTH_16)
1027 stm32_fmc2_set_buswidth_16(fmc2, true);
1028
1029 /* Scan the device to fill MTD data-structures */
1030 ret = nand_scan_tail(mtd);
1031 if (ret)
1032 return ret;
1033
1034 return nand_register(0, mtd);
1035 }
1036
1037 static const struct udevice_id stm32_fmc2_match[] = {
1038 { .compatible = "st,stm32mp15-fmc2" },
1039 { /* Sentinel */ }
1040 };
1041
1042 U_BOOT_DRIVER(stm32_fmc2_nand) = {
1043 .name = "stm32_fmc2_nand",
1044 .id = UCLASS_MTD,
1045 .of_match = stm32_fmc2_match,
1046 .probe = stm32_fmc2_probe,
1047 .priv_auto_alloc_size = sizeof(struct stm32_fmc2_nfc),
1048 };
1049
board_nand_init(void)1050 void board_nand_init(void)
1051 {
1052 struct udevice *dev;
1053 int ret;
1054
1055 ret = uclass_get_device_by_driver(UCLASS_MTD,
1056 DM_GET_DRIVER(stm32_fmc2_nand),
1057 &dev);
1058 if (ret && ret != -ENODEV)
1059 pr_err("Failed to initialize STM32 FMC2 NAND controller. (error %d)\n",
1060 ret);
1061 }
1062