| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCCodeEmitter.cpp | 192 assert(MO.isImm() && "did not expect relocated expression"); in getMachineOpValue()
203 if (MO.isImm()) in getLdStUImm12OpValue()
224 if (MO.isImm()) in getAdrLabelOpValue()
255 if (MO.isImm()) in getAddSubImmOpValue()
277 if (MO.isImm()) in getCondBranchTargetOpValue()
299 if (MO.isImm()) in getLoadLiteralOpValue()
327 if (MO.isImm()) in getMoveWideImmOpValue()
347 if (MO.isImm()) in getTestBranchTargetOpValue()
369 if (MO.isImm()) in getBranchTargetOpValue()
395 assert(MO.isImm() && "Expected an immediate value for the shift amount!"); in getVecShifterOpValue()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCCodeEmitter.cpp | 207 assert(MO.isImm() && "did not expect relocated expression"); in getMachineOpValue()
218 if (MO.isImm()) in getLdStUImm12OpValue()
239 if (MO.isImm()) in getAdrLabelOpValue()
270 if (MO.isImm()) in getAddSubImmOpValue()
301 if (MO.isImm()) in getCondBranchTargetOpValue()
323 if (MO.isImm()) in getLoadLiteralOpValue()
351 if (MO.isImm()) in getMoveWideImmOpValue()
371 if (MO.isImm()) in getTestBranchTargetOpValue()
393 if (MO.isImm()) in getBranchTargetOpValue()
419 assert(MO.isImm() && "Expected an immediate value for the shift amount!"); in getVecShifterOpValue()
[all …]
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 55 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
101 assert(InstIn.getOperand(2).isImm()); in LowerDins()
103 assert(InstIn.getOperand(3).isImm()); in LowerDins()
276 if (MO.isImm()) return MO.getImm() >> 2; in getBranchTargetOpValue()
299 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTargetOpValue1SImm16()
322 if (MO.isImm()) in getBranchTargetOpValueMMR6()
346 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTarget7OpValueMM()
368 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTargetOpValueMMPC10()
390 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTargetOpValueMM()
413 if (MO.isImm()) return MO.getImm() >> 2; in getBranchTarget21OpValue()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenAsmWriter.inc | 6798 MI->getOperand(1).isImm() &&
6807 MI->getOperand(0).isImm() &&
6816 MI->getOperand(0).isImm() &&
6824 MI->getOperand(0).isImm() &&
6833 MI->getOperand(0).isImm() &&
6841 MI->getOperand(0).isImm() &&
6850 MI->getOperand(0).isImm() &&
6858 MI->getOperand(0).isImm() &&
6867 MI->getOperand(0).isImm() &&
6875 MI->getOperand(0).isImm() &&
[all …]
|
| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 117 if (MCOp.isImm()) in getMachineOpValue()
148 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
156 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
197 assert((Op2.isImm() || Op2.isExpr()) && in getRiMemoryOpValue()
203 if (Op2.isImm()) { in getRiMemoryOpValue()
233 assert(AluMCOp.isImm() && "Third operator is not immediate."); in getRrMemoryOpValue()
268 assert((Op2.isImm() || Op2.isExpr()) && in getSplsOpValue()
274 if (Op2.isImm()) { in getSplsOpValue()
295 if (MCOp.isReg() || MCOp.isImm()) in getCallTargetOpValue()
308 if (MCOp.isReg() || MCOp.isImm()) in getBranchTargetOpValue()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 63 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
238 if (MO.isImm()) return MO.getImm() >> 2; in getBranchTargetOpValue()
260 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTargetOpValue1SImm16()
282 if (MO.isImm()) in getBranchTargetOpValueMMR6()
305 if (MO.isImm()) in getBranchTargetOpValueLsl2MMR6()
328 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTarget7OpValueMM()
349 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTargetOpValueMMPC10()
370 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTargetOpValueMM()
392 if (MO.isImm()) return MO.getImm() >> 2; in getBranchTarget21OpValue()
414 if (MO.isImm()) return MO.getImm() >> 2; in getBranchTarget21OpValueMM()
[all …]
|
| /external/capstone/arch/Sparc/ |
| D | SparcDisassembler.c | 258 bool isImm = fieldFromInstruction_4(insn, 13, 1) != 0; in DecodeMem() local
262 if (isImm) in DecodeMem()
279 if (isImm) in DecodeMem()
379 unsigned isImm = fieldFromInstruction_4(insn, 13, 1); in DecodeJMPL() local
383 if (isImm) in DecodeJMPL()
399 if (isImm) in DecodeJMPL()
415 unsigned isImm = fieldFromInstruction_4(insn, 13, 1); in DecodeReturn() local
418 if (isImm) in DecodeReturn()
429 if (isImm) in DecodeReturn()
446 unsigned isImm = fieldFromInstruction_4(insn, 13, 1); in DecodeSWAP() local
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 115 if (MCOp.isImm()) in getMachineOpValue()
146 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
154 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
195 assert((Op2.isImm() || Op2.isExpr()) && in getRiMemoryOpValue()
201 if (Op2.isImm()) { in getRiMemoryOpValue()
231 assert(AluMCOp.isImm() && "Third operator is not immediate."); in getRrMemoryOpValue()
266 assert((Op2.isImm() || Op2.isExpr()) && in getSplsOpValue()
272 if (Op2.isImm()) { in getSplsOpValue()
293 if (MCOp.isReg() || MCOp.isImm()) in getBranchTargetOpValue()
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCTargetDesc.cpp | 37 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && in getMCRDeprecationInfo()
38 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && in getMCRDeprecationInfo()
41 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { in getMCRDeprecationInfo()
42 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { in getMCRDeprecationInfo()
43 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) { in getMCRDeprecationInfo()
50 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) { in getMCRDeprecationInfo()
57 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && in getMCRDeprecationInfo()
58 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) { in getMCRDeprecationInfo()
68 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() && in getITDeprecationInfo()
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 157 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
169 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
182 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
195 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
207 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
224 if (MO.isImm()) in getMemRIEncoding()
243 if (MO.isImm()) in getMemRIXEncoding()
261 assert(MO.isImm()); in getMemRIX16Encoding()
276 assert(MO.isImm()); in getSPE8DisEncoding()
292 assert(MO.isImm()); in getSPE4DisEncoding()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 164 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
176 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
189 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
202 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
214 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
231 if (MO.isImm()) in getMemRIEncoding()
249 if (MO.isImm()) in getMemRIXEncoding()
267 assert(MO.isImm() && !(MO.getImm() % 16) && in getMemRIX16Encoding()
283 assert(MO.isImm()); in getSPE8DisEncoding()
298 assert(MO.isImm()); in getSPE4DisEncoding()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCTargetDesc.cpp | 40 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && in getMCRDeprecationInfo()
41 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && in getMCRDeprecationInfo()
44 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { in getMCRDeprecationInfo()
45 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { in getMCRDeprecationInfo()
46 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) { in getMCRDeprecationInfo()
53 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) { in getMCRDeprecationInfo()
60 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && in getMCRDeprecationInfo()
61 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) { in getMCRDeprecationInfo()
71 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() && in getITDeprecationInfo()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/InstPrinter/ |
| D | BPFInstPrinter.cpp | 57 } else if (Op.isImm()) { in printOperand()
75 if (OffsetOp.isImm()) { in printMemOperand()
89 if (Op.isImm()) in printImm64Operand()
100 if (Op.isImm()) { in printBrTargetOperand()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/InstPrinter/ |
| D | LanaiInstPrinter.cpp | 152 else if (Op.isImm()) in printOperand()
163 if (Op.isImm()) { in printMemImmOperand()
177 if (Op.isImm()) { in printHi16ImmOperand()
189 if (Op.isImm()) { in printHi16AndImmOperand()
201 if (Op.isImm()) { in printLo16AndImmOperand()
226 assert((OffsetOp.isImm() || OffsetOp.isExpr()) && "Immediate expected"); in printMemoryImmediateOffset()
227 if (OffsetOp.isImm()) { in printMemoryImmediateOffset()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| D | LanaiMemAluCombiner.cpp | 186 (Op.isImm() && Op.getImm() == 0)); in isZeroOperand()
247 assert((AluOffset.isReg() || AluOffset.isImm()) && in insertMergedInstruction()
252 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); in insertMergedInstruction()
266 else if (AluOffset.isImm()) in insertMergedInstruction()
302 if (Op2.isImm()) { in isSuitableAluInstr()
311 if (Offset.isImm() && in isSuitableAluInstr()
376 assert(AluOperand.isImm() && "Unexpected memory operator type"); in combineMemAluInBasicBlock()
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiMemAluCombiner.cpp | 186 (Op.isImm() && Op.getImm() == 0)); in isZeroOperand()
247 assert((AluOffset.isReg() || AluOffset.isImm()) && in insertMergedInstruction()
252 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); in insertMergedInstruction()
266 else if (AluOffset.isImm()) in insertMergedInstruction()
302 if (Op2.isImm()) { in isSuitableAluInstr()
311 if (Offset.isImm() && in isSuitableAluInstr()
373 assert(AluOperand.isImm() && "Unexpected memory operator type"); in combineMemAluInBasicBlock()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/MCTargetDesc/ |
| D | AVRMCCodeEmitter.cpp | 104 assert(MO.isImm()); in encodeRelCondBrTarget()
157 if (OffsetOp.isImm()) { in encodeMemri()
174 assert(MI.getOperand(OpNo).isImm()); in encodeComplement()
201 assert(MO.isImm()); in encodeImm()
216 assert(MO.isImm()); in encodeCallTarget()
255 if (MO.isImm()) return static_cast<unsigned>(MO.getImm()); in getMachineOpValue()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 160 assert(isImm() && "Invalid type access!"); in getImm()
192 bool isImm() const override { return Kind == IMMEDIATE; } in isImm() function
209 if (!isImm()) in isBrImm()
223 bool isCallTarget() { return isImm() || isToken(); } in isCallTarget()
226 if (!isImm()) in isHiImm16()
249 if (!isImm()) in isHiImm16And()
262 if (!isImm()) in isLoImm16()
286 if (!isImm()) in isLoImm16Signed()
310 if (!isImm()) in isLoImm16And()
323 if (!isImm()) in isImmShift()
[all …]
|
| /external/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 145 assert(isImm() && "Invalid type access!"); in getImm()
177 bool isImm() const override { return Kind == IMMEDIATE; } in isImm() function
194 if (!isImm()) in isBrImm()
208 bool isCallTarget() { return isImm() || isToken(); } in isCallTarget()
211 if (!isImm()) in isHiImm16()
234 if (!isImm()) in isHiImm16And()
247 if (!isImm()) in isLoImm16()
271 if (!isImm()) in isLoImm16Signed()
295 if (!isImm()) in isLoImm16And()
308 if (!isImm()) in isImmShift()
[all …]
|
| /external/llvm/lib/Target/Lanai/InstPrinter/ |
| D | LanaiInstPrinter.cpp | 152 else if (Op.isImm()) in printOperand()
163 if (Op.isImm()) { in printMemImmOperand()
177 if (Op.isImm()) { in printHi16ImmOperand()
189 if (Op.isImm()) { in printHi16AndImmOperand()
201 if (Op.isImm()) { in printLo16AndImmOperand()
226 assert((OffsetOp.isImm() || OffsetOp.isExpr()) && "Immediate expected"); in printMemoryImmediateOffset()
227 if (OffsetOp.isImm()) { in printMemoryImmediateOffset()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 385 bool isImm = fieldFromInstruction(insn, 13, 1); in DecodeMem() local
390 if (isImm) in DecodeMem()
408 if (isImm) in DecodeMem()
542 unsigned isImm = fieldFromInstruction(insn, 13, 1); in DecodeJMPL() local
545 if (isImm) in DecodeJMPL()
561 if (isImm) in DecodeJMPL()
575 unsigned isImm = fieldFromInstruction(insn, 13, 1); in DecodeReturn() local
578 if (isImm) in DecodeReturn()
589 if (isImm) in DecodeReturn()
604 unsigned isImm = fieldFromInstruction(insn, 13, 1); in DecodeSWAP() local
[all …]
|
| /external/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 383 bool isImm = fieldFromInstruction(insn, 13, 1); in DecodeMem() local
388 if (isImm) in DecodeMem()
406 if (isImm) in DecodeMem()
540 unsigned isImm = fieldFromInstruction(insn, 13, 1); in DecodeJMPL() local
543 if (isImm) in DecodeJMPL()
559 if (isImm) in DecodeJMPL()
573 unsigned isImm = fieldFromInstruction(insn, 13, 1); in DecodeReturn() local
576 if (isImm) in DecodeReturn()
587 if (isImm) in DecodeReturn()
602 unsigned isImm = fieldFromInstruction(insn, 13, 1); in DecodeSWAP() local
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIFoldOperands.cpp | 46 if (FoldOp->isImm()) { in FoldCandidate()
60 bool isImm() const { in isImm() function
162 if (Fold.isImm()) { in updateOperand()
252 if (Opc == AMDGPU::S_SETREG_B32 && OpToFold->isImm()) { in tryAddToFoldList()
363 bool FoldingImm = OpToFold.isImm(); in foldOperand()
519 if (ImmSrc.isImm()) in getImmOrMaterializedImm()
550 if (!Src0->isImm() && !Src1->isImm()) in tryConstantFoldOp()
556 if (Src0->isImm() && Src1->isImm()) { in tryConstantFoldOp()
575 if (Src0->isImm() && !Src1->isImm()) { in tryConstantFoldOp()
665 bool FoldingImm = OpToFold.isImm() || OpToFold.isFI(); in foldInstOperand()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/InstPrinter/ |
| D | ARCInstPrinter.cpp | 143 if (Op.isImm()) { in printOperand()
157 assert(offset.isImm() && "Offset should be immediate."); in printMemOperandRI()
166 assert(Op.isImm() && "Predicate operand is immediate."); in printPredicateOperand()
173 assert(Op.isImm() && "Predicate operand is immediate."); in printBRCCPredicateOperand()
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86InstComments.cpp | 389 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
405 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
421 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
435 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
453 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
543 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
560 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
573 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
584 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
595 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
[all …]
|