/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
D | TargetCallingConv.h | 69 bool isInReg() const { return IsInReg; } in isInReg() function
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/external/llvm/include/llvm/Target/ |
D | TargetCallingConv.h | 76 bool isInReg() const { return Flags & InReg; } in isInReg() function
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D | TargetCallingConv.td | 66 class CCIfInReg<CCAction A> : CCIf<"ArgFlags.isInReg()", A> {}
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D | TargetLowering.h | 2466 bool isInReg : 1; member 2476 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), in ArgListEntry()
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
D | MipsGenCallingConv.inc | 118 if (ArgFlags.isInReg()) { 274 if (ArgFlags.isInReg()) { 640 if (ArgFlags.isInReg()) { 715 if (ArgFlags.isInReg()) { 732 if (ArgFlags.isInReg()) {
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
D | AMDGPUCallLowering.cpp | 193 !OrigArg.Flags.isInReg() && !OrigArg.Flags.isByVal() && in lowerFormalArguments()
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D | AMDGPUCallingConv.td | 15 class CCIfNotInReg<CCAction A> : CCIf<"!ArgFlags.isInReg()", A> {}
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D | SIISelLowering.cpp | 1356 !Arg->Flags.isInReg() && !Arg->Flags.isByVal() && PSInputNum <= 15) { in processShaderInputArgs()
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/external/llvm/lib/Target/AMDGPU/ |
D | AMDGPUCallingConv.td | 15 class CCIfNotInReg<CCAction A> : CCIf<"!ArgFlags.isInReg()", A> {}
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D | SIISelLowering.cpp | 619 if (CallConv == CallingConv::AMDGPU_PS && !Arg.Flags.isInReg() && in LowerFormalArguments()
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/ |
D | TargetCallingConv.td | 66 class CCIfInReg<CCAction A> : CCIf<"ArgFlags.isInReg()", A> {}
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
D | X86GenCallingConv.inc | 396 if (ArgFlags.isInReg()) { 426 if (ArgFlags.isInReg()) { 640 if (ArgFlags.isInReg()) { 652 if (ArgFlags.isInReg()) { 664 if (ArgFlags.isInReg()) { 2861 if (ArgFlags.isInReg()) {
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/external/llvm/lib/Target/Mips/ |
D | MipsFastISel.cpp | 1282 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal()) in fastLowerCall()
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D | MipsISelLowering.cpp | 2464 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { in CC_MipsO32()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
D | MipsFastISel.cpp | 1501 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal()) in fastLowerCall()
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D | MipsISelLowering.cpp | 2655 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { in CC_MipsO32()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCFastISel.cpp | 1523 if (Flags.isInReg() || Flags.isSRet() || Flags.isNest() || Flags.isByVal()) in fastLowerCall()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
D | PPCFastISel.cpp | 1610 if (Flags.isInReg() || Flags.isSRet() || Flags.isNest() || Flags.isByVal()) in fastLowerCall()
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAGBuilder.cpp | 2066 Entry.isInReg = true; in visitSPDescriptorParent() 7516 Entry.isInReg = false; in LowerCallTo() 7589 if (Args[i].isInReg) in LowerCallTo()
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D | TargetLowering.cpp | 103 isInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg); in setAttributes()
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/external/llvm/lib/Target/X86/ |
D | X86FastISel.cpp | 3360 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { in fastLowerCall()
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D | X86ISelLowering.cpp | 2299 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget.hasSSE1())) { in LowerCallResult() 2358 if (Flags.isInReg() || IsMCU) in callIsStructReturn() 2372 if (Flags.isInReg() || IsMCU) in argsAreStructReturn()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86FastISel.cpp | 3576 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { in fastLowerCall()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
D | AArch64FastISel.cpp | 3181 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal() || in fastLowerCall()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64FastISel.cpp | 3095 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal() || in fastLowerCall()
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