1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Calling Convention Implementation Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT, 10 MVT LocVT, CCValAssign::LocInfo LocInfo, 11 ISD::ArgFlagsTy ArgFlags, CCState &State); 12static bool CC_X86(unsigned ValNo, MVT ValVT, 13 MVT LocVT, CCValAssign::LocInfo LocInfo, 14 ISD::ArgFlagsTy ArgFlags, CCState &State); 15static bool CC_X86_32(unsigned ValNo, MVT ValVT, 16 MVT LocVT, CCValAssign::LocInfo LocInfo, 17 ISD::ArgFlagsTy ArgFlags, CCState &State); 18static bool CC_X86_32_C(unsigned ValNo, MVT ValVT, 19 MVT LocVT, CCValAssign::LocInfo LocInfo, 20 ISD::ArgFlagsTy ArgFlags, CCState &State); 21static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT, 22 MVT LocVT, CCValAssign::LocInfo LocInfo, 23 ISD::ArgFlagsTy ArgFlags, CCState &State); 24static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT, 25 MVT LocVT, CCValAssign::LocInfo LocInfo, 26 ISD::ArgFlagsTy ArgFlags, CCState &State); 27static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT, 28 MVT LocVT, CCValAssign::LocInfo LocInfo, 29 ISD::ArgFlagsTy ArgFlags, CCState &State); 30static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT, 31 MVT LocVT, CCValAssign::LocInfo LocInfo, 32 ISD::ArgFlagsTy ArgFlags, CCState &State); 33static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT, 34 MVT LocVT, CCValAssign::LocInfo LocInfo, 35 ISD::ArgFlagsTy ArgFlags, CCState &State); 36static bool CC_X86_32_Intr(unsigned ValNo, MVT ValVT, 37 MVT LocVT, CCValAssign::LocInfo LocInfo, 38 ISD::ArgFlagsTy ArgFlags, CCState &State); 39static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT, 40 MVT LocVT, CCValAssign::LocInfo LocInfo, 41 ISD::ArgFlagsTy ArgFlags, CCState &State); 42static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT, 43 MVT LocVT, CCValAssign::LocInfo LocInfo, 44 ISD::ArgFlagsTy ArgFlags, CCState &State); 45static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT, 46 MVT LocVT, CCValAssign::LocInfo LocInfo, 47 ISD::ArgFlagsTy ArgFlags, CCState &State); 48static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT, 49 MVT LocVT, CCValAssign::LocInfo LocInfo, 50 ISD::ArgFlagsTy ArgFlags, CCState &State); 51static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT, 52 MVT LocVT, CCValAssign::LocInfo LocInfo, 53 ISD::ArgFlagsTy ArgFlags, CCState &State); 54static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT, 55 MVT LocVT, CCValAssign::LocInfo LocInfo, 56 ISD::ArgFlagsTy ArgFlags, CCState &State); 57static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT, 58 MVT LocVT, CCValAssign::LocInfo LocInfo, 59 ISD::ArgFlagsTy ArgFlags, CCState &State); 60static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT, 61 MVT LocVT, CCValAssign::LocInfo LocInfo, 62 ISD::ArgFlagsTy ArgFlags, CCState &State); 63static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT, 64 MVT LocVT, CCValAssign::LocInfo LocInfo, 65 ISD::ArgFlagsTy ArgFlags, CCState &State); 66static bool CC_X86_64(unsigned ValNo, MVT ValVT, 67 MVT LocVT, CCValAssign::LocInfo LocInfo, 68 ISD::ArgFlagsTy ArgFlags, CCState &State); 69static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT, 70 MVT LocVT, CCValAssign::LocInfo LocInfo, 71 ISD::ArgFlagsTy ArgFlags, CCState &State); 72static bool CC_X86_64_C(unsigned ValNo, MVT ValVT, 73 MVT LocVT, CCValAssign::LocInfo LocInfo, 74 ISD::ArgFlagsTy ArgFlags, CCState &State); 75static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT, 76 MVT LocVT, CCValAssign::LocInfo LocInfo, 77 ISD::ArgFlagsTy ArgFlags, CCState &State); 78static bool CC_X86_64_HHVM(unsigned ValNo, MVT ValVT, 79 MVT LocVT, CCValAssign::LocInfo LocInfo, 80 ISD::ArgFlagsTy ArgFlags, CCState &State); 81static bool CC_X86_64_HHVM_C(unsigned ValNo, MVT ValVT, 82 MVT LocVT, CCValAssign::LocInfo LocInfo, 83 ISD::ArgFlagsTy ArgFlags, CCState &State); 84static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT, 85 MVT LocVT, CCValAssign::LocInfo LocInfo, 86 ISD::ArgFlagsTy ArgFlags, CCState &State); 87static bool CC_X86_64_Intr(unsigned ValNo, MVT ValVT, 88 MVT LocVT, CCValAssign::LocInfo LocInfo, 89 ISD::ArgFlagsTy ArgFlags, CCState &State); 90static bool CC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT, 91 MVT LocVT, CCValAssign::LocInfo LocInfo, 92 ISD::ArgFlagsTy ArgFlags, CCState &State); 93static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT, 94 MVT LocVT, CCValAssign::LocInfo LocInfo, 95 ISD::ArgFlagsTy ArgFlags, CCState &State); 96static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT, 97 MVT LocVT, CCValAssign::LocInfo LocInfo, 98 ISD::ArgFlagsTy ArgFlags, CCState &State); 99static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT, 100 MVT LocVT, CCValAssign::LocInfo LocInfo, 101 ISD::ArgFlagsTy ArgFlags, CCState &State); 102static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT, 103 MVT LocVT, CCValAssign::LocInfo LocInfo, 104 ISD::ArgFlagsTy ArgFlags, CCState &State); 105static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT, 106 MVT LocVT, CCValAssign::LocInfo LocInfo, 107 ISD::ArgFlagsTy ArgFlags, CCState &State); 108static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT, 109 MVT LocVT, CCValAssign::LocInfo LocInfo, 110 ISD::ArgFlagsTy ArgFlags, CCState &State); 111static bool RetCC_X86(unsigned ValNo, MVT ValVT, 112 MVT LocVT, CCValAssign::LocInfo LocInfo, 113 ISD::ArgFlagsTy ArgFlags, CCState &State); 114static bool RetCC_X86Common(unsigned ValNo, MVT ValVT, 115 MVT LocVT, CCValAssign::LocInfo LocInfo, 116 ISD::ArgFlagsTy ArgFlags, CCState &State); 117static bool RetCC_X86_32(unsigned ValNo, MVT ValVT, 118 MVT LocVT, CCValAssign::LocInfo LocInfo, 119 ISD::ArgFlagsTy ArgFlags, CCState &State); 120static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT, 121 MVT LocVT, CCValAssign::LocInfo LocInfo, 122 ISD::ArgFlagsTy ArgFlags, CCState &State); 123static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT, 124 MVT LocVT, CCValAssign::LocInfo LocInfo, 125 ISD::ArgFlagsTy ArgFlags, CCState &State); 126static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT, 127 MVT LocVT, CCValAssign::LocInfo LocInfo, 128 ISD::ArgFlagsTy ArgFlags, CCState &State); 129static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT, 130 MVT LocVT, CCValAssign::LocInfo LocInfo, 131 ISD::ArgFlagsTy ArgFlags, CCState &State); 132static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT, 133 MVT LocVT, CCValAssign::LocInfo LocInfo, 134 ISD::ArgFlagsTy ArgFlags, CCState &State); 135static bool RetCC_X86_64(unsigned ValNo, MVT ValVT, 136 MVT LocVT, CCValAssign::LocInfo LocInfo, 137 ISD::ArgFlagsTy ArgFlags, CCState &State); 138static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT, 139 MVT LocVT, CCValAssign::LocInfo LocInfo, 140 ISD::ArgFlagsTy ArgFlags, CCState &State); 141static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT, 142 MVT LocVT, CCValAssign::LocInfo LocInfo, 143 ISD::ArgFlagsTy ArgFlags, CCState &State); 144static bool RetCC_X86_64_HHVM(unsigned ValNo, MVT ValVT, 145 MVT LocVT, CCValAssign::LocInfo LocInfo, 146 ISD::ArgFlagsTy ArgFlags, CCState &State); 147static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT, 148 MVT LocVT, CCValAssign::LocInfo LocInfo, 149 ISD::ArgFlagsTy ArgFlags, CCState &State); 150static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT, 151 MVT LocVT, CCValAssign::LocInfo LocInfo, 152 ISD::ArgFlagsTy ArgFlags, CCState &State); 153static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT, 154 MVT LocVT, CCValAssign::LocInfo LocInfo, 155 ISD::ArgFlagsTy ArgFlags, CCState &State); 156static bool RetCC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT, 157 MVT LocVT, CCValAssign::LocInfo LocInfo, 158 ISD::ArgFlagsTy ArgFlags, CCState &State); 159static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT, 160 MVT LocVT, CCValAssign::LocInfo LocInfo, 161 ISD::ArgFlagsTy ArgFlags, CCState &State); 162static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT, 163 MVT LocVT, CCValAssign::LocInfo LocInfo, 164 ISD::ArgFlagsTy ArgFlags, CCState &State); 165static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT, 166 MVT LocVT, CCValAssign::LocInfo LocInfo, 167 ISD::ArgFlagsTy ArgFlags, CCState &State); 168 169 170static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT, 171 MVT LocVT, CCValAssign::LocInfo LocInfo, 172 ISD::ArgFlagsTy ArgFlags, CCState &State) { 173 174 if (LocVT == MVT::i32) { 175 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { 176 static const MCPhysReg RegList1[] = { 177 X86::ECX, X86::EDX, X86::R8D, X86::R9D 178 }; 179 if (unsigned Reg = State.AllocateReg(RegList1)) { 180 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 181 return false; 182 } 183 } 184 } 185 186 if (LocVT == MVT::i64) { 187 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { 188 static const MCPhysReg RegList2[] = { 189 X86::RCX, X86::RDX, X86::R8, X86::R9 190 }; 191 if (unsigned Reg = State.AllocateReg(RegList2)) { 192 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 193 return false; 194 } 195 } 196 } 197 198 if (LocVT == MVT::i32) { 199 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 200 static const MCPhysReg RegList3[] = { 201 X86::EDI, X86::ESI, X86::EDX, X86::ECX 202 }; 203 if (unsigned Reg = State.AllocateReg(RegList3)) { 204 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 205 return false; 206 } 207 } 208 } 209 210 if (LocVT == MVT::i64) { 211 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 212 static const MCPhysReg RegList4[] = { 213 X86::RDI, X86::RSI, X86::RDX, X86::RCX 214 }; 215 if (unsigned Reg = State.AllocateReg(RegList4)) { 216 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 217 return false; 218 } 219 } 220 } 221 222 if (LocVT == MVT::i32) { 223 unsigned Offset5 = State.AllocateStack(4, 4); 224 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo)); 225 return false; 226 } 227 228 if (LocVT == MVT::f32 || 229 LocVT == MVT::f64 || 230 LocVT == MVT::v4i32 || 231 LocVT == MVT::v2i64 || 232 LocVT == MVT::v4f32 || 233 LocVT == MVT::v2f64) { 234 static const MCPhysReg RegList6[] = { 235 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 236 }; 237 if (unsigned Reg = State.AllocateReg(RegList6)) { 238 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 239 return false; 240 } 241 } 242 243 if (LocVT == MVT::v8f32 || 244 LocVT == MVT::v4f64 || 245 LocVT == MVT::v8i32 || 246 LocVT == MVT::v4i64) { 247 static const MCPhysReg RegList7[] = { 248 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3 249 }; 250 if (unsigned Reg = State.AllocateReg(RegList7)) { 251 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 252 return false; 253 } 254 } 255 256 if (LocVT == MVT::v16f32 || 257 LocVT == MVT::v8f64 || 258 LocVT == MVT::v16i32 || 259 LocVT == MVT::v8i64) { 260 static const MCPhysReg RegList8[] = { 261 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 262 }; 263 if (unsigned Reg = State.AllocateReg(RegList8)) { 264 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 265 return false; 266 } 267 } 268 269 if (LocVT == MVT::v16i1 || 270 LocVT == MVT::v8i1) { 271 if (unsigned Reg = State.AllocateReg(X86::K1)) { 272 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 273 return false; 274 } 275 } 276 277 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { 278 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 279 return false; 280 } 281 282 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 283 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 284 return false; 285 } 286 287 if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 288 return false; 289 290 return true; // CC didn't match. 291} 292 293 294static bool CC_X86(unsigned ValNo, MVT ValVT, 295 MVT LocVT, CCValAssign::LocInfo LocInfo, 296 ISD::ArgFlagsTy ArgFlags, CCState &State) { 297 298 if (State.getCallingConv() == CallingConv::Intel_OCL_BI) { 299 if (!CC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 300 return false; 301 } 302 303 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 304 if (!CC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 305 return false; 306 } 307 308 if (!CC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 309 return false; 310 311 return true; // CC didn't match. 312} 313 314 315static bool CC_X86_32(unsigned ValNo, MVT ValVT, 316 MVT LocVT, CCValAssign::LocInfo LocInfo, 317 ISD::ArgFlagsTy ArgFlags, CCState &State) { 318 319 if (State.getCallingConv() == CallingConv::X86_INTR) { 320 if (!CC_X86_32_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 321 return false; 322 } 323 324 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetMCU()) { 325 if (!CC_X86_32_MCU(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 326 return false; 327 } 328 329 if (State.getCallingConv() == CallingConv::X86_FastCall) { 330 if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 331 return false; 332 } 333 334 if (State.getCallingConv() == CallingConv::X86_VectorCall) { 335 if (!CC_X86_Win32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 336 return false; 337 } 338 339 if (State.getCallingConv() == CallingConv::X86_ThisCall) { 340 if (!CC_X86_32_ThisCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 341 return false; 342 } 343 344 if (State.getCallingConv() == CallingConv::Fast) { 345 if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 346 return false; 347 } 348 349 if (State.getCallingConv() == CallingConv::GHC) { 350 if (!CC_X86_32_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 351 return false; 352 } 353 354 if (State.getCallingConv() == CallingConv::HiPE) { 355 if (!CC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 356 return false; 357 } 358 359 if (State.getCallingConv() == CallingConv::X86_RegCall) { 360 if (!CC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 361 return false; 362 } 363 364 if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 365 return false; 366 367 return true; // CC didn't match. 368} 369 370 371static bool CC_X86_32_C(unsigned ValNo, MVT ValVT, 372 MVT LocVT, CCValAssign::LocInfo LocInfo, 373 ISD::ArgFlagsTy ArgFlags, CCState &State) { 374 375 if (LocVT == MVT::i1 || 376 LocVT == MVT::i8 || 377 LocVT == MVT::i16 || 378 LocVT == MVT::v1i1) { 379 LocVT = MVT::i32; 380 if (ArgFlags.isSExt()) 381 LocInfo = CCValAssign::SExt; 382 else if (ArgFlags.isZExt()) 383 LocInfo = CCValAssign::ZExt; 384 else 385 LocInfo = CCValAssign::AExt; 386 } 387 388 if (ArgFlags.isNest()) { 389 if (unsigned Reg = State.AllocateReg(X86::ECX)) { 390 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 391 return false; 392 } 393 } 394 395 if (!State.isVarArg()) { 396 if (ArgFlags.isInReg()) { 397 if (LocVT == MVT::i32) { 398 static const MCPhysReg RegList1[] = { 399 X86::EAX, X86::EDX, X86::ECX 400 }; 401 if (unsigned Reg = State.AllocateReg(RegList1)) { 402 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 403 return false; 404 } 405 } 406 } 407 } 408 409 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 410 return false; 411 412 return true; // CC didn't match. 413} 414 415 416static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT, 417 MVT LocVT, CCValAssign::LocInfo LocInfo, 418 ISD::ArgFlagsTy ArgFlags, CCState &State) { 419 420 if (ArgFlags.isByVal()) { 421 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags); 422 return false; 423 } 424 425 if (!State.isVarArg()) { 426 if (ArgFlags.isInReg()) { 427 if (LocVT == MVT::f32 || 428 LocVT == MVT::f64) { 429 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) { 430 static const MCPhysReg RegList1[] = { 431 X86::XMM0, X86::XMM1, X86::XMM2 432 }; 433 if (unsigned Reg = State.AllocateReg(RegList1)) { 434 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 435 return false; 436 } 437 } 438 } 439 } 440 } 441 442 if (!State.isVarArg()) { 443 if (LocVT == MVT::x86mmx) { 444 static const MCPhysReg RegList2[] = { 445 X86::MM0, X86::MM1, X86::MM2 446 }; 447 if (unsigned Reg = State.AllocateReg(RegList2)) { 448 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 449 return false; 450 } 451 } 452 } 453 454 if (LocVT == MVT::i32 || 455 LocVT == MVT::f32) { 456 unsigned Offset3 = State.AllocateStack(4, 4); 457 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo)); 458 return false; 459 } 460 461 if (LocVT == MVT::f64) { 462 unsigned Offset4 = State.AllocateStack(8, 4); 463 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo)); 464 return false; 465 } 466 467 if (LocVT == MVT::f80) { 468 unsigned Offset5 = State.AllocateStack( 469 State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 4); 470 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo)); 471 return false; 472 } 473 474 if (LocVT == MVT::v2i1) { 475 LocVT = MVT::v2i64; 476 if (ArgFlags.isSExt()) 477 LocInfo = CCValAssign::SExt; 478 else if (ArgFlags.isZExt()) 479 LocInfo = CCValAssign::ZExt; 480 else 481 LocInfo = CCValAssign::AExt; 482 } 483 484 if (LocVT == MVT::v4i1) { 485 LocVT = MVT::v4i32; 486 if (ArgFlags.isSExt()) 487 LocInfo = CCValAssign::SExt; 488 else if (ArgFlags.isZExt()) 489 LocInfo = CCValAssign::ZExt; 490 else 491 LocInfo = CCValAssign::AExt; 492 } 493 494 if (LocVT == MVT::v8i1) { 495 LocVT = MVT::v8i16; 496 if (ArgFlags.isSExt()) 497 LocInfo = CCValAssign::SExt; 498 else if (ArgFlags.isZExt()) 499 LocInfo = CCValAssign::ZExt; 500 else 501 LocInfo = CCValAssign::AExt; 502 } 503 504 if (LocVT == MVT::v16i1) { 505 LocVT = MVT::v16i8; 506 if (ArgFlags.isSExt()) 507 LocInfo = CCValAssign::SExt; 508 else if (ArgFlags.isZExt()) 509 LocInfo = CCValAssign::ZExt; 510 else 511 LocInfo = CCValAssign::AExt; 512 } 513 514 if (LocVT == MVT::v32i1) { 515 LocVT = MVT::v32i8; 516 if (ArgFlags.isSExt()) 517 LocInfo = CCValAssign::SExt; 518 else if (ArgFlags.isZExt()) 519 LocInfo = CCValAssign::ZExt; 520 else 521 LocInfo = CCValAssign::AExt; 522 } 523 524 if (LocVT == MVT::v64i1) { 525 LocVT = MVT::v64i8; 526 if (ArgFlags.isSExt()) 527 LocInfo = CCValAssign::SExt; 528 else if (ArgFlags.isZExt()) 529 LocInfo = CCValAssign::ZExt; 530 else 531 LocInfo = CCValAssign::AExt; 532 } 533 534 if (LocVT == MVT::x86mmx) { 535 unsigned Offset6 = State.AllocateStack(8, 4); 536 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo)); 537 return false; 538 } 539 540 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) { 541 if (!CC_X86_32_Vector_Darwin(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 542 return false; 543 } 544 545 if (!CC_X86_32_Vector_Standard(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 546 return false; 547 548 return true; // CC didn't match. 549} 550 551 552static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT, 553 MVT LocVT, CCValAssign::LocInfo LocInfo, 554 ISD::ArgFlagsTy ArgFlags, CCState &State) { 555 556 if (ArgFlags.isByVal()) { 557 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags); 558 return false; 559 } 560 561 if (LocVT == MVT::i1 || 562 LocVT == MVT::i8 || 563 LocVT == MVT::i16 || 564 LocVT == MVT::v1i1) { 565 LocVT = MVT::i32; 566 if (ArgFlags.isSExt()) 567 LocInfo = CCValAssign::SExt; 568 else if (ArgFlags.isZExt()) 569 LocInfo = CCValAssign::ZExt; 570 else 571 LocInfo = CCValAssign::AExt; 572 } 573 574 if (ArgFlags.isNest()) { 575 if (unsigned Reg = State.AllocateReg(X86::EAX)) { 576 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 577 return false; 578 } 579 } 580 581 if (LocVT == MVT::i32) { 582 static const MCPhysReg RegList1[] = { 583 X86::ECX, X86::EDX 584 }; 585 if (unsigned Reg = State.AllocateReg(RegList1)) { 586 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 587 return false; 588 } 589 } 590 591 if (!State.isVarArg()) { 592 if (LocVT == MVT::f32 || 593 LocVT == MVT::f64) { 594 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) { 595 static const MCPhysReg RegList2[] = { 596 X86::XMM0, X86::XMM1, X86::XMM2 597 }; 598 if (unsigned Reg = State.AllocateReg(RegList2)) { 599 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 600 return false; 601 } 602 } 603 } 604 } 605 606 if (LocVT == MVT::f64) { 607 unsigned Offset3 = State.AllocateStack(8, 8); 608 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo)); 609 return false; 610 } 611 612 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 613 return false; 614 615 return true; // CC didn't match. 616} 617 618 619static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT, 620 MVT LocVT, CCValAssign::LocInfo LocInfo, 621 ISD::ArgFlagsTy ArgFlags, CCState &State) { 622 623 if (LocVT == MVT::i1) { 624 LocVT = MVT::i8; 625 if (ArgFlags.isSExt()) 626 LocInfo = CCValAssign::SExt; 627 else if (ArgFlags.isZExt()) 628 LocInfo = CCValAssign::ZExt; 629 else 630 LocInfo = CCValAssign::AExt; 631 } 632 633 if (ArgFlags.isNest()) { 634 if (unsigned Reg = State.AllocateReg(X86::EAX)) { 635 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 636 return false; 637 } 638 } 639 640 if (ArgFlags.isInReg()) { 641 if (LocVT == MVT::i8) { 642 static const MCPhysReg RegList1[] = { 643 X86::CL, X86::DL 644 }; 645 if (unsigned Reg = State.AllocateReg(RegList1)) { 646 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 647 return false; 648 } 649 } 650 } 651 652 if (ArgFlags.isInReg()) { 653 if (LocVT == MVT::i16) { 654 static const MCPhysReg RegList2[] = { 655 X86::CX, X86::DX 656 }; 657 if (unsigned Reg = State.AllocateReg(RegList2)) { 658 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 659 return false; 660 } 661 } 662 } 663 664 if (ArgFlags.isInReg()) { 665 if (LocVT == MVT::i32) { 666 static const MCPhysReg RegList3[] = { 667 X86::ECX, X86::EDX 668 }; 669 if (unsigned Reg = State.AllocateReg(RegList3)) { 670 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 671 return false; 672 } 673 } 674 } 675 676 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 677 return false; 678 679 return true; // CC didn't match. 680} 681 682 683static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT, 684 MVT LocVT, CCValAssign::LocInfo LocInfo, 685 ISD::ArgFlagsTy ArgFlags, CCState &State) { 686 687 if (LocVT == MVT::i8 || 688 LocVT == MVT::i16) { 689 LocVT = MVT::i32; 690 if (ArgFlags.isSExt()) 691 LocInfo = CCValAssign::SExt; 692 else if (ArgFlags.isZExt()) 693 LocInfo = CCValAssign::ZExt; 694 else 695 LocInfo = CCValAssign::AExt; 696 } 697 698 if (LocVT == MVT::i32) { 699 static const MCPhysReg RegList1[] = { 700 X86::EBX, X86::EBP, X86::EDI, X86::ESI 701 }; 702 if (unsigned Reg = State.AllocateReg(RegList1)) { 703 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 704 return false; 705 } 706 } 707 708 return true; // CC didn't match. 709} 710 711 712static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT, 713 MVT LocVT, CCValAssign::LocInfo LocInfo, 714 ISD::ArgFlagsTy ArgFlags, CCState &State) { 715 716 if (LocVT == MVT::i8 || 717 LocVT == MVT::i16) { 718 LocVT = MVT::i32; 719 if (ArgFlags.isSExt()) 720 LocInfo = CCValAssign::SExt; 721 else if (ArgFlags.isZExt()) 722 LocInfo = CCValAssign::ZExt; 723 else 724 LocInfo = CCValAssign::AExt; 725 } 726 727 if (LocVT == MVT::i32) { 728 static const MCPhysReg RegList1[] = { 729 X86::ESI, X86::EBP, X86::EAX, X86::EDX, X86::ECX 730 }; 731 if (unsigned Reg = State.AllocateReg(RegList1)) { 732 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 733 return false; 734 } 735 } 736 737 if (LocVT == MVT::i32 || 738 LocVT == MVT::f32) { 739 unsigned Offset2 = State.AllocateStack(4, 4); 740 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); 741 return false; 742 } 743 744 return true; // CC didn't match. 745} 746 747 748static bool CC_X86_32_Intr(unsigned ValNo, MVT ValVT, 749 MVT LocVT, CCValAssign::LocInfo LocInfo, 750 ISD::ArgFlagsTy ArgFlags, CCState &State) { 751 752 unsigned Offset1 = State.AllocateStack(4, 4); 753 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); 754 return false; 755 756 return true; // CC didn't match. 757} 758 759 760static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT, 761 MVT LocVT, CCValAssign::LocInfo LocInfo, 762 ISD::ArgFlagsTy ArgFlags, CCState &State) { 763 764 if (ArgFlags.isByVal()) { 765 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags); 766 return false; 767 } 768 769 if (LocVT == MVT::i1 || 770 LocVT == MVT::i8 || 771 LocVT == MVT::i16 || 772 LocVT == MVT::v1i1) { 773 LocVT = MVT::i32; 774 if (ArgFlags.isSExt()) 775 LocInfo = CCValAssign::SExt; 776 else if (ArgFlags.isZExt()) 777 LocInfo = CCValAssign::ZExt; 778 else 779 LocInfo = CCValAssign::AExt; 780 } 781 782 if (!State.isVarArg()) { 783 if (LocVT == MVT::i32) { 784 if (CC_X86_32_MCUInReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 785 return false; 786 } 787 } 788 789 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 790 return false; 791 792 return true; // CC didn't match. 793} 794 795 796static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT, 797 MVT LocVT, CCValAssign::LocInfo LocInfo, 798 ISD::ArgFlagsTy ArgFlags, CCState &State) { 799 800 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 801 if (ArgFlags.isByVal()) { 802 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags); 803 return false; 804 } 805 } 806 807 if (ArgFlags.isByVal()) { 808 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags); 809 return false; 810 } 811 812 if (LocVT == MVT::i1 || 813 LocVT == MVT::i8 || 814 LocVT == MVT::i16 || 815 LocVT == MVT::v1i1) { 816 LocVT = MVT::i32; 817 if (ArgFlags.isSExt()) 818 LocInfo = CCValAssign::SExt; 819 else if (ArgFlags.isZExt()) 820 LocInfo = CCValAssign::ZExt; 821 else 822 LocInfo = CCValAssign::AExt; 823 } 824 825 if (LocVT == MVT::v8i1 || 826 LocVT == MVT::v16i1 || 827 LocVT == MVT::v32i1) { 828 LocVT = MVT::i32; 829 if (ArgFlags.isSExt()) 830 LocInfo = CCValAssign::SExt; 831 else if (ArgFlags.isZExt()) 832 LocInfo = CCValAssign::ZExt; 833 else 834 LocInfo = CCValAssign::AExt; 835 } 836 837 if (LocVT == MVT::i32) { 838 static const MCPhysReg RegList1[] = { 839 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI 840 }; 841 if (unsigned Reg = State.AllocateReg(RegList1)) { 842 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 843 return false; 844 } 845 } 846 847 if (LocVT == MVT::i64) { 848 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 849 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 850 return false; 851 } 852 } 853 854 if (LocVT == MVT::v64i1) { 855 LocVT = MVT::i64; 856 if (ArgFlags.isSExt()) 857 LocInfo = CCValAssign::SExt; 858 else if (ArgFlags.isZExt()) 859 LocInfo = CCValAssign::ZExt; 860 else 861 LocInfo = CCValAssign::AExt; 862 } 863 864 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 865 if (LocVT == MVT::i64) { 866 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 867 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 868 return false; 869 } 870 } 871 } 872 873 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { 874 if (LocVT == MVT::i64) { 875 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 876 return false; 877 } 878 } 879 880 if (LocVT == MVT::f32 || 881 LocVT == MVT::f64 || 882 LocVT == MVT::f128) { 883 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 884 static const MCPhysReg RegList2[] = { 885 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 886 }; 887 if (unsigned Reg = State.AllocateReg(RegList2)) { 888 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 889 return false; 890 } 891 } 892 } 893 894 if (LocVT == MVT::f80) { 895 if (unsigned Reg = State.AllocateReg(X86::FP0)) { 896 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 897 return false; 898 } 899 } 900 901 if (LocVT == MVT::v16i8 || 902 LocVT == MVT::v8i16 || 903 LocVT == MVT::v4i32 || 904 LocVT == MVT::v2i64 || 905 LocVT == MVT::v4f32 || 906 LocVT == MVT::v2f64) { 907 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 908 static const MCPhysReg RegList3[] = { 909 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 910 }; 911 if (unsigned Reg = State.AllocateReg(RegList3)) { 912 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 913 return false; 914 } 915 } 916 } 917 918 if (LocVT == MVT::v32i8 || 919 LocVT == MVT::v16i16 || 920 LocVT == MVT::v8i32 || 921 LocVT == MVT::v4i64 || 922 LocVT == MVT::v8f32 || 923 LocVT == MVT::v4f64) { 924 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { 925 static const MCPhysReg RegList4[] = { 926 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7 927 }; 928 if (unsigned Reg = State.AllocateReg(RegList4)) { 929 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 930 return false; 931 } 932 } 933 } 934 935 if (LocVT == MVT::v64i8 || 936 LocVT == MVT::v32i16 || 937 LocVT == MVT::v16i32 || 938 LocVT == MVT::v8i64 || 939 LocVT == MVT::v16f32 || 940 LocVT == MVT::v8f64) { 941 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { 942 static const MCPhysReg RegList5[] = { 943 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 944 }; 945 if (unsigned Reg = State.AllocateReg(RegList5)) { 946 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 947 return false; 948 } 949 } 950 } 951 952 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 953 if (LocVT == MVT::i32 || 954 LocVT == MVT::i64 || 955 LocVT == MVT::f32 || 956 LocVT == MVT::f64) { 957 unsigned Offset6 = State.AllocateStack(8, 8); 958 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo)); 959 return false; 960 } 961 } 962 963 if (LocVT == MVT::i32 || 964 LocVT == MVT::f32) { 965 unsigned Offset7 = State.AllocateStack(4, 4); 966 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo)); 967 return false; 968 } 969 970 if (LocVT == MVT::i64 || 971 LocVT == MVT::f64) { 972 unsigned Offset8 = State.AllocateStack(8, 4); 973 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo)); 974 return false; 975 } 976 977 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 978 if (LocVT == MVT::x86mmx) { 979 unsigned Offset9 = State.AllocateStack(8, 8); 980 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo)); 981 return false; 982 } 983 } 984 985 if (LocVT == MVT::x86mmx) { 986 unsigned Offset10 = State.AllocateStack(8, 4); 987 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo)); 988 return false; 989 } 990 991 if (LocVT == MVT::f80 || 992 LocVT == MVT::f128) { 993 unsigned Offset11 = State.AllocateStack( 994 State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 995 State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext()))); 996 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo)); 997 return false; 998 } 999 1000 if (LocVT == MVT::v16i8 || 1001 LocVT == MVT::v8i16 || 1002 LocVT == MVT::v4i32 || 1003 LocVT == MVT::v2i64 || 1004 LocVT == MVT::v4f32 || 1005 LocVT == MVT::v2f64) { 1006 unsigned Offset12 = State.AllocateStack(16, 16); 1007 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo)); 1008 return false; 1009 } 1010 1011 if (LocVT == MVT::v32i8 || 1012 LocVT == MVT::v16i16 || 1013 LocVT == MVT::v8i32 || 1014 LocVT == MVT::v4i64 || 1015 LocVT == MVT::v8f32 || 1016 LocVT == MVT::v4f64) { 1017 unsigned Offset13 = State.AllocateStack(32, 32); 1018 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo)); 1019 return false; 1020 } 1021 1022 if (LocVT == MVT::v16i32 || 1023 LocVT == MVT::v8i64 || 1024 LocVT == MVT::v16f32 || 1025 LocVT == MVT::v8f64) { 1026 unsigned Offset14 = State.AllocateStack(64, 64); 1027 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo)); 1028 return false; 1029 } 1030 1031 return true; // CC didn't match. 1032} 1033 1034 1035static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT, 1036 MVT LocVT, CCValAssign::LocInfo LocInfo, 1037 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1038 1039 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetCygMing()) { 1040 if (!CC_X86_32_ThisCall_Mingw(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1041 return false; 1042 } 1043 1044 if (!CC_X86_32_ThisCall_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1045 return false; 1046 1047 return true; // CC didn't match. 1048} 1049 1050 1051static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT, 1052 MVT LocVT, CCValAssign::LocInfo LocInfo, 1053 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1054 1055 if (LocVT == MVT::i32) { 1056 if (unsigned Reg = State.AllocateReg(X86::ECX)) { 1057 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1058 return false; 1059 } 1060 } 1061 1062 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1063 return false; 1064 1065 return true; // CC didn't match. 1066} 1067 1068 1069static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT, 1070 MVT LocVT, CCValAssign::LocInfo LocInfo, 1071 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1072 1073 if (LocVT == MVT::i1 || 1074 LocVT == MVT::i8 || 1075 LocVT == MVT::i16 || 1076 LocVT == MVT::v1i1) { 1077 LocVT = MVT::i32; 1078 if (ArgFlags.isSExt()) 1079 LocInfo = CCValAssign::SExt; 1080 else if (ArgFlags.isZExt()) 1081 LocInfo = CCValAssign::ZExt; 1082 else 1083 LocInfo = CCValAssign::AExt; 1084 } 1085 1086 if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1087 return false; 1088 1089 return true; // CC didn't match. 1090} 1091 1092 1093static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT, 1094 MVT LocVT, CCValAssign::LocInfo LocInfo, 1095 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1096 1097 if (LocVT == MVT::i1 || 1098 LocVT == MVT::i8 || 1099 LocVT == MVT::i16 || 1100 LocVT == MVT::v1i1) { 1101 LocVT = MVT::i32; 1102 if (ArgFlags.isSExt()) 1103 LocInfo = CCValAssign::SExt; 1104 else if (ArgFlags.isZExt()) 1105 LocInfo = CCValAssign::ZExt; 1106 else 1107 LocInfo = CCValAssign::AExt; 1108 } 1109 1110 if (ArgFlags.isSRet()) { 1111 unsigned Offset1 = State.AllocateStack(4, 4); 1112 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); 1113 return false; 1114 } 1115 1116 if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1117 return false; 1118 1119 return true; // CC didn't match. 1120} 1121 1122 1123static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT, 1124 MVT LocVT, CCValAssign::LocInfo LocInfo, 1125 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1126 1127 if (LocVT == MVT::v16i8 || 1128 LocVT == MVT::v8i16 || 1129 LocVT == MVT::v4i32 || 1130 LocVT == MVT::v2i64 || 1131 LocVT == MVT::v4f32 || 1132 LocVT == MVT::v2f64) { 1133 unsigned Offset1 = State.AllocateStack(16, 16); 1134 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); 1135 return false; 1136 } 1137 1138 if (LocVT == MVT::v32i8 || 1139 LocVT == MVT::v16i16 || 1140 LocVT == MVT::v8i32 || 1141 LocVT == MVT::v4i64 || 1142 LocVT == MVT::v8f32 || 1143 LocVT == MVT::v4f64) { 1144 unsigned Offset2 = State.AllocateStack(32, 32); 1145 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); 1146 return false; 1147 } 1148 1149 if (LocVT == MVT::v64i8 || 1150 LocVT == MVT::v32i16 || 1151 LocVT == MVT::v16i32 || 1152 LocVT == MVT::v8i64 || 1153 LocVT == MVT::v16f32 || 1154 LocVT == MVT::v8f64) { 1155 unsigned Offset3 = State.AllocateStack(64, 64); 1156 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo)); 1157 return false; 1158 } 1159 1160 return true; // CC didn't match. 1161} 1162 1163 1164static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT, 1165 MVT LocVT, CCValAssign::LocInfo LocInfo, 1166 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1167 1168 if (!State.isVarArg()) { 1169 if (LocVT == MVT::v16i8 || 1170 LocVT == MVT::v8i16 || 1171 LocVT == MVT::v4i32 || 1172 LocVT == MVT::v2i64 || 1173 LocVT == MVT::v4f32 || 1174 LocVT == MVT::v2f64) { 1175 static const MCPhysReg RegList1[] = { 1176 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1177 }; 1178 if (unsigned Reg = State.AllocateReg(RegList1)) { 1179 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1180 return false; 1181 } 1182 } 1183 } 1184 1185 if (!State.isVarArg()) { 1186 if (LocVT == MVT::v32i8 || 1187 LocVT == MVT::v16i16 || 1188 LocVT == MVT::v8i32 || 1189 LocVT == MVT::v4i64 || 1190 LocVT == MVT::v8f32 || 1191 LocVT == MVT::v4f64) { 1192 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { 1193 static const MCPhysReg RegList2[] = { 1194 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3 1195 }; 1196 if (unsigned Reg = State.AllocateReg(RegList2)) { 1197 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1198 return false; 1199 } 1200 } 1201 } 1202 } 1203 1204 if (!State.isVarArg()) { 1205 if (LocVT == MVT::v64i8 || 1206 LocVT == MVT::v32i16 || 1207 LocVT == MVT::v16i32 || 1208 LocVT == MVT::v8i64 || 1209 LocVT == MVT::v16f32 || 1210 LocVT == MVT::v8f64) { 1211 static const MCPhysReg RegList3[] = { 1212 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 1213 }; 1214 if (unsigned Reg = State.AllocateReg(RegList3)) { 1215 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1216 return false; 1217 } 1218 } 1219 } 1220 1221 if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1222 return false; 1223 1224 return true; // CC didn't match. 1225} 1226 1227 1228static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT, 1229 MVT LocVT, CCValAssign::LocInfo LocInfo, 1230 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1231 1232 if (!State.isVarArg()) { 1233 if (LocVT == MVT::v16i8 || 1234 LocVT == MVT::v8i16 || 1235 LocVT == MVT::v4i32 || 1236 LocVT == MVT::v2i64 || 1237 LocVT == MVT::v4f32 || 1238 LocVT == MVT::v2f64) { 1239 static const MCPhysReg RegList1[] = { 1240 X86::XMM0, X86::XMM1, X86::XMM2 1241 }; 1242 if (unsigned Reg = State.AllocateReg(RegList1)) { 1243 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1244 return false; 1245 } 1246 } 1247 } 1248 1249 if (!State.isVarArg()) { 1250 if (LocVT == MVT::v32i8 || 1251 LocVT == MVT::v16i16 || 1252 LocVT == MVT::v8i32 || 1253 LocVT == MVT::v4i64 || 1254 LocVT == MVT::v8f32 || 1255 LocVT == MVT::v4f64) { 1256 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { 1257 static const MCPhysReg RegList2[] = { 1258 X86::YMM0, X86::YMM1, X86::YMM2 1259 }; 1260 if (unsigned Reg = State.AllocateReg(RegList2)) { 1261 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1262 return false; 1263 } 1264 } 1265 } 1266 } 1267 1268 if (!State.isVarArg()) { 1269 if (LocVT == MVT::v64i8 || 1270 LocVT == MVT::v32i16 || 1271 LocVT == MVT::v16i32 || 1272 LocVT == MVT::v8i64 || 1273 LocVT == MVT::v16f32 || 1274 LocVT == MVT::v8f64) { 1275 static const MCPhysReg RegList3[] = { 1276 X86::ZMM0, X86::ZMM1, X86::ZMM2 1277 }; 1278 if (unsigned Reg = State.AllocateReg(RegList3)) { 1279 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1280 return false; 1281 } 1282 } 1283 } 1284 1285 if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1286 return false; 1287 1288 return true; // CC didn't match. 1289} 1290 1291 1292static bool CC_X86_64(unsigned ValNo, MVT ValVT, 1293 MVT LocVT, CCValAssign::LocInfo LocInfo, 1294 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1295 1296 if (State.getCallingConv() == CallingConv::GHC) { 1297 if (!CC_X86_64_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1298 return false; 1299 } 1300 1301 if (State.getCallingConv() == CallingConv::HiPE) { 1302 if (!CC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1303 return false; 1304 } 1305 1306 if (State.getCallingConv() == CallingConv::WebKit_JS) { 1307 if (!CC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1308 return false; 1309 } 1310 1311 if (State.getCallingConv() == CallingConv::AnyReg) { 1312 if (!CC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1313 return false; 1314 } 1315 1316 if (State.getCallingConv() == CallingConv::Win64) { 1317 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1318 return false; 1319 } 1320 1321 if (State.getCallingConv() == CallingConv::X86_64_SysV) { 1322 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1323 return false; 1324 } 1325 1326 if (State.getCallingConv() == CallingConv::X86_VectorCall) { 1327 if (!CC_X86_Win64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1328 return false; 1329 } 1330 1331 if (State.getCallingConv() == CallingConv::HHVM) { 1332 if (!CC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1333 return false; 1334 } 1335 1336 if (State.getCallingConv() == CallingConv::HHVM_C) { 1337 if (!CC_X86_64_HHVM_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1338 return false; 1339 } 1340 1341 if (State.getCallingConv() == CallingConv::X86_RegCall) { 1342 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { 1343 if (!CC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1344 return false; 1345 } 1346 } 1347 1348 if (State.getCallingConv() == CallingConv::X86_RegCall) { 1349 if (!CC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1350 return false; 1351 } 1352 1353 if (State.getCallingConv() == CallingConv::X86_INTR) { 1354 if (!CC_X86_64_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1355 return false; 1356 } 1357 1358 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { 1359 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1360 return false; 1361 } 1362 1363 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1364 return false; 1365 1366 return true; // CC didn't match. 1367} 1368 1369 1370static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT, 1371 MVT LocVT, CCValAssign::LocInfo LocInfo, 1372 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1373 1374 if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1375 return false; 1376 1377 return true; // CC didn't match. 1378} 1379 1380 1381static bool CC_X86_64_C(unsigned ValNo, MVT ValVT, 1382 MVT LocVT, CCValAssign::LocInfo LocInfo, 1383 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1384 1385 if (ArgFlags.isByVal()) { 1386 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags); 1387 return false; 1388 } 1389 1390 if (LocVT == MVT::i1 || 1391 LocVT == MVT::i8 || 1392 LocVT == MVT::i16 || 1393 LocVT == MVT::v1i1) { 1394 LocVT = MVT::i32; 1395 if (ArgFlags.isSExt()) 1396 LocInfo = CCValAssign::SExt; 1397 else if (ArgFlags.isZExt()) 1398 LocInfo = CCValAssign::ZExt; 1399 else 1400 LocInfo = CCValAssign::AExt; 1401 } 1402 1403 if (ArgFlags.isNest()) { 1404 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTarget64BitILP32()) { 1405 if (unsigned Reg = State.AllocateReg(X86::R10D)) { 1406 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1407 return false; 1408 } 1409 } 1410 } 1411 1412 if (ArgFlags.isNest()) { 1413 if (unsigned Reg = State.AllocateReg(X86::R10)) { 1414 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1415 return false; 1416 } 1417 } 1418 1419 if (ArgFlags.isSwiftSelf()) { 1420 if (LocVT == MVT::i64) { 1421 if (unsigned Reg = State.AllocateReg(X86::R13)) { 1422 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1423 return false; 1424 } 1425 } 1426 } 1427 1428 if (ArgFlags.isSwiftError()) { 1429 if (LocVT == MVT::i64) { 1430 if (unsigned Reg = State.AllocateReg(X86::R12)) { 1431 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1432 return false; 1433 } 1434 } 1435 } 1436 1437 if (State.getCallingConv() == CallingConv::Swift) { 1438 if (ArgFlags.isSRet()) { 1439 if (LocVT == MVT::i64) { 1440 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 1441 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1442 return false; 1443 } 1444 } 1445 } 1446 } 1447 1448 if (LocVT == MVT::i32) { 1449 static const MCPhysReg RegList1[] = { 1450 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D 1451 }; 1452 if (unsigned Reg = State.AllocateReg(RegList1)) { 1453 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1454 return false; 1455 } 1456 } 1457 1458 if (LocVT == MVT::i64) { 1459 static const MCPhysReg RegList2[] = { 1460 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1461 }; 1462 if (unsigned Reg = State.AllocateReg(RegList2)) { 1463 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1464 return false; 1465 } 1466 } 1467 1468 if (LocVT == MVT::x86mmx) { 1469 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) { 1470 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) { 1471 LocVT = MVT::v2i64; 1472 if (ArgFlags.isSExt()) 1473 LocInfo = CCValAssign::SExt; 1474 else if (ArgFlags.isZExt()) 1475 LocInfo = CCValAssign::ZExt; 1476 else 1477 LocInfo = CCValAssign::AExt; 1478 } 1479 } 1480 } 1481 1482 if (LocVT == MVT::v2i1) { 1483 LocVT = MVT::v2i64; 1484 if (ArgFlags.isSExt()) 1485 LocInfo = CCValAssign::SExt; 1486 else if (ArgFlags.isZExt()) 1487 LocInfo = CCValAssign::ZExt; 1488 else 1489 LocInfo = CCValAssign::AExt; 1490 } 1491 1492 if (LocVT == MVT::v4i1) { 1493 LocVT = MVT::v4i32; 1494 if (ArgFlags.isSExt()) 1495 LocInfo = CCValAssign::SExt; 1496 else if (ArgFlags.isZExt()) 1497 LocInfo = CCValAssign::ZExt; 1498 else 1499 LocInfo = CCValAssign::AExt; 1500 } 1501 1502 if (LocVT == MVT::v8i1) { 1503 LocVT = MVT::v8i16; 1504 if (ArgFlags.isSExt()) 1505 LocInfo = CCValAssign::SExt; 1506 else if (ArgFlags.isZExt()) 1507 LocInfo = CCValAssign::ZExt; 1508 else 1509 LocInfo = CCValAssign::AExt; 1510 } 1511 1512 if (LocVT == MVT::v16i1) { 1513 LocVT = MVT::v16i8; 1514 if (ArgFlags.isSExt()) 1515 LocInfo = CCValAssign::SExt; 1516 else if (ArgFlags.isZExt()) 1517 LocInfo = CCValAssign::ZExt; 1518 else 1519 LocInfo = CCValAssign::AExt; 1520 } 1521 1522 if (LocVT == MVT::v32i1) { 1523 LocVT = MVT::v32i8; 1524 if (ArgFlags.isSExt()) 1525 LocInfo = CCValAssign::SExt; 1526 else if (ArgFlags.isZExt()) 1527 LocInfo = CCValAssign::ZExt; 1528 else 1529 LocInfo = CCValAssign::AExt; 1530 } 1531 1532 if (LocVT == MVT::v64i1) { 1533 LocVT = MVT::v64i8; 1534 if (ArgFlags.isSExt()) 1535 LocInfo = CCValAssign::SExt; 1536 else if (ArgFlags.isZExt()) 1537 LocInfo = CCValAssign::ZExt; 1538 else 1539 LocInfo = CCValAssign::AExt; 1540 } 1541 1542 if (LocVT == MVT::f32 || 1543 LocVT == MVT::f64 || 1544 LocVT == MVT::f128 || 1545 LocVT == MVT::v16i8 || 1546 LocVT == MVT::v8i16 || 1547 LocVT == MVT::v4i32 || 1548 LocVT == MVT::v2i64 || 1549 LocVT == MVT::v4f32 || 1550 LocVT == MVT::v2f64) { 1551 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 1552 static const MCPhysReg RegList3[] = { 1553 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1554 }; 1555 if (unsigned Reg = State.AllocateReg(RegList3)) { 1556 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1557 return false; 1558 } 1559 } 1560 } 1561 1562 if (!State.isVarArg()) { 1563 if (LocVT == MVT::v32i8 || 1564 LocVT == MVT::v16i16 || 1565 LocVT == MVT::v8i32 || 1566 LocVT == MVT::v4i64 || 1567 LocVT == MVT::v8f32 || 1568 LocVT == MVT::v4f64) { 1569 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { 1570 static const MCPhysReg RegList4[] = { 1571 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7 1572 }; 1573 if (unsigned Reg = State.AllocateReg(RegList4)) { 1574 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1575 return false; 1576 } 1577 } 1578 } 1579 } 1580 1581 if (!State.isVarArg()) { 1582 if (LocVT == MVT::v64i8 || 1583 LocVT == MVT::v32i16 || 1584 LocVT == MVT::v16i32 || 1585 LocVT == MVT::v8i64 || 1586 LocVT == MVT::v16f32 || 1587 LocVT == MVT::v8f64) { 1588 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { 1589 static const MCPhysReg RegList5[] = { 1590 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 1591 }; 1592 if (unsigned Reg = State.AllocateReg(RegList5)) { 1593 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1594 return false; 1595 } 1596 } 1597 } 1598 } 1599 1600 if (LocVT == MVT::i32 || 1601 LocVT == MVT::i64 || 1602 LocVT == MVT::f32 || 1603 LocVT == MVT::f64) { 1604 unsigned Offset6 = State.AllocateStack(8, 8); 1605 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo)); 1606 return false; 1607 } 1608 1609 if (LocVT == MVT::f80 || 1610 LocVT == MVT::f128) { 1611 unsigned Offset7 = State.AllocateStack( 1612 State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 1613 State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext()))); 1614 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo)); 1615 return false; 1616 } 1617 1618 if (LocVT == MVT::v16i8 || 1619 LocVT == MVT::v8i16 || 1620 LocVT == MVT::v4i32 || 1621 LocVT == MVT::v2i64 || 1622 LocVT == MVT::v4f32 || 1623 LocVT == MVT::v2f64) { 1624 unsigned Offset8 = State.AllocateStack(16, 16); 1625 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo)); 1626 return false; 1627 } 1628 1629 if (LocVT == MVT::v32i8 || 1630 LocVT == MVT::v16i16 || 1631 LocVT == MVT::v8i32 || 1632 LocVT == MVT::v4i64 || 1633 LocVT == MVT::v8f32 || 1634 LocVT == MVT::v4f64) { 1635 unsigned Offset9 = State.AllocateStack(32, 32); 1636 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo)); 1637 return false; 1638 } 1639 1640 if (LocVT == MVT::v16i32 || 1641 LocVT == MVT::v8i64 || 1642 LocVT == MVT::v16f32 || 1643 LocVT == MVT::v8f64) { 1644 unsigned Offset10 = State.AllocateStack(64, 64); 1645 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo)); 1646 return false; 1647 } 1648 1649 return true; // CC didn't match. 1650} 1651 1652 1653static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT, 1654 MVT LocVT, CCValAssign::LocInfo LocInfo, 1655 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1656 1657 if (LocVT == MVT::i8 || 1658 LocVT == MVT::i16 || 1659 LocVT == MVT::i32) { 1660 LocVT = MVT::i64; 1661 if (ArgFlags.isSExt()) 1662 LocInfo = CCValAssign::SExt; 1663 else if (ArgFlags.isZExt()) 1664 LocInfo = CCValAssign::ZExt; 1665 else 1666 LocInfo = CCValAssign::AExt; 1667 } 1668 1669 if (LocVT == MVT::i64) { 1670 static const MCPhysReg RegList1[] = { 1671 X86::R13, X86::RBP, X86::R12, X86::RBX, X86::R14, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R15 1672 }; 1673 if (unsigned Reg = State.AllocateReg(RegList1)) { 1674 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1675 return false; 1676 } 1677 } 1678 1679 if (LocVT == MVT::f32 || 1680 LocVT == MVT::f64 || 1681 LocVT == MVT::v16i8 || 1682 LocVT == MVT::v8i16 || 1683 LocVT == MVT::v4i32 || 1684 LocVT == MVT::v2i64 || 1685 LocVT == MVT::v4f32 || 1686 LocVT == MVT::v2f64) { 1687 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 1688 static const MCPhysReg RegList2[] = { 1689 X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6 1690 }; 1691 if (unsigned Reg = State.AllocateReg(RegList2)) { 1692 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1693 return false; 1694 } 1695 } 1696 } 1697 1698 if (LocVT == MVT::v32i8 || 1699 LocVT == MVT::v16i16 || 1700 LocVT == MVT::v8i32 || 1701 LocVT == MVT::v4i64 || 1702 LocVT == MVT::v8f32 || 1703 LocVT == MVT::v4f64) { 1704 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { 1705 static const MCPhysReg RegList3[] = { 1706 X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6 1707 }; 1708 if (unsigned Reg = State.AllocateReg(RegList3)) { 1709 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1710 return false; 1711 } 1712 } 1713 } 1714 1715 if (LocVT == MVT::v64i8 || 1716 LocVT == MVT::v32i16 || 1717 LocVT == MVT::v16i32 || 1718 LocVT == MVT::v8i64 || 1719 LocVT == MVT::v16f32 || 1720 LocVT == MVT::v8f64) { 1721 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { 1722 static const MCPhysReg RegList4[] = { 1723 X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6 1724 }; 1725 if (unsigned Reg = State.AllocateReg(RegList4)) { 1726 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1727 return false; 1728 } 1729 } 1730 } 1731 1732 return true; // CC didn't match. 1733} 1734 1735 1736static bool CC_X86_64_HHVM(unsigned ValNo, MVT ValVT, 1737 MVT LocVT, CCValAssign::LocInfo LocInfo, 1738 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1739 1740 if (LocVT == MVT::i64) { 1741 static const MCPhysReg RegList1[] = { 1742 X86::RBX, X86::R12, X86::RBP, X86::R15, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14 1743 }; 1744 if (unsigned Reg = State.AllocateReg(RegList1)) { 1745 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1746 return false; 1747 } 1748 } 1749 1750 return true; // CC didn't match. 1751} 1752 1753 1754static bool CC_X86_64_HHVM_C(unsigned ValNo, MVT ValVT, 1755 MVT LocVT, CCValAssign::LocInfo LocInfo, 1756 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1757 1758 if (LocVT == MVT::i64) { 1759 if (unsigned Reg = State.AllocateReg(X86::RBP)) { 1760 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1761 return false; 1762 } 1763 } 1764 1765 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1766 return false; 1767 1768 return true; // CC didn't match. 1769} 1770 1771 1772static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT, 1773 MVT LocVT, CCValAssign::LocInfo LocInfo, 1774 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1775 1776 if (LocVT == MVT::i8 || 1777 LocVT == MVT::i16 || 1778 LocVT == MVT::i32) { 1779 LocVT = MVT::i64; 1780 if (ArgFlags.isSExt()) 1781 LocInfo = CCValAssign::SExt; 1782 else if (ArgFlags.isZExt()) 1783 LocInfo = CCValAssign::ZExt; 1784 else 1785 LocInfo = CCValAssign::AExt; 1786 } 1787 1788 if (LocVT == MVT::i64) { 1789 static const MCPhysReg RegList1[] = { 1790 X86::R15, X86::RBP, X86::RSI, X86::RDX, X86::RCX, X86::R8 1791 }; 1792 if (unsigned Reg = State.AllocateReg(RegList1)) { 1793 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1794 return false; 1795 } 1796 } 1797 1798 if (LocVT == MVT::i32 || 1799 LocVT == MVT::i64 || 1800 LocVT == MVT::f32 || 1801 LocVT == MVT::f64) { 1802 unsigned Offset2 = State.AllocateStack(8, 8); 1803 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); 1804 return false; 1805 } 1806 1807 return true; // CC didn't match. 1808} 1809 1810 1811static bool CC_X86_64_Intr(unsigned ValNo, MVT ValVT, 1812 MVT LocVT, CCValAssign::LocInfo LocInfo, 1813 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1814 1815 unsigned Offset1 = State.AllocateStack(8, 8); 1816 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); 1817 return false; 1818 1819 return true; // CC didn't match. 1820} 1821 1822 1823static bool CC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT, 1824 MVT LocVT, CCValAssign::LocInfo LocInfo, 1825 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1826 1827 if (LocVT == MVT::i8 || 1828 LocVT == MVT::i16) { 1829 LocVT = MVT::i32; 1830 if (ArgFlags.isSExt()) 1831 LocInfo = CCValAssign::SExt; 1832 else if (ArgFlags.isZExt()) 1833 LocInfo = CCValAssign::ZExt; 1834 else 1835 LocInfo = CCValAssign::AExt; 1836 } 1837 1838 if (LocVT == MVT::i32) { 1839 if (unsigned Reg = State.AllocateReg(X86::EAX)) { 1840 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1841 return false; 1842 } 1843 } 1844 1845 if (LocVT == MVT::i64) { 1846 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 1847 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1848 return false; 1849 } 1850 } 1851 1852 if (LocVT == MVT::i32 || 1853 LocVT == MVT::f32) { 1854 unsigned Offset1 = State.AllocateStack(4, 4); 1855 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); 1856 return false; 1857 } 1858 1859 if (LocVT == MVT::i64 || 1860 LocVT == MVT::f64) { 1861 unsigned Offset2 = State.AllocateStack(8, 8); 1862 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); 1863 return false; 1864 } 1865 1866 return true; // CC didn't match. 1867} 1868 1869 1870static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT, 1871 MVT LocVT, CCValAssign::LocInfo LocInfo, 1872 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1873 1874 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 1875 if (ArgFlags.isByVal()) { 1876 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags); 1877 return false; 1878 } 1879 } 1880 1881 if (ArgFlags.isByVal()) { 1882 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags); 1883 return false; 1884 } 1885 1886 if (LocVT == MVT::i1 || 1887 LocVT == MVT::i8 || 1888 LocVT == MVT::i16 || 1889 LocVT == MVT::v1i1) { 1890 LocVT = MVT::i32; 1891 if (ArgFlags.isSExt()) 1892 LocInfo = CCValAssign::SExt; 1893 else if (ArgFlags.isZExt()) 1894 LocInfo = CCValAssign::ZExt; 1895 else 1896 LocInfo = CCValAssign::AExt; 1897 } 1898 1899 if (LocVT == MVT::v8i1 || 1900 LocVT == MVT::v16i1 || 1901 LocVT == MVT::v32i1) { 1902 LocVT = MVT::i32; 1903 if (ArgFlags.isSExt()) 1904 LocInfo = CCValAssign::SExt; 1905 else if (ArgFlags.isZExt()) 1906 LocInfo = CCValAssign::ZExt; 1907 else 1908 LocInfo = CCValAssign::AExt; 1909 } 1910 1911 if (LocVT == MVT::i32) { 1912 static const MCPhysReg RegList1[] = { 1913 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D 1914 }; 1915 if (unsigned Reg = State.AllocateReg(RegList1)) { 1916 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1917 return false; 1918 } 1919 } 1920 1921 if (LocVT == MVT::i64) { 1922 static const MCPhysReg RegList2[] = { 1923 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15 1924 }; 1925 if (unsigned Reg = State.AllocateReg(RegList2)) { 1926 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1927 return false; 1928 } 1929 } 1930 1931 if (LocVT == MVT::v64i1) { 1932 LocVT = MVT::i64; 1933 if (ArgFlags.isSExt()) 1934 LocInfo = CCValAssign::SExt; 1935 else if (ArgFlags.isZExt()) 1936 LocInfo = CCValAssign::ZExt; 1937 else 1938 LocInfo = CCValAssign::AExt; 1939 } 1940 1941 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 1942 if (LocVT == MVT::i64) { 1943 static const MCPhysReg RegList3[] = { 1944 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15 1945 }; 1946 if (unsigned Reg = State.AllocateReg(RegList3)) { 1947 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1948 return false; 1949 } 1950 } 1951 } 1952 1953 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { 1954 if (LocVT == MVT::i64) { 1955 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1956 return false; 1957 } 1958 } 1959 1960 if (LocVT == MVT::f32 || 1961 LocVT == MVT::f64 || 1962 LocVT == MVT::f128) { 1963 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 1964 static const MCPhysReg RegList4[] = { 1965 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 1966 }; 1967 if (unsigned Reg = State.AllocateReg(RegList4)) { 1968 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1969 return false; 1970 } 1971 } 1972 } 1973 1974 if (LocVT == MVT::f80) { 1975 if (unsigned Reg = State.AllocateReg(X86::FP0)) { 1976 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1977 return false; 1978 } 1979 } 1980 1981 if (LocVT == MVT::v16i8 || 1982 LocVT == MVT::v8i16 || 1983 LocVT == MVT::v4i32 || 1984 LocVT == MVT::v2i64 || 1985 LocVT == MVT::v4f32 || 1986 LocVT == MVT::v2f64) { 1987 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 1988 static const MCPhysReg RegList5[] = { 1989 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 1990 }; 1991 if (unsigned Reg = State.AllocateReg(RegList5)) { 1992 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1993 return false; 1994 } 1995 } 1996 } 1997 1998 if (LocVT == MVT::v32i8 || 1999 LocVT == MVT::v16i16 || 2000 LocVT == MVT::v8i32 || 2001 LocVT == MVT::v4i64 || 2002 LocVT == MVT::v8f32 || 2003 LocVT == MVT::v4f64) { 2004 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { 2005 static const MCPhysReg RegList6[] = { 2006 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15 2007 }; 2008 if (unsigned Reg = State.AllocateReg(RegList6)) { 2009 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2010 return false; 2011 } 2012 } 2013 } 2014 2015 if (LocVT == MVT::v64i8 || 2016 LocVT == MVT::v32i16 || 2017 LocVT == MVT::v16i32 || 2018 LocVT == MVT::v8i64 || 2019 LocVT == MVT::v16f32 || 2020 LocVT == MVT::v8f64) { 2021 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { 2022 static const MCPhysReg RegList7[] = { 2023 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15 2024 }; 2025 if (unsigned Reg = State.AllocateReg(RegList7)) { 2026 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2027 return false; 2028 } 2029 } 2030 } 2031 2032 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 2033 if (LocVT == MVT::i32 || 2034 LocVT == MVT::i64 || 2035 LocVT == MVT::f32 || 2036 LocVT == MVT::f64) { 2037 unsigned Offset8 = State.AllocateStack(8, 8); 2038 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo)); 2039 return false; 2040 } 2041 } 2042 2043 if (LocVT == MVT::i32 || 2044 LocVT == MVT::f32) { 2045 unsigned Offset9 = State.AllocateStack(4, 4); 2046 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo)); 2047 return false; 2048 } 2049 2050 if (LocVT == MVT::i64 || 2051 LocVT == MVT::f64) { 2052 unsigned Offset10 = State.AllocateStack(8, 4); 2053 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo)); 2054 return false; 2055 } 2056 2057 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 2058 if (LocVT == MVT::x86mmx) { 2059 unsigned Offset11 = State.AllocateStack(8, 8); 2060 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo)); 2061 return false; 2062 } 2063 } 2064 2065 if (LocVT == MVT::x86mmx) { 2066 unsigned Offset12 = State.AllocateStack(8, 4); 2067 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo)); 2068 return false; 2069 } 2070 2071 if (LocVT == MVT::f80 || 2072 LocVT == MVT::f128) { 2073 unsigned Offset13 = State.AllocateStack( 2074 State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 2075 State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext()))); 2076 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo)); 2077 return false; 2078 } 2079 2080 if (LocVT == MVT::v16i8 || 2081 LocVT == MVT::v8i16 || 2082 LocVT == MVT::v4i32 || 2083 LocVT == MVT::v2i64 || 2084 LocVT == MVT::v4f32 || 2085 LocVT == MVT::v2f64) { 2086 unsigned Offset14 = State.AllocateStack(16, 16); 2087 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo)); 2088 return false; 2089 } 2090 2091 if (LocVT == MVT::v32i8 || 2092 LocVT == MVT::v16i16 || 2093 LocVT == MVT::v8i32 || 2094 LocVT == MVT::v4i64 || 2095 LocVT == MVT::v8f32 || 2096 LocVT == MVT::v4f64) { 2097 unsigned Offset15 = State.AllocateStack(32, 32); 2098 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo)); 2099 return false; 2100 } 2101 2102 if (LocVT == MVT::v16i32 || 2103 LocVT == MVT::v8i64 || 2104 LocVT == MVT::v16f32 || 2105 LocVT == MVT::v8f64) { 2106 unsigned Offset16 = State.AllocateStack(64, 64); 2107 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo)); 2108 return false; 2109 } 2110 2111 return true; // CC didn't match. 2112} 2113 2114 2115static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT, 2116 MVT LocVT, CCValAssign::LocInfo LocInfo, 2117 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2118 2119 if (CC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2120 return false; 2121 2122 if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2123 return false; 2124 2125 return true; // CC didn't match. 2126} 2127 2128 2129static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT, 2130 MVT LocVT, CCValAssign::LocInfo LocInfo, 2131 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2132 2133 if (LocVT == MVT::i1 || 2134 LocVT == MVT::v1i1) { 2135 LocVT = MVT::i8; 2136 if (ArgFlags.isSExt()) 2137 LocInfo = CCValAssign::SExt; 2138 else if (ArgFlags.isZExt()) 2139 LocInfo = CCValAssign::ZExt; 2140 else 2141 LocInfo = CCValAssign::AExt; 2142 } 2143 2144 if (ArgFlags.isNest()) { 2145 if (unsigned Reg = State.AllocateReg(X86::R10)) { 2146 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2147 return false; 2148 } 2149 } 2150 2151 if (ArgFlags.isSwiftError()) { 2152 if (LocVT == MVT::i64) { 2153 if (unsigned Reg = State.AllocateReg(X86::R12)) { 2154 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2155 return false; 2156 } 2157 } 2158 } 2159 2160 if (LocVT == MVT::v16i8 || 2161 LocVT == MVT::v8i16 || 2162 LocVT == MVT::v4i32 || 2163 LocVT == MVT::v2i64 || 2164 LocVT == MVT::v4f32 || 2165 LocVT == MVT::v2f64) { 2166 LocVT = MVT::i64; 2167 LocInfo = CCValAssign::Indirect; 2168 } 2169 2170 if (LocVT == MVT::v32i8 || 2171 LocVT == MVT::v16i16 || 2172 LocVT == MVT::v8i32 || 2173 LocVT == MVT::v4i64 || 2174 LocVT == MVT::v8f32 || 2175 LocVT == MVT::v4f64) { 2176 LocVT = MVT::i64; 2177 LocInfo = CCValAssign::Indirect; 2178 } 2179 2180 if (LocVT == MVT::v16i32 || 2181 LocVT == MVT::v16f32 || 2182 LocVT == MVT::v8f64 || 2183 LocVT == MVT::v8i64) { 2184 LocVT = MVT::i64; 2185 LocInfo = CCValAssign::Indirect; 2186 } 2187 2188 if (LocVT == MVT::f80) { 2189 LocVT = MVT::i64; 2190 LocInfo = CCValAssign::Indirect; 2191 } 2192 2193 if (LocVT == MVT::x86mmx) { 2194 LocVT = MVT::i64; 2195 LocInfo = CCValAssign::BCvt; 2196 } 2197 2198 if (LocVT == MVT::i8) { 2199 static const MCPhysReg RegList1[] = { 2200 X86::CL, X86::DL, X86::R8B, X86::R9B 2201 }; 2202 static const MCPhysReg RegList2[] = { 2203 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 2204 }; 2205 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) { 2206 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2207 return false; 2208 } 2209 } 2210 2211 if (LocVT == MVT::i16) { 2212 static const MCPhysReg RegList3[] = { 2213 X86::CX, X86::DX, X86::R8W, X86::R9W 2214 }; 2215 static const MCPhysReg RegList4[] = { 2216 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 2217 }; 2218 if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) { 2219 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2220 return false; 2221 } 2222 } 2223 2224 if (LocVT == MVT::i32) { 2225 static const MCPhysReg RegList5[] = { 2226 X86::ECX, X86::EDX, X86::R8D, X86::R9D 2227 }; 2228 static const MCPhysReg RegList6[] = { 2229 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 2230 }; 2231 if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) { 2232 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2233 return false; 2234 } 2235 } 2236 2237 if (State.getCallingConv() == CallingConv::X86_ThisCall) { 2238 if (ArgFlags.isSRet()) { 2239 if (LocVT == MVT::i64) { 2240 static const MCPhysReg RegList7[] = { 2241 X86::RDX, X86::R8, X86::R9 2242 }; 2243 static const MCPhysReg RegList8[] = { 2244 X86::XMM1, X86::XMM2, X86::XMM3 2245 }; 2246 if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) { 2247 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2248 return false; 2249 } 2250 } 2251 } 2252 } 2253 2254 if (LocVT == MVT::i64) { 2255 static const MCPhysReg RegList9[] = { 2256 X86::RCX, X86::RDX, X86::R8, X86::R9 2257 }; 2258 static const MCPhysReg RegList10[] = { 2259 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 2260 }; 2261 if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) { 2262 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2263 return false; 2264 } 2265 } 2266 2267 if (LocVT == MVT::f32 || 2268 LocVT == MVT::f64 || 2269 LocVT == MVT::v16i8 || 2270 LocVT == MVT::v8i16 || 2271 LocVT == MVT::v4i32 || 2272 LocVT == MVT::v2i64 || 2273 LocVT == MVT::v4f32 || 2274 LocVT == MVT::v2f64) { 2275 static const MCPhysReg RegList11[] = { 2276 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 2277 }; 2278 static const MCPhysReg RegList12[] = { 2279 X86::RCX, X86::RDX, X86::R8, X86::R9 2280 }; 2281 if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) { 2282 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2283 return false; 2284 } 2285 } 2286 2287 if (LocVT == MVT::i8 || 2288 LocVT == MVT::i16 || 2289 LocVT == MVT::i32 || 2290 LocVT == MVT::i64 || 2291 LocVT == MVT::f32 || 2292 LocVT == MVT::f64) { 2293 unsigned Offset13 = State.AllocateStack(8, 8); 2294 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo)); 2295 return false; 2296 } 2297 2298 return true; // CC didn't match. 2299} 2300 2301 2302static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT, 2303 MVT LocVT, CCValAssign::LocInfo LocInfo, 2304 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2305 2306 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 2307 if (ArgFlags.isByVal()) { 2308 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags); 2309 return false; 2310 } 2311 } 2312 2313 if (ArgFlags.isByVal()) { 2314 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags); 2315 return false; 2316 } 2317 2318 if (LocVT == MVT::i1 || 2319 LocVT == MVT::i8 || 2320 LocVT == MVT::i16 || 2321 LocVT == MVT::v1i1) { 2322 LocVT = MVT::i32; 2323 if (ArgFlags.isSExt()) 2324 LocInfo = CCValAssign::SExt; 2325 else if (ArgFlags.isZExt()) 2326 LocInfo = CCValAssign::ZExt; 2327 else 2328 LocInfo = CCValAssign::AExt; 2329 } 2330 2331 if (LocVT == MVT::v8i1 || 2332 LocVT == MVT::v16i1 || 2333 LocVT == MVT::v32i1) { 2334 LocVT = MVT::i32; 2335 if (ArgFlags.isSExt()) 2336 LocInfo = CCValAssign::SExt; 2337 else if (ArgFlags.isZExt()) 2338 LocInfo = CCValAssign::ZExt; 2339 else 2340 LocInfo = CCValAssign::AExt; 2341 } 2342 2343 if (LocVT == MVT::i32) { 2344 static const MCPhysReg RegList1[] = { 2345 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D 2346 }; 2347 if (unsigned Reg = State.AllocateReg(RegList1)) { 2348 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2349 return false; 2350 } 2351 } 2352 2353 if (LocVT == MVT::i64) { 2354 static const MCPhysReg RegList2[] = { 2355 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15 2356 }; 2357 if (unsigned Reg = State.AllocateReg(RegList2)) { 2358 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2359 return false; 2360 } 2361 } 2362 2363 if (LocVT == MVT::v64i1) { 2364 LocVT = MVT::i64; 2365 if (ArgFlags.isSExt()) 2366 LocInfo = CCValAssign::SExt; 2367 else if (ArgFlags.isZExt()) 2368 LocInfo = CCValAssign::ZExt; 2369 else 2370 LocInfo = CCValAssign::AExt; 2371 } 2372 2373 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 2374 if (LocVT == MVT::i64) { 2375 static const MCPhysReg RegList3[] = { 2376 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15 2377 }; 2378 if (unsigned Reg = State.AllocateReg(RegList3)) { 2379 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2380 return false; 2381 } 2382 } 2383 } 2384 2385 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { 2386 if (LocVT == MVT::i64) { 2387 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2388 return false; 2389 } 2390 } 2391 2392 if (LocVT == MVT::f32 || 2393 LocVT == MVT::f64 || 2394 LocVT == MVT::f128) { 2395 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 2396 static const MCPhysReg RegList4[] = { 2397 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 2398 }; 2399 if (unsigned Reg = State.AllocateReg(RegList4)) { 2400 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2401 return false; 2402 } 2403 } 2404 } 2405 2406 if (LocVT == MVT::f80) { 2407 if (unsigned Reg = State.AllocateReg(X86::FP0)) { 2408 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2409 return false; 2410 } 2411 } 2412 2413 if (LocVT == MVT::v16i8 || 2414 LocVT == MVT::v8i16 || 2415 LocVT == MVT::v4i32 || 2416 LocVT == MVT::v2i64 || 2417 LocVT == MVT::v4f32 || 2418 LocVT == MVT::v2f64) { 2419 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 2420 static const MCPhysReg RegList5[] = { 2421 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 2422 }; 2423 if (unsigned Reg = State.AllocateReg(RegList5)) { 2424 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2425 return false; 2426 } 2427 } 2428 } 2429 2430 if (LocVT == MVT::v32i8 || 2431 LocVT == MVT::v16i16 || 2432 LocVT == MVT::v8i32 || 2433 LocVT == MVT::v4i64 || 2434 LocVT == MVT::v8f32 || 2435 LocVT == MVT::v4f64) { 2436 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { 2437 static const MCPhysReg RegList6[] = { 2438 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15 2439 }; 2440 if (unsigned Reg = State.AllocateReg(RegList6)) { 2441 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2442 return false; 2443 } 2444 } 2445 } 2446 2447 if (LocVT == MVT::v64i8 || 2448 LocVT == MVT::v32i16 || 2449 LocVT == MVT::v16i32 || 2450 LocVT == MVT::v8i64 || 2451 LocVT == MVT::v16f32 || 2452 LocVT == MVT::v8f64) { 2453 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { 2454 static const MCPhysReg RegList7[] = { 2455 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15 2456 }; 2457 if (unsigned Reg = State.AllocateReg(RegList7)) { 2458 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2459 return false; 2460 } 2461 } 2462 } 2463 2464 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 2465 if (LocVT == MVT::i32 || 2466 LocVT == MVT::i64 || 2467 LocVT == MVT::f32 || 2468 LocVT == MVT::f64) { 2469 unsigned Offset8 = State.AllocateStack(8, 8); 2470 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo)); 2471 return false; 2472 } 2473 } 2474 2475 if (LocVT == MVT::i32 || 2476 LocVT == MVT::f32) { 2477 unsigned Offset9 = State.AllocateStack(4, 4); 2478 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo)); 2479 return false; 2480 } 2481 2482 if (LocVT == MVT::i64 || 2483 LocVT == MVT::f64) { 2484 unsigned Offset10 = State.AllocateStack(8, 4); 2485 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo)); 2486 return false; 2487 } 2488 2489 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 2490 if (LocVT == MVT::x86mmx) { 2491 unsigned Offset11 = State.AllocateStack(8, 8); 2492 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo)); 2493 return false; 2494 } 2495 } 2496 2497 if (LocVT == MVT::x86mmx) { 2498 unsigned Offset12 = State.AllocateStack(8, 4); 2499 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo)); 2500 return false; 2501 } 2502 2503 if (LocVT == MVT::f80 || 2504 LocVT == MVT::f128) { 2505 unsigned Offset13 = State.AllocateStack( 2506 State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 2507 State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext()))); 2508 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo)); 2509 return false; 2510 } 2511 2512 if (LocVT == MVT::v16i8 || 2513 LocVT == MVT::v8i16 || 2514 LocVT == MVT::v4i32 || 2515 LocVT == MVT::v2i64 || 2516 LocVT == MVT::v4f32 || 2517 LocVT == MVT::v2f64) { 2518 unsigned Offset14 = State.AllocateStack(16, 16); 2519 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo)); 2520 return false; 2521 } 2522 2523 if (LocVT == MVT::v32i8 || 2524 LocVT == MVT::v16i16 || 2525 LocVT == MVT::v8i32 || 2526 LocVT == MVT::v4i64 || 2527 LocVT == MVT::v8f32 || 2528 LocVT == MVT::v4f64) { 2529 unsigned Offset15 = State.AllocateStack(32, 32); 2530 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo)); 2531 return false; 2532 } 2533 2534 if (LocVT == MVT::v16i32 || 2535 LocVT == MVT::v8i64 || 2536 LocVT == MVT::v16f32 || 2537 LocVT == MVT::v8f64) { 2538 unsigned Offset16 = State.AllocateStack(64, 64); 2539 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo)); 2540 return false; 2541 } 2542 2543 return true; // CC didn't match. 2544} 2545 2546 2547static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT, 2548 MVT LocVT, CCValAssign::LocInfo LocInfo, 2549 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2550 2551 if (CC_X86_64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2552 return false; 2553 2554 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2555 return false; 2556 2557 return true; // CC didn't match. 2558} 2559 2560 2561static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT, 2562 MVT LocVT, CCValAssign::LocInfo LocInfo, 2563 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2564 2565 if (LocVT == MVT::f32 || 2566 LocVT == MVT::f64 || 2567 LocVT == MVT::v4i32 || 2568 LocVT == MVT::v2i64 || 2569 LocVT == MVT::v4f32 || 2570 LocVT == MVT::v2f64) { 2571 static const MCPhysReg RegList1[] = { 2572 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 2573 }; 2574 if (unsigned Reg = State.AllocateReg(RegList1)) { 2575 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2576 return false; 2577 } 2578 } 2579 2580 if (LocVT == MVT::v8f32 || 2581 LocVT == MVT::v4f64 || 2582 LocVT == MVT::v8i32 || 2583 LocVT == MVT::v4i64) { 2584 static const MCPhysReg RegList2[] = { 2585 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3 2586 }; 2587 if (unsigned Reg = State.AllocateReg(RegList2)) { 2588 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2589 return false; 2590 } 2591 } 2592 2593 if (LocVT == MVT::v16f32 || 2594 LocVT == MVT::v8f64 || 2595 LocVT == MVT::v16i32 || 2596 LocVT == MVT::v8i64) { 2597 static const MCPhysReg RegList3[] = { 2598 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 2599 }; 2600 if (unsigned Reg = State.AllocateReg(RegList3)) { 2601 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2602 return false; 2603 } 2604 } 2605 2606 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2607 return false; 2608 2609 return true; // CC didn't match. 2610} 2611 2612 2613static bool RetCC_X86(unsigned ValNo, MVT ValVT, 2614 MVT LocVT, CCValAssign::LocInfo LocInfo, 2615 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2616 2617 if (State.getCallingConv() == CallingConv::Intel_OCL_BI) { 2618 if (!RetCC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2619 return false; 2620 } 2621 2622 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 2623 if (!RetCC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2624 return false; 2625 } 2626 2627 if (!RetCC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2628 return false; 2629 2630 return true; // CC didn't match. 2631} 2632 2633 2634static bool RetCC_X86Common(unsigned ValNo, MVT ValVT, 2635 MVT LocVT, CCValAssign::LocInfo LocInfo, 2636 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2637 2638 if (LocVT == MVT::v1i1) { 2639 LocVT = MVT::i8; 2640 if (ArgFlags.isSExt()) 2641 LocInfo = CCValAssign::SExt; 2642 else if (ArgFlags.isZExt()) 2643 LocInfo = CCValAssign::ZExt; 2644 else 2645 LocInfo = CCValAssign::AExt; 2646 } 2647 2648 if (LocVT == MVT::i1) { 2649 LocVT = MVT::i8; 2650 if (ArgFlags.isSExt()) 2651 LocInfo = CCValAssign::SExt; 2652 else if (ArgFlags.isZExt()) 2653 LocInfo = CCValAssign::ZExt; 2654 else 2655 LocInfo = CCValAssign::AExt; 2656 } 2657 2658 if (LocVT == MVT::i8) { 2659 static const MCPhysReg RegList1[] = { 2660 X86::AL, X86::DL, X86::CL 2661 }; 2662 if (unsigned Reg = State.AllocateReg(RegList1)) { 2663 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2664 return false; 2665 } 2666 } 2667 2668 if (LocVT == MVT::i16) { 2669 static const MCPhysReg RegList2[] = { 2670 X86::AX, X86::DX, X86::CX 2671 }; 2672 if (unsigned Reg = State.AllocateReg(RegList2)) { 2673 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2674 return false; 2675 } 2676 } 2677 2678 if (LocVT == MVT::i32) { 2679 static const MCPhysReg RegList3[] = { 2680 X86::EAX, X86::EDX, X86::ECX 2681 }; 2682 if (unsigned Reg = State.AllocateReg(RegList3)) { 2683 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2684 return false; 2685 } 2686 } 2687 2688 if (LocVT == MVT::i64) { 2689 static const MCPhysReg RegList4[] = { 2690 X86::RAX, X86::RDX, X86::RCX 2691 }; 2692 if (unsigned Reg = State.AllocateReg(RegList4)) { 2693 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2694 return false; 2695 } 2696 } 2697 2698 if (LocVT == MVT::v2i1) { 2699 LocVT = MVT::v2i64; 2700 if (ArgFlags.isSExt()) 2701 LocInfo = CCValAssign::SExt; 2702 else if (ArgFlags.isZExt()) 2703 LocInfo = CCValAssign::ZExt; 2704 else 2705 LocInfo = CCValAssign::AExt; 2706 } 2707 2708 if (LocVT == MVT::v4i1) { 2709 LocVT = MVT::v4i32; 2710 if (ArgFlags.isSExt()) 2711 LocInfo = CCValAssign::SExt; 2712 else if (ArgFlags.isZExt()) 2713 LocInfo = CCValAssign::ZExt; 2714 else 2715 LocInfo = CCValAssign::AExt; 2716 } 2717 2718 if (LocVT == MVT::v8i1) { 2719 LocVT = MVT::v8i16; 2720 if (ArgFlags.isSExt()) 2721 LocInfo = CCValAssign::SExt; 2722 else if (ArgFlags.isZExt()) 2723 LocInfo = CCValAssign::ZExt; 2724 else 2725 LocInfo = CCValAssign::AExt; 2726 } 2727 2728 if (LocVT == MVT::v16i1) { 2729 LocVT = MVT::v16i8; 2730 if (ArgFlags.isSExt()) 2731 LocInfo = CCValAssign::SExt; 2732 else if (ArgFlags.isZExt()) 2733 LocInfo = CCValAssign::ZExt; 2734 else 2735 LocInfo = CCValAssign::AExt; 2736 } 2737 2738 if (LocVT == MVT::v32i1) { 2739 LocVT = MVT::v32i8; 2740 if (ArgFlags.isSExt()) 2741 LocInfo = CCValAssign::SExt; 2742 else if (ArgFlags.isZExt()) 2743 LocInfo = CCValAssign::ZExt; 2744 else 2745 LocInfo = CCValAssign::AExt; 2746 } 2747 2748 if (LocVT == MVT::v64i1) { 2749 LocVT = MVT::v64i8; 2750 if (ArgFlags.isSExt()) 2751 LocInfo = CCValAssign::SExt; 2752 else if (ArgFlags.isZExt()) 2753 LocInfo = CCValAssign::ZExt; 2754 else 2755 LocInfo = CCValAssign::AExt; 2756 } 2757 2758 if (LocVT == MVT::v16i8 || 2759 LocVT == MVT::v8i16 || 2760 LocVT == MVT::v4i32 || 2761 LocVT == MVT::v2i64 || 2762 LocVT == MVT::v4f32 || 2763 LocVT == MVT::v2f64) { 2764 static const MCPhysReg RegList5[] = { 2765 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 2766 }; 2767 if (unsigned Reg = State.AllocateReg(RegList5)) { 2768 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2769 return false; 2770 } 2771 } 2772 2773 if (LocVT == MVT::v32i8 || 2774 LocVT == MVT::v16i16 || 2775 LocVT == MVT::v8i32 || 2776 LocVT == MVT::v4i64 || 2777 LocVT == MVT::v8f32 || 2778 LocVT == MVT::v4f64) { 2779 static const MCPhysReg RegList6[] = { 2780 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3 2781 }; 2782 if (unsigned Reg = State.AllocateReg(RegList6)) { 2783 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2784 return false; 2785 } 2786 } 2787 2788 if (LocVT == MVT::v64i8 || 2789 LocVT == MVT::v32i16 || 2790 LocVT == MVT::v16i32 || 2791 LocVT == MVT::v8i64 || 2792 LocVT == MVT::v16f32 || 2793 LocVT == MVT::v8f64) { 2794 static const MCPhysReg RegList7[] = { 2795 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 2796 }; 2797 if (unsigned Reg = State.AllocateReg(RegList7)) { 2798 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2799 return false; 2800 } 2801 } 2802 2803 if (LocVT == MVT::x86mmx) { 2804 if (unsigned Reg = State.AllocateReg(X86::MM0)) { 2805 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2806 return false; 2807 } 2808 } 2809 2810 if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { 2811 if (LocVT == MVT::f80) { 2812 static const MCPhysReg RegList8[] = { 2813 X86::FP0, X86::FP1 2814 }; 2815 if (unsigned Reg = State.AllocateReg(RegList8)) { 2816 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2817 return false; 2818 } 2819 } 2820 } 2821 2822 return true; // CC didn't match. 2823} 2824 2825 2826static bool RetCC_X86_32(unsigned ValNo, MVT ValVT, 2827 MVT LocVT, CCValAssign::LocInfo LocInfo, 2828 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2829 2830 if (State.getCallingConv() == CallingConv::Fast) { 2831 if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2832 return false; 2833 } 2834 2835 if (State.getCallingConv() == CallingConv::HiPE) { 2836 if (!RetCC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2837 return false; 2838 } 2839 2840 if (State.getCallingConv() == CallingConv::X86_VectorCall) { 2841 if (!RetCC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2842 return false; 2843 } 2844 2845 if (State.getCallingConv() == CallingConv::X86_RegCall) { 2846 if (!RetCC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2847 return false; 2848 } 2849 2850 if (!RetCC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2851 return false; 2852 2853 return true; // CC didn't match. 2854} 2855 2856 2857static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT, 2858 MVT LocVT, CCValAssign::LocInfo LocInfo, 2859 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2860 2861 if (ArgFlags.isInReg()) { 2862 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) { 2863 if (LocVT == MVT::f32 || 2864 LocVT == MVT::f64) { 2865 static const MCPhysReg RegList1[] = { 2866 X86::XMM0, X86::XMM1, X86::XMM2 2867 }; 2868 if (unsigned Reg = State.AllocateReg(RegList1)) { 2869 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2870 return false; 2871 } 2872 } 2873 } 2874 } 2875 2876 if (LocVT == MVT::f32 || 2877 LocVT == MVT::f64) { 2878 static const MCPhysReg RegList2[] = { 2879 X86::FP0, X86::FP1 2880 }; 2881 if (unsigned Reg = State.AllocateReg(RegList2)) { 2882 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2883 return false; 2884 } 2885 } 2886 2887 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2888 return false; 2889 2890 return true; // CC didn't match. 2891} 2892 2893 2894static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT, 2895 MVT LocVT, CCValAssign::LocInfo LocInfo, 2896 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2897 2898 if (LocVT == MVT::f32) { 2899 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) { 2900 static const MCPhysReg RegList1[] = { 2901 X86::XMM0, X86::XMM1, X86::XMM2 2902 }; 2903 if (unsigned Reg = State.AllocateReg(RegList1)) { 2904 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2905 return false; 2906 } 2907 } 2908 } 2909 2910 if (LocVT == MVT::f64) { 2911 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) { 2912 static const MCPhysReg RegList2[] = { 2913 X86::XMM0, X86::XMM1, X86::XMM2 2914 }; 2915 if (unsigned Reg = State.AllocateReg(RegList2)) { 2916 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2917 return false; 2918 } 2919 } 2920 } 2921 2922 if (LocVT == MVT::i8) { 2923 static const MCPhysReg RegList3[] = { 2924 X86::AL, X86::DL, X86::CL 2925 }; 2926 if (unsigned Reg = State.AllocateReg(RegList3)) { 2927 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2928 return false; 2929 } 2930 } 2931 2932 if (LocVT == MVT::i16) { 2933 static const MCPhysReg RegList4[] = { 2934 X86::AX, X86::DX, X86::CX 2935 }; 2936 if (unsigned Reg = State.AllocateReg(RegList4)) { 2937 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2938 return false; 2939 } 2940 } 2941 2942 if (LocVT == MVT::i32) { 2943 static const MCPhysReg RegList5[] = { 2944 X86::EAX, X86::EDX, X86::ECX 2945 }; 2946 if (unsigned Reg = State.AllocateReg(RegList5)) { 2947 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2948 return false; 2949 } 2950 } 2951 2952 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2953 return false; 2954 2955 return true; // CC didn't match. 2956} 2957 2958 2959static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT, 2960 MVT LocVT, CCValAssign::LocInfo LocInfo, 2961 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2962 2963 if (LocVT == MVT::i8 || 2964 LocVT == MVT::i16) { 2965 LocVT = MVT::i32; 2966 if (ArgFlags.isSExt()) 2967 LocInfo = CCValAssign::SExt; 2968 else if (ArgFlags.isZExt()) 2969 LocInfo = CCValAssign::ZExt; 2970 else 2971 LocInfo = CCValAssign::AExt; 2972 } 2973 2974 if (LocVT == MVT::i32) { 2975 static const MCPhysReg RegList1[] = { 2976 X86::ESI, X86::EBP, X86::EAX, X86::EDX 2977 }; 2978 if (unsigned Reg = State.AllocateReg(RegList1)) { 2979 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2980 return false; 2981 } 2982 } 2983 2984 return true; // CC didn't match. 2985} 2986 2987 2988static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT, 2989 MVT LocVT, CCValAssign::LocInfo LocInfo, 2990 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2991 2992 if (LocVT == MVT::i1 || 2993 LocVT == MVT::v1i1 || 2994 LocVT == MVT::v8i1) { 2995 LocVT = MVT::i8; 2996 if (ArgFlags.isSExt()) 2997 LocInfo = CCValAssign::SExt; 2998 else if (ArgFlags.isZExt()) 2999 LocInfo = CCValAssign::ZExt; 3000 else 3001 LocInfo = CCValAssign::AExt; 3002 } 3003 3004 if (LocVT == MVT::v16i1) { 3005 LocVT = MVT::i16; 3006 if (ArgFlags.isSExt()) 3007 LocInfo = CCValAssign::SExt; 3008 else if (ArgFlags.isZExt()) 3009 LocInfo = CCValAssign::ZExt; 3010 else 3011 LocInfo = CCValAssign::AExt; 3012 } 3013 3014 if (LocVT == MVT::v32i1) { 3015 LocVT = MVT::i32; 3016 if (ArgFlags.isSExt()) 3017 LocInfo = CCValAssign::SExt; 3018 else if (ArgFlags.isZExt()) 3019 LocInfo = CCValAssign::ZExt; 3020 else 3021 LocInfo = CCValAssign::AExt; 3022 } 3023 3024 if (LocVT == MVT::i8) { 3025 static const MCPhysReg RegList1[] = { 3026 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL 3027 }; 3028 if (unsigned Reg = State.AllocateReg(RegList1)) { 3029 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3030 return false; 3031 } 3032 } 3033 3034 if (LocVT == MVT::i16) { 3035 static const MCPhysReg RegList2[] = { 3036 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI 3037 }; 3038 if (unsigned Reg = State.AllocateReg(RegList2)) { 3039 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3040 return false; 3041 } 3042 } 3043 3044 if (LocVT == MVT::i32) { 3045 static const MCPhysReg RegList3[] = { 3046 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI 3047 }; 3048 if (unsigned Reg = State.AllocateReg(RegList3)) { 3049 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3050 return false; 3051 } 3052 } 3053 3054 if (LocVT == MVT::i64) { 3055 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 3056 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3057 return false; 3058 } 3059 } 3060 3061 if (LocVT == MVT::v64i1) { 3062 LocVT = MVT::i64; 3063 if (ArgFlags.isSExt()) 3064 LocInfo = CCValAssign::SExt; 3065 else if (ArgFlags.isZExt()) 3066 LocInfo = CCValAssign::ZExt; 3067 else 3068 LocInfo = CCValAssign::AExt; 3069 } 3070 3071 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 3072 if (LocVT == MVT::i64) { 3073 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 3074 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3075 return false; 3076 } 3077 } 3078 } 3079 3080 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { 3081 if (LocVT == MVT::i64) { 3082 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3083 return false; 3084 } 3085 } 3086 3087 if (LocVT == MVT::f80) { 3088 static const MCPhysReg RegList4[] = { 3089 X86::FP0, X86::FP1 3090 }; 3091 if (unsigned Reg = State.AllocateReg(RegList4)) { 3092 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3093 return false; 3094 } 3095 } 3096 3097 if (LocVT == MVT::f32 || 3098 LocVT == MVT::f64 || 3099 LocVT == MVT::f128) { 3100 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 3101 static const MCPhysReg RegList5[] = { 3102 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 3103 }; 3104 if (unsigned Reg = State.AllocateReg(RegList5)) { 3105 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3106 return false; 3107 } 3108 } 3109 } 3110 3111 if (LocVT == MVT::v16i8 || 3112 LocVT == MVT::v8i16 || 3113 LocVT == MVT::v4i32 || 3114 LocVT == MVT::v2i64 || 3115 LocVT == MVT::v4f32 || 3116 LocVT == MVT::v2f64) { 3117 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 3118 static const MCPhysReg RegList6[] = { 3119 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 3120 }; 3121 if (unsigned Reg = State.AllocateReg(RegList6)) { 3122 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3123 return false; 3124 } 3125 } 3126 } 3127 3128 if (LocVT == MVT::v32i8 || 3129 LocVT == MVT::v16i16 || 3130 LocVT == MVT::v8i32 || 3131 LocVT == MVT::v4i64 || 3132 LocVT == MVT::v8f32 || 3133 LocVT == MVT::v4f64) { 3134 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { 3135 static const MCPhysReg RegList7[] = { 3136 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7 3137 }; 3138 if (unsigned Reg = State.AllocateReg(RegList7)) { 3139 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3140 return false; 3141 } 3142 } 3143 } 3144 3145 if (LocVT == MVT::v64i8 || 3146 LocVT == MVT::v32i16 || 3147 LocVT == MVT::v16i32 || 3148 LocVT == MVT::v8i64 || 3149 LocVT == MVT::v16f32 || 3150 LocVT == MVT::v8f64) { 3151 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { 3152 static const MCPhysReg RegList8[] = { 3153 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 3154 }; 3155 if (unsigned Reg = State.AllocateReg(RegList8)) { 3156 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3157 return false; 3158 } 3159 } 3160 } 3161 3162 return true; // CC didn't match. 3163} 3164 3165 3166static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT, 3167 MVT LocVT, CCValAssign::LocInfo LocInfo, 3168 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3169 3170 if (LocVT == MVT::f32 || 3171 LocVT == MVT::f64 || 3172 LocVT == MVT::f128) { 3173 static const MCPhysReg RegList1[] = { 3174 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 3175 }; 3176 if (unsigned Reg = State.AllocateReg(RegList1)) { 3177 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3178 return false; 3179 } 3180 } 3181 3182 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3183 return false; 3184 3185 return true; // CC didn't match. 3186} 3187 3188 3189static bool RetCC_X86_64(unsigned ValNo, MVT ValVT, 3190 MVT LocVT, CCValAssign::LocInfo LocInfo, 3191 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3192 3193 if (State.getCallingConv() == CallingConv::HiPE) { 3194 if (!RetCC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3195 return false; 3196 } 3197 3198 if (State.getCallingConv() == CallingConv::WebKit_JS) { 3199 if (!RetCC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3200 return false; 3201 } 3202 3203 if (State.getCallingConv() == CallingConv::AnyReg) { 3204 if (!RetCC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3205 return false; 3206 } 3207 3208 if (State.getCallingConv() == CallingConv::Swift) { 3209 if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3210 return false; 3211 } 3212 3213 if (State.getCallingConv() == CallingConv::Win64) { 3214 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3215 return false; 3216 } 3217 3218 if (State.getCallingConv() == CallingConv::X86_64_SysV) { 3219 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3220 return false; 3221 } 3222 3223 if (State.getCallingConv() == CallingConv::X86_VectorCall) { 3224 if (!RetCC_X86_64_Vectorcall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3225 return false; 3226 } 3227 3228 if (State.getCallingConv() == CallingConv::HHVM) { 3229 if (!RetCC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3230 return false; 3231 } 3232 3233 if (State.getCallingConv() == CallingConv::X86_RegCall) { 3234 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { 3235 if (!RetCC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3236 return false; 3237 } 3238 } 3239 3240 if (State.getCallingConv() == CallingConv::X86_RegCall) { 3241 if (!RetCC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3242 return false; 3243 } 3244 3245 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { 3246 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3247 return false; 3248 } 3249 3250 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3251 return false; 3252 3253 return true; // CC didn't match. 3254} 3255 3256 3257static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT, 3258 MVT LocVT, CCValAssign::LocInfo LocInfo, 3259 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3260 3261 if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3262 return false; 3263 3264 return true; // CC didn't match. 3265} 3266 3267 3268static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT, 3269 MVT LocVT, CCValAssign::LocInfo LocInfo, 3270 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3271 3272 if (LocVT == MVT::f32) { 3273 static const MCPhysReg RegList1[] = { 3274 X86::XMM0, X86::XMM1 3275 }; 3276 if (unsigned Reg = State.AllocateReg(RegList1)) { 3277 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3278 return false; 3279 } 3280 } 3281 3282 if (LocVT == MVT::f64) { 3283 static const MCPhysReg RegList2[] = { 3284 X86::XMM0, X86::XMM1 3285 }; 3286 if (unsigned Reg = State.AllocateReg(RegList2)) { 3287 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3288 return false; 3289 } 3290 } 3291 3292 if (LocVT == MVT::f128) { 3293 static const MCPhysReg RegList3[] = { 3294 X86::XMM0, X86::XMM1 3295 }; 3296 if (unsigned Reg = State.AllocateReg(RegList3)) { 3297 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3298 return false; 3299 } 3300 } 3301 3302 if (LocVT == MVT::x86mmx) { 3303 static const MCPhysReg RegList4[] = { 3304 X86::XMM0, X86::XMM1 3305 }; 3306 if (unsigned Reg = State.AllocateReg(RegList4)) { 3307 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3308 return false; 3309 } 3310 } 3311 3312 if (ArgFlags.isSwiftError()) { 3313 if (LocVT == MVT::i64) { 3314 if (unsigned Reg = State.AllocateReg(X86::R12)) { 3315 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3316 return false; 3317 } 3318 } 3319 } 3320 3321 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3322 return false; 3323 3324 return true; // CC didn't match. 3325} 3326 3327 3328static bool RetCC_X86_64_HHVM(unsigned ValNo, MVT ValVT, 3329 MVT LocVT, CCValAssign::LocInfo LocInfo, 3330 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3331 3332 if (LocVT == MVT::i8 || 3333 LocVT == MVT::i16 || 3334 LocVT == MVT::i32) { 3335 LocVT = MVT::i64; 3336 if (ArgFlags.isSExt()) 3337 LocInfo = CCValAssign::SExt; 3338 else if (ArgFlags.isZExt()) 3339 LocInfo = CCValAssign::ZExt; 3340 else 3341 LocInfo = CCValAssign::AExt; 3342 } 3343 3344 if (LocVT == MVT::i64) { 3345 static const MCPhysReg RegList1[] = { 3346 X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14, X86::R15 3347 }; 3348 if (unsigned Reg = State.AllocateReg(RegList1)) { 3349 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3350 return false; 3351 } 3352 } 3353 3354 return true; // CC didn't match. 3355} 3356 3357 3358static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT, 3359 MVT LocVT, CCValAssign::LocInfo LocInfo, 3360 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3361 3362 if (LocVT == MVT::i8 || 3363 LocVT == MVT::i16 || 3364 LocVT == MVT::i32) { 3365 LocVT = MVT::i64; 3366 if (ArgFlags.isSExt()) 3367 LocInfo = CCValAssign::SExt; 3368 else if (ArgFlags.isZExt()) 3369 LocInfo = CCValAssign::ZExt; 3370 else 3371 LocInfo = CCValAssign::AExt; 3372 } 3373 3374 if (LocVT == MVT::i64) { 3375 static const MCPhysReg RegList1[] = { 3376 X86::R15, X86::RBP, X86::RAX, X86::RDX 3377 }; 3378 if (unsigned Reg = State.AllocateReg(RegList1)) { 3379 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3380 return false; 3381 } 3382 } 3383 3384 return true; // CC didn't match. 3385} 3386 3387 3388static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT, 3389 MVT LocVT, CCValAssign::LocInfo LocInfo, 3390 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3391 3392 if (ArgFlags.isSwiftError()) { 3393 if (LocVT == MVT::i64) { 3394 if (unsigned Reg = State.AllocateReg(X86::R12)) { 3395 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3396 return false; 3397 } 3398 } 3399 } 3400 3401 if (LocVT == MVT::v1i1) { 3402 LocVT = MVT::i8; 3403 if (ArgFlags.isSExt()) 3404 LocInfo = CCValAssign::SExt; 3405 else if (ArgFlags.isZExt()) 3406 LocInfo = CCValAssign::ZExt; 3407 else 3408 LocInfo = CCValAssign::AExt; 3409 } 3410 3411 if (LocVT == MVT::i1) { 3412 LocVT = MVT::i8; 3413 if (ArgFlags.isSExt()) 3414 LocInfo = CCValAssign::SExt; 3415 else if (ArgFlags.isZExt()) 3416 LocInfo = CCValAssign::ZExt; 3417 else 3418 LocInfo = CCValAssign::AExt; 3419 } 3420 3421 if (LocVT == MVT::i8) { 3422 static const MCPhysReg RegList1[] = { 3423 X86::AL, X86::DL, X86::CL, X86::R8B 3424 }; 3425 if (unsigned Reg = State.AllocateReg(RegList1)) { 3426 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3427 return false; 3428 } 3429 } 3430 3431 if (LocVT == MVT::i16) { 3432 static const MCPhysReg RegList2[] = { 3433 X86::AX, X86::DX, X86::CX, X86::R8W 3434 }; 3435 if (unsigned Reg = State.AllocateReg(RegList2)) { 3436 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3437 return false; 3438 } 3439 } 3440 3441 if (LocVT == MVT::i32) { 3442 static const MCPhysReg RegList3[] = { 3443 X86::EAX, X86::EDX, X86::ECX, X86::R8D 3444 }; 3445 if (unsigned Reg = State.AllocateReg(RegList3)) { 3446 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3447 return false; 3448 } 3449 } 3450 3451 if (LocVT == MVT::i64) { 3452 static const MCPhysReg RegList4[] = { 3453 X86::RAX, X86::RDX, X86::RCX, X86::R8 3454 }; 3455 if (unsigned Reg = State.AllocateReg(RegList4)) { 3456 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3457 return false; 3458 } 3459 } 3460 3461 if (LocVT == MVT::f32) { 3462 static const MCPhysReg RegList5[] = { 3463 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 3464 }; 3465 if (unsigned Reg = State.AllocateReg(RegList5)) { 3466 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3467 return false; 3468 } 3469 } 3470 3471 if (LocVT == MVT::f64) { 3472 static const MCPhysReg RegList6[] = { 3473 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 3474 }; 3475 if (unsigned Reg = State.AllocateReg(RegList6)) { 3476 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3477 return false; 3478 } 3479 } 3480 3481 if (LocVT == MVT::f128) { 3482 static const MCPhysReg RegList7[] = { 3483 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 3484 }; 3485 if (unsigned Reg = State.AllocateReg(RegList7)) { 3486 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3487 return false; 3488 } 3489 } 3490 3491 if (LocVT == MVT::x86mmx) { 3492 static const MCPhysReg RegList8[] = { 3493 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 3494 }; 3495 if (unsigned Reg = State.AllocateReg(RegList8)) { 3496 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3497 return false; 3498 } 3499 } 3500 3501 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3502 return false; 3503 3504 return true; // CC didn't match. 3505} 3506 3507 3508static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT, 3509 MVT LocVT, CCValAssign::LocInfo LocInfo, 3510 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3511 3512 if (LocVT == MVT::f32 || 3513 LocVT == MVT::f64 || 3514 LocVT == MVT::f128) { 3515 static const MCPhysReg RegList1[] = { 3516 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 3517 }; 3518 if (unsigned Reg = State.AllocateReg(RegList1)) { 3519 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3520 return false; 3521 } 3522 } 3523 3524 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3525 return false; 3526 3527 return true; // CC didn't match. 3528} 3529 3530 3531static bool RetCC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT, 3532 MVT LocVT, CCValAssign::LocInfo LocInfo, 3533 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3534 3535 if (LocVT == MVT::i8 || 3536 LocVT == MVT::i16 || 3537 LocVT == MVT::i32) { 3538 LocVT = MVT::i64; 3539 if (ArgFlags.isSExt()) 3540 LocInfo = CCValAssign::SExt; 3541 else if (ArgFlags.isZExt()) 3542 LocInfo = CCValAssign::ZExt; 3543 else 3544 LocInfo = CCValAssign::AExt; 3545 } 3546 3547 if (LocVT == MVT::i64) { 3548 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 3549 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3550 return false; 3551 } 3552 } 3553 3554 return true; // CC didn't match. 3555} 3556 3557 3558static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT, 3559 MVT LocVT, CCValAssign::LocInfo LocInfo, 3560 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3561 3562 if (LocVT == MVT::i1 || 3563 LocVT == MVT::v1i1 || 3564 LocVT == MVT::v8i1) { 3565 LocVT = MVT::i8; 3566 if (ArgFlags.isSExt()) 3567 LocInfo = CCValAssign::SExt; 3568 else if (ArgFlags.isZExt()) 3569 LocInfo = CCValAssign::ZExt; 3570 else 3571 LocInfo = CCValAssign::AExt; 3572 } 3573 3574 if (LocVT == MVT::v16i1) { 3575 LocVT = MVT::i16; 3576 if (ArgFlags.isSExt()) 3577 LocInfo = CCValAssign::SExt; 3578 else if (ArgFlags.isZExt()) 3579 LocInfo = CCValAssign::ZExt; 3580 else 3581 LocInfo = CCValAssign::AExt; 3582 } 3583 3584 if (LocVT == MVT::v32i1) { 3585 LocVT = MVT::i32; 3586 if (ArgFlags.isSExt()) 3587 LocInfo = CCValAssign::SExt; 3588 else if (ArgFlags.isZExt()) 3589 LocInfo = CCValAssign::ZExt; 3590 else 3591 LocInfo = CCValAssign::AExt; 3592 } 3593 3594 if (LocVT == MVT::i8) { 3595 static const MCPhysReg RegList1[] = { 3596 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R12B, X86::R13B, X86::R14B, X86::R15B 3597 }; 3598 if (unsigned Reg = State.AllocateReg(RegList1)) { 3599 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3600 return false; 3601 } 3602 } 3603 3604 if (LocVT == MVT::i16) { 3605 static const MCPhysReg RegList2[] = { 3606 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R12W, X86::R13W, X86::R14W, X86::R15W 3607 }; 3608 if (unsigned Reg = State.AllocateReg(RegList2)) { 3609 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3610 return false; 3611 } 3612 } 3613 3614 if (LocVT == MVT::i32) { 3615 static const MCPhysReg RegList3[] = { 3616 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D 3617 }; 3618 if (unsigned Reg = State.AllocateReg(RegList3)) { 3619 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3620 return false; 3621 } 3622 } 3623 3624 if (LocVT == MVT::i64) { 3625 static const MCPhysReg RegList4[] = { 3626 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15 3627 }; 3628 if (unsigned Reg = State.AllocateReg(RegList4)) { 3629 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3630 return false; 3631 } 3632 } 3633 3634 if (LocVT == MVT::v64i1) { 3635 LocVT = MVT::i64; 3636 if (ArgFlags.isSExt()) 3637 LocInfo = CCValAssign::SExt; 3638 else if (ArgFlags.isZExt()) 3639 LocInfo = CCValAssign::ZExt; 3640 else 3641 LocInfo = CCValAssign::AExt; 3642 } 3643 3644 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 3645 if (LocVT == MVT::i64) { 3646 static const MCPhysReg RegList5[] = { 3647 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15 3648 }; 3649 if (unsigned Reg = State.AllocateReg(RegList5)) { 3650 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3651 return false; 3652 } 3653 } 3654 } 3655 3656 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { 3657 if (LocVT == MVT::i64) { 3658 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3659 return false; 3660 } 3661 } 3662 3663 if (LocVT == MVT::f80) { 3664 static const MCPhysReg RegList6[] = { 3665 X86::FP0, X86::FP1 3666 }; 3667 if (unsigned Reg = State.AllocateReg(RegList6)) { 3668 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3669 return false; 3670 } 3671 } 3672 3673 if (LocVT == MVT::f32 || 3674 LocVT == MVT::f64 || 3675 LocVT == MVT::f128) { 3676 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 3677 static const MCPhysReg RegList7[] = { 3678 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 3679 }; 3680 if (unsigned Reg = State.AllocateReg(RegList7)) { 3681 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3682 return false; 3683 } 3684 } 3685 } 3686 3687 if (LocVT == MVT::v16i8 || 3688 LocVT == MVT::v8i16 || 3689 LocVT == MVT::v4i32 || 3690 LocVT == MVT::v2i64 || 3691 LocVT == MVT::v4f32 || 3692 LocVT == MVT::v2f64) { 3693 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 3694 static const MCPhysReg RegList8[] = { 3695 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 3696 }; 3697 if (unsigned Reg = State.AllocateReg(RegList8)) { 3698 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3699 return false; 3700 } 3701 } 3702 } 3703 3704 if (LocVT == MVT::v32i8 || 3705 LocVT == MVT::v16i16 || 3706 LocVT == MVT::v8i32 || 3707 LocVT == MVT::v4i64 || 3708 LocVT == MVT::v8f32 || 3709 LocVT == MVT::v4f64) { 3710 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { 3711 static const MCPhysReg RegList9[] = { 3712 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15 3713 }; 3714 if (unsigned Reg = State.AllocateReg(RegList9)) { 3715 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3716 return false; 3717 } 3718 } 3719 } 3720 3721 if (LocVT == MVT::v64i8 || 3722 LocVT == MVT::v32i16 || 3723 LocVT == MVT::v16i32 || 3724 LocVT == MVT::v8i64 || 3725 LocVT == MVT::v16f32 || 3726 LocVT == MVT::v8f64) { 3727 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { 3728 static const MCPhysReg RegList10[] = { 3729 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15 3730 }; 3731 if (unsigned Reg = State.AllocateReg(RegList10)) { 3732 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3733 return false; 3734 } 3735 } 3736 } 3737 3738 return true; // CC didn't match. 3739} 3740 3741 3742static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT, 3743 MVT LocVT, CCValAssign::LocInfo LocInfo, 3744 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3745 3746 if (LocVT == MVT::x86mmx) { 3747 LocVT = MVT::i64; 3748 LocInfo = CCValAssign::BCvt; 3749 } 3750 3751 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3752 return false; 3753 3754 return true; // CC didn't match. 3755} 3756 3757 3758static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT, 3759 MVT LocVT, CCValAssign::LocInfo LocInfo, 3760 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3761 3762 if (LocVT == MVT::i1 || 3763 LocVT == MVT::v1i1 || 3764 LocVT == MVT::v8i1) { 3765 LocVT = MVT::i8; 3766 if (ArgFlags.isSExt()) 3767 LocInfo = CCValAssign::SExt; 3768 else if (ArgFlags.isZExt()) 3769 LocInfo = CCValAssign::ZExt; 3770 else 3771 LocInfo = CCValAssign::AExt; 3772 } 3773 3774 if (LocVT == MVT::v16i1) { 3775 LocVT = MVT::i16; 3776 if (ArgFlags.isSExt()) 3777 LocInfo = CCValAssign::SExt; 3778 else if (ArgFlags.isZExt()) 3779 LocInfo = CCValAssign::ZExt; 3780 else 3781 LocInfo = CCValAssign::AExt; 3782 } 3783 3784 if (LocVT == MVT::v32i1) { 3785 LocVT = MVT::i32; 3786 if (ArgFlags.isSExt()) 3787 LocInfo = CCValAssign::SExt; 3788 else if (ArgFlags.isZExt()) 3789 LocInfo = CCValAssign::ZExt; 3790 else 3791 LocInfo = CCValAssign::AExt; 3792 } 3793 3794 if (LocVT == MVT::i8) { 3795 static const MCPhysReg RegList1[] = { 3796 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R12B, X86::R14B, X86::R15B 3797 }; 3798 if (unsigned Reg = State.AllocateReg(RegList1)) { 3799 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3800 return false; 3801 } 3802 } 3803 3804 if (LocVT == MVT::i16) { 3805 static const MCPhysReg RegList2[] = { 3806 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R12W, X86::R14W, X86::R15W 3807 }; 3808 if (unsigned Reg = State.AllocateReg(RegList2)) { 3809 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3810 return false; 3811 } 3812 } 3813 3814 if (LocVT == MVT::i32) { 3815 static const MCPhysReg RegList3[] = { 3816 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D 3817 }; 3818 if (unsigned Reg = State.AllocateReg(RegList3)) { 3819 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3820 return false; 3821 } 3822 } 3823 3824 if (LocVT == MVT::i64) { 3825 static const MCPhysReg RegList4[] = { 3826 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15 3827 }; 3828 if (unsigned Reg = State.AllocateReg(RegList4)) { 3829 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3830 return false; 3831 } 3832 } 3833 3834 if (LocVT == MVT::v64i1) { 3835 LocVT = MVT::i64; 3836 if (ArgFlags.isSExt()) 3837 LocInfo = CCValAssign::SExt; 3838 else if (ArgFlags.isZExt()) 3839 LocInfo = CCValAssign::ZExt; 3840 else 3841 LocInfo = CCValAssign::AExt; 3842 } 3843 3844 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 3845 if (LocVT == MVT::i64) { 3846 static const MCPhysReg RegList5[] = { 3847 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15 3848 }; 3849 if (unsigned Reg = State.AllocateReg(RegList5)) { 3850 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3851 return false; 3852 } 3853 } 3854 } 3855 3856 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { 3857 if (LocVT == MVT::i64) { 3858 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3859 return false; 3860 } 3861 } 3862 3863 if (LocVT == MVT::f80) { 3864 static const MCPhysReg RegList6[] = { 3865 X86::FP0, X86::FP1 3866 }; 3867 if (unsigned Reg = State.AllocateReg(RegList6)) { 3868 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3869 return false; 3870 } 3871 } 3872 3873 if (LocVT == MVT::f32 || 3874 LocVT == MVT::f64 || 3875 LocVT == MVT::f128) { 3876 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 3877 static const MCPhysReg RegList7[] = { 3878 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 3879 }; 3880 if (unsigned Reg = State.AllocateReg(RegList7)) { 3881 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3882 return false; 3883 } 3884 } 3885 } 3886 3887 if (LocVT == MVT::v16i8 || 3888 LocVT == MVT::v8i16 || 3889 LocVT == MVT::v4i32 || 3890 LocVT == MVT::v2i64 || 3891 LocVT == MVT::v4f32 || 3892 LocVT == MVT::v2f64) { 3893 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 3894 static const MCPhysReg RegList8[] = { 3895 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 3896 }; 3897 if (unsigned Reg = State.AllocateReg(RegList8)) { 3898 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3899 return false; 3900 } 3901 } 3902 } 3903 3904 if (LocVT == MVT::v32i8 || 3905 LocVT == MVT::v16i16 || 3906 LocVT == MVT::v8i32 || 3907 LocVT == MVT::v4i64 || 3908 LocVT == MVT::v8f32 || 3909 LocVT == MVT::v4f64) { 3910 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { 3911 static const MCPhysReg RegList9[] = { 3912 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15 3913 }; 3914 if (unsigned Reg = State.AllocateReg(RegList9)) { 3915 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3916 return false; 3917 } 3918 } 3919 } 3920 3921 if (LocVT == MVT::v64i8 || 3922 LocVT == MVT::v32i16 || 3923 LocVT == MVT::v16i32 || 3924 LocVT == MVT::v8i64 || 3925 LocVT == MVT::v16f32 || 3926 LocVT == MVT::v8f64) { 3927 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { 3928 static const MCPhysReg RegList10[] = { 3929 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15 3930 }; 3931 if (unsigned Reg = State.AllocateReg(RegList10)) { 3932 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3933 return false; 3934 } 3935 } 3936 } 3937 3938 return true; // CC didn't match. 3939} 3940