| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenCallingConv.inc | 380 if (ArgFlags.isSExt())
476 if (ArgFlags.isSExt())
486 if (ArgFlags.isSExt())
496 if (ArgFlags.isSExt())
506 if (ArgFlags.isSExt())
516 if (ArgFlags.isSExt())
526 if (ArgFlags.isSExt())
566 if (ArgFlags.isSExt())
625 if (ArgFlags.isSExt())
690 if (ArgFlags.isSExt())
[all …]
|
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineFrameInfo.h | 129 bool isSExt; member
135 PreAllocated(false), isAliased(A), isZExt(false), isSExt(false) {} in StackObject()
452 return Objects[ObjectIdx+NumFixedObjects].isSExt; in isObjectSExt()
458 Objects[ObjectIdx+NumFixedObjects].isSExt = IsSExt; in setObjectSExt()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenCallingConv.inc | 118 if (ArgFlags.isSExt())
318 if (ArgFlags.isSExt())
328 if (ArgFlags.isSExt())
338 if (ArgFlags.isSExt())
348 if (ArgFlags.isSExt())
394 if (ArgFlags.isSExt())
406 if (ArgFlags.isSExt())
563 if (ArgFlags.isSExt())
573 if (ArgFlags.isSExt())
583 if (ArgFlags.isSExt())
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | MachineFrameInfo.h | 163 bool isSExt = false; member
489 return Objects[ObjectIdx+NumFixedObjects].isSExt; in isObjectSExt()
495 Objects[ObjectIdx+NumFixedObjects].isSExt = IsSExt; in setObjectSExt()
|
| D | TargetCallingConv.h | 66 bool isSExt() const { return IsSExt; } in isSExt() function
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCMachineFunctionInfo.cpp | 50 return LiveIn.second.isSExt(); in isLiveInSExt()
|
| D | PPCISelDAGToDAG.cpp | 4231 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select() local
4234 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
4240 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break; in Select()
4246 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
4251 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; in Select()
4268 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select() local
4271 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
4279 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break; in Select()
4285 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) && in Select()
4290 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break; in Select()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenCallingConv.inc | 120 if (ArgFlags.isSExt())
135 if (ArgFlags.isSExt())
276 if (ArgFlags.isSExt())
290 if (ArgFlags.isSExt())
344 if (ArgFlags.isSExt())
473 if (ArgFlags.isSExt())
717 if (ArgFlags.isSExt())
734 if (ArgFlags.isSExt())
786 if (ArgFlags.isSExt())
|
| /external/llvm/include/llvm/Target/ |
| D | TargetCallingConv.h | 73 bool isSExt() const { return Flags & SExt; } in isSExt() function
|
| D | TargetLowering.h | 2464 bool isSExt : 1; member
2476 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), in ArgListEntry()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenCallingConv.inc | 124 if (ArgFlags.isSExt())
323 if (ArgFlags.isSExt())
465 if (ArgFlags.isSExt())
641 if (ArgFlags.isSExt())
763 if (ArgFlags.isSExt())
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenCallingConv.inc | 127 if (ArgFlags.isSExt())
371 if (ArgFlags.isSExt())
584 if (ArgFlags.isSExt())
698 if (ArgFlags.isSExt())
728 if (ArgFlags.isSExt())
847 if (ArgFlags.isSExt())
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 686 bool isSExt = false; in select() local
690 isSExt = true; in select()
708 if (isSExt) { in select()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.cpp | 98 Entry.isSExt = false; in EmitSpecializedLibcall()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 2516 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select() local
2519 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
2525 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break; in Select()
2531 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
2536 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; in Select()
2553 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select() local
2556 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
2564 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break; in Select()
2570 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) && in Select()
2575 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break; in Select()
[all …]
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZCallingConv.td | 13 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallingConv.td | 17 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZCallingConv.td | 13 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 1948 Entry.isSExt = isSigned; in ExpandLibCall()
1999 Entry.isSExt = isSigned; in ExpandLibCall()
2033 Entry.isSExt = isSigned; in ExpandChainLibCall()
2120 Entry.isSExt = isSigned; in ExpandDivRemLibCall()
2129 Entry.isSExt = isSigned; in ExpandDivRemLibCall()
2224 Entry.isSExt = false; in ExpandSinCosLibCall()
2232 Entry.isSExt = false; in ExpandSinCosLibCall()
2240 Entry.isSExt = false; in ExpandSinCosLibCall()
|
| D | SelectionDAGBuilder.cpp | 697 bool isSExt = true; in getCopyFromRegs() local
700 isSExt = true; // ASSERT SEXT 1 in getCopyFromRegs()
703 isSExt = false; // ASSERT ZEXT 1 in getCopyFromRegs()
706 isSExt = true; // ASSERT SEXT 8 in getCopyFromRegs()
709 isSExt = false; // ASSERT ZEXT 8 in getCopyFromRegs()
712 isSExt = true; // ASSERT SEXT 16 in getCopyFromRegs()
715 isSExt = false; // ASSERT ZEXT 16 in getCopyFromRegs()
718 isSExt = true; // ASSERT SEXT 32 in getCopyFromRegs()
721 isSExt = false; // ASSERT ZEXT 32 in getCopyFromRegs()
728 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
[all …]
|
| D | LegalizeTypes.cpp | 1094 Entry.isSExt = isSigned; in ExpandChainLibCall()
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 1303 if (Outs[OIdx].Flags.isSExt()) in LowerCall()
1316 else if (Outs[OIdx].Flags.isSExt() && VT.getSizeInBits() < 32) in LowerCall()
2186 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments()
2312 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments()
|
| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1218 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in X86SelectRet()
1224 if (Outs[0].Flags.isSExt()) in X86SelectRet()
3069 if (Flags.isSExt()) in fastLowerCall()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 168 if (ArgFlags.isSExt()) in CC_Hexagon_VarArg()
233 if (ArgFlags.isSExt()) in CC_Hexagon()
400 if (ArgFlags.isSExt()) in RetCC_Hexagon()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1240 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in X86SelectRet()
1246 if (Outs[0].Flags.isSExt()) in X86SelectRet()
3277 if (Flags.isSExt()) in fastLowerCall()
|