/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
D | TargetCallingConv.h | 72 bool isSRet() const { return IsSRet; } in isSRet() function
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/external/llvm/lib/Target/Mips/ |
D | MipsCCState.cpp | 123 if (Ins[i].Flags.isSRet()) { in PreAnalyzeFormalArgumentsForF128()
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D | MipsFastISel.cpp | 1282 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal()) in fastLowerCall()
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/external/llvm/include/llvm/Target/ |
D | TargetCallingConv.h | 79 bool isSRet() const { return Flags & SRet; } in isSRet() function
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D | TargetCallingConv.td | 78 class CCIfSRet<CCAction A> : CCIf<"ArgFlags.isSRet()", A> {}
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D | TargetLowering.h | 2467 bool isSRet : 1; member 2477 isSRet(false), isNest(false), isByVal(false), isInAlloca(false), in ArgListEntry()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
D | MipsCCState.cpp | 157 if (Ins[i].Flags.isSRet()) { in PreAnalyzeFormalArgumentsForF128()
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D | MipsCallLowering.cpp | 306 if (Arg.Flags.isByVal() || Arg.Flags.isSRet()) in lowerCall()
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D | MipsFastISel.cpp | 1501 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal()) in fastLowerCall()
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D | MipsISelLowering.cpp | 3439 if (Ins[i].Flags.isSRet()) { in LowerFormalArguments()
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/ |
D | TargetCallingConv.td | 78 class CCIfSRet<CCAction A> : CCIf<"ArgFlags.isSRet()", A> {}
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
D | AArch64GenCallingConv.inc | 79 if (ArgFlags.isSRet()) { 330 if (ArgFlags.isSRet()) {
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/external/llvm/lib/Target/Sparc/ |
D | SparcISelLowering.cpp | 43 assert (ArgFlags.isSRet()); in CC_Sparc_Assign_SRet() 402 if (Ins[InIdx].Flags.isSRet()) { in LowerFormalArguments_32() 826 if (Flags.isSRet()) { in LowerCall_32() 2195 Entry.isSRet = true; in LowerF128Op()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
D | SparcISelLowering.cpp | 45 assert (ArgFlags.isSRet()); in CC_Sparc_Assign_SRet() 404 if (Ins[InIdx].Flags.isSRet()) { in LowerFormalArguments_32() 818 if (Flags.isSRet()) { in LowerCall_32()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
D | RISCVISelLowering.cpp | 1146 auto IsCalleeStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet(); in IsEligibleForTailCallOptimization()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/ |
D | MSP430ISelLowering.cpp | 683 if (Ins[i].Flags.isSRet()) { in LowerCCCArguments()
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
D | X86GenCallingConv.inc | 1110 if (ArgFlags.isSRet()) { 1438 if (ArgFlags.isSRet()) { 2238 if (ArgFlags.isSRet()) {
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/external/llvm/lib/Target/PowerPC/ |
D | PPCFastISel.cpp | 1523 if (Flags.isInReg() || Flags.isSRet() || Flags.isNest() || Flags.isByVal()) in fastLowerCall()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
D | PPCFastISel.cpp | 1610 if (Flags.isInReg() || Flags.isSRet() || Flags.isNest() || Flags.isByVal()) in fastLowerCall()
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAGBuilder.cpp | 5798 if (Entry.isSRet && isa<Instruction>(V)) in LowerCallTo() 7517 Entry.isSRet = true; in LowerCallTo() 7591 if (Args[i].isSRet) in LowerCallTo()
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D | TargetLowering.cpp | 104 isSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet); in setAttributes()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
D | HexagonISelLowering.cpp | 325 bool IsStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet(); in LowerCall()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonISelLowering.cpp | 671 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); in LowerCall()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
D | AArch64FastISel.cpp | 3181 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal() || in fastLowerCall()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64FastISel.cpp | 3095 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal() || in fastLowerCall()
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