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Searched refs:l2csr0 (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/powerpc/cpu/mpc85xx/
Dcpu_init.c567 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); in enable_cluster_l2()
568 while ((in_be32(&l2cache->l2csr0) in enable_cluster_l2()
571 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); in enable_cluster_l2()
706 if (l2cache->l2csr0 & L2CSR0_L2E) in l2cache_init()
/external/u-boot/arch/powerpc/include/asm/
Dimmap_85xx.h3054 u32 l2csr0; /* 0x000 L2 cache control and status register 0 */ member