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Searched refs:l2csr1 (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/powerpc/cpu/mpc85xx/
Dcpu_init.c563 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); in enable_cluster_l2()
/external/u-boot/arch/powerpc/include/asm/
Dimmap_85xx.h3055 u32 l2csr1; /* 0x004 L2 cache control and status register 1 */ member