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Searched refs:mfvsrwz (Results 1 – 21 of 21) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dfp-int-conversions-direct-moves.ll14 ; CHECK: mfvsrwz 3, [[CONVREG01]]
40 ; CHECK: mfvsrwz 3, [[CONVREG02]]
66 ; CHECK: mfvsrwz 3, [[CONVREG03]]
92 ; CHECK: mfvsrwz 3, [[CONVREG04]]
118 ; CHECK: mfvsrwz 3, [[CONVREG05]]
144 ; CHECK: mfvsrwz 3, [[CONVREG06]]
170 ; CHECK: mfvsrwz 3, [[CONVREG07]]
196 ; CHECK: mfvsrwz 3, [[CONVREG08]]
222 ; CHECK: mfvsrwz 3, [[CONVREG09]]
248 ; CHECK: mfvsrwz 3, [[CONVREG10]]
[all …]
Dvec_extract_p9_2.ll139 ; When extracting word element 2 on LE, it's better to use mfvsrwz rather than vextuwrx
143 ; CHECK-LE-NEXT: mfvsrwz 3, 34
158 ; CHECK-LE-NEXT: mfvsrwz 3, 34
178 ; CHECK-LE-NEXT: mfvsrwz 3, 34
195 ; CHECK-LE-NEXT: mfvsrwz 3, 34
212 ; When extracting word element 1 on BE, it's better to use mfvsrwz rather than vextuwlx
222 ; CHECK-BE-NEXT: mfvsrwz 3, 34
240 ; CHECK-BE-NEXT: mfvsrwz 3, 34
Dstore_fptoi.ll69 ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
91 ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
155 ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
177 ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
256 ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
281 ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
360 ; CHECK-PWR8-NEXT: mfvsrwz [[REG2:[0-9]+]], [[CONV]]
385 ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
453 ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
475 ; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
[all …]
Df128-truncateNconv.ll207 ; CHECK-NEXT: mfvsrwz r[[REG2:[0-9]+]], v[[CONV]]
249 ; CHECK-NEXT: mfvsrwz r[[REG2:[0-9]+]], v[[CONV]]
284 ; CHECK-NEXT: mfvsrwz r3, v[[CONV]]
325 ; CHECK-NEXT: mfvsrwz r3, v[[CONV]]
357 ; CHECK-NEXT: mfvsrwz r3, v2
395 ; CHECK-NEXT: mfvsrwz r3, v2
434 ; CHECK-NEXT: mfvsrwz r3, v2
472 ; CHECK-NEXT: mfvsrwz r3, v2
511 ; CHECK-NEXT: mfvsrwz r3, v2
549 ; CHECK-NEXT: mfvsrwz r3, v2
[all …]
Dbitcasts-direct-move.ll14 ; CHECK: mfvsrwz 3, [[SHIFTREG]]
54 ; CHECK: mfvsrwz 3, [[SHIFTREG]]
Dp8-scalar_vector_conversions.ll877 ; CHECK: mfvsrwz 3, [[SHL]]
881 ; CHECK-LE: mfvsrwz 3, [[SHL]]
891 ; CHECK: mfvsrwz 3, 34
895 ; CHECK-LE: mfvsrwz 3, [[SHL]]
906 ; CHECK: mfvsrwz 3, [[SHL]]
909 ; CHECK-LE: mfvsrwz 3, 34
920 ; CHECK: mfvsrwz 3, [[SHL]]
924 ; CHECK-LE: mfvsrwz 3, [[SHL]]
935 ; CHECK: mfvsrwz 3, [[SHL]]
938 ; CHECK-LE: mfvsrwz 3, [[SHL]]
[all …]
Dfp64-to-int16.ll9 ; CHECK-NEXT: mfvsrwz 3, 1
Df128-passByValue.ll39 ; CHECK-NEXT: mfvsrwz r3, v2
/external/llvm/test/CodeGen/PowerPC/
Dfp-int-conversions-direct-moves.ll14 ; CHECK: mfvsrwz 3, [[CONVREG01]]
40 ; CHECK: mfvsrwz 3, [[CONVREG02]]
66 ; CHECK: mfvsrwz 3, [[CONVREG03]]
92 ; CHECK: mfvsrwz 3, [[CONVREG04]]
118 ; CHECK: mfvsrwz 3, [[CONVREG05]]
144 ; CHECK: mfvsrwz 3, [[CONVREG06]]
170 ; CHECK: mfvsrwz 3, [[CONVREG07]]
196 ; CHECK: mfvsrwz 3, [[CONVREG08]]
222 ; CHECK: mfvsrwz 3, [[CONVREG09]]
248 ; CHECK: mfvsrwz 3, [[CONVREG10]]
[all …]
Dbitcasts-direct-move.ll13 ; CHECK: mfvsrwz 3, [[SHIFTREG]]
53 ; CHECK: mfvsrwz 3, [[SHIFTREG]]
Dp8-scalar_vector_conversions.ll1102 ; CHECK: mfvsrwz 3, [[SHL]]
1106 ; CHECK-LE: mfvsrwz 3, [[SHL]]
1119 ; CHECK: mfvsrwz 3, 34
1123 ; CHECK-LE: mfvsrwz 3, [[SHL]]
1137 ; CHECK: mfvsrwz 3, [[SHL]]
1140 ; CHECK-LE: mfvsrwz 3, 34
1154 ; CHECK: mfvsrwz 3, [[SHL]]
1158 ; CHECK-LE: mfvsrwz 3, [[SHL]]
1172 ; CHECK: mfvsrwz 3, [[SHL]]
1176 ; CHECK-LE: mfvsrwz 3, [[SHL]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dvsx.s541 # CHECK-BE: mfvsrwz 5, 0 # encoding: [0x7c,0x05,0x00,0xe6]
542 # CHECK-LE: mfvsrwz 5, 0 # encoding: [0xe6,0x00,0x05,0x7c]
543 mfvsrwz 5, 0
/external/llvm/test/MC/PowerPC/
Dvsx.s538 # CHECK-BE: mfvsrwz 5, 0 # encoding: [0x7c,0x05,0x00,0xe6]
539 # CHECK-LE: mfvsrwz 5, 0 # encoding: [0xe6,0x00,0x05,0x7c]
540 mfvsrwz 5, 0
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dvsx.txt531 # CHECK: mfvsrwz 5, 0
/external/llvm/test/MC/Disassembler/PowerPC/
Dvsx.txt531 # CHECK: mfvsrwz 5, 0
/external/v8/src/codegen/ppc/
Dassembler-ppc.h1020 void mfvsrwz(const Register ra, const Simd128Register r);
Dconstants-ppc.h1993 V(mfvsrwz, MFVSRWZ, 0x7C0000E6) \
Dassembler-ppc.cc1779 void Assembler::mfvsrwz(const Register ra, const Simd128Register rs) { in mfvsrwz() function in v8::internal::Assembler
/external/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td1248 "mfvsrwz $rA, $XT", IIC_VecGeneral,
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc4264 "mftcr\005mfvrd\010mfvrsave\006mfvscr\006mfvsrd\007mfvsrld\007mfvsrwz\005"
5878 …{ 7151 /* mfvsrwz */, PPC::MFVSRWZ, Convert__RegGPRC1_0__RegVSFRC1_1, 0, { MCK_RegGPRC, MCK_RegVSF…
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td1511 "mfvsrwz $rA, $XT", IIC_VecGeneral,