1; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ 2; RUN: -verify-machineinstrs -enable-ppc-quad-precision \ 3; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s 4 5@f128Array = global [4 x fp128] [fp128 0xL00000000000000004004C00000000000, 6 fp128 0xLF000000000000000400808AB851EB851, 7 fp128 0xL5000000000000000400E0C26324C8366, 8 fp128 0xL8000000000000000400A24E2E147AE14], 9 align 16 10 11; Function Attrs: norecurse nounwind readonly 12define i64 @qpConv2sdw(fp128* nocapture readonly %a) { 13entry: 14 %0 = load fp128, fp128* %a, align 16 15 %conv = fptosi fp128 %0 to i64 16 ret i64 %conv 17 18; CHECK-LABEL: qpConv2sdw 19; CHECK: lxv v[[REG:[0-9]+]], 0(r3) 20; CHECK-NEXT: xscvqpsdz v[[CONV:[0-9]+]], v[[REG]] 21; CHECK-NEXT: mfvsrd r3, v[[CONV]] 22; CHECK-NEXT: blr 23} 24 25; Function Attrs: norecurse nounwind 26define void @qpConv2sdw_02(i64* nocapture %res) local_unnamed_addr #1 { 27entry: 28 %0 = load fp128, fp128* getelementptr inbounds 29 ([4 x fp128], [4 x fp128]* @f128Array, i64 0, 30 i64 2), align 16 31 %conv = fptosi fp128 %0 to i64 32 store i64 %conv, i64* %res, align 8 33 ret void 34 35; CHECK-LABEL: qpConv2sdw_02 36; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha 37; CHECK: ld r[[REG0]], .LC0@toc@l(r[[REG0]]) 38; CHECK: lxv v[[REG:[0-9]+]], 32(r[[REG0]]) 39; CHECK-NEXT: xscvqpsdz v[[CONV:[0-9]+]], v[[REG]] 40; CHECK-NEXT: stxsd v[[CONV]], 0(r3) 41; CHECK-NEXT: blr 42} 43 44; Function Attrs: norecurse nounwind readonly 45define i64 @qpConv2sdw_03(fp128* nocapture readonly %a) { 46entry: 47 %0 = load fp128, fp128* %a, align 16 48 %1 = load fp128, fp128* getelementptr inbounds 49 ([4 x fp128], [4 x fp128]* @f128Array, i64 0, 50 i64 1), align 16 51 %add = fadd fp128 %0, %1 52 %conv = fptosi fp128 %add to i64 53 ret i64 %conv 54 55; CHECK-LABEL: qpConv2sdw_03 56; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha 57; CHECK-DAG: ld r[[REG0]], .LC0@toc@l(r[[REG0]]) 58; CHECK-DAG: lxv v[[REG1:[0-9]+]], 16(r[[REG0]]) 59; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3) 60; CHECK: xsaddqp v[[REG]], v[[REG]], v[[REG1]] 61; CHECK-NEXT: xscvqpsdz v[[CONV:[0-9]+]], v[[REG]] 62; CHECK-NEXT: mfvsrd r3, v[[CONV]] 63; CHECK-NEXT: blr 64} 65 66; Function Attrs: norecurse nounwind 67define void @qpConv2sdw_04(fp128* nocapture readonly %a, 68 fp128* nocapture readonly %b, i64* nocapture %res) { 69entry: 70 %0 = load fp128, fp128* %a, align 16 71 %1 = load fp128, fp128* %b, align 16 72 %add = fadd fp128 %0, %1 73 %conv = fptosi fp128 %add to i64 74 store i64 %conv, i64* %res, align 8 75 ret void 76 77; CHECK-LABEL: qpConv2sdw_04 78; CHECK-DAG: lxv v[[REG1:[0-9]+]], 0(r4) 79; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3) 80; CHECK: xsaddqp v[[REG]], v[[REG]], v[[REG1]] 81; CHECK-NEXT: xscvqpsdz v[[CONV:[0-9]+]], v[[REG]] 82; CHECK-NEXT: stxsd v[[CONV]], 0(r5) 83; CHECK-NEXT: blr 84} 85 86; Function Attrs: norecurse nounwind 87define void @qpConv2sdw_testXForm(i64* nocapture %res, i32 signext %idx) { 88entry: 89 %0 = load fp128, fp128* getelementptr inbounds 90 ([4 x fp128], [4 x fp128]* @f128Array, 91 i64 0, i64 2), align 16 92 %conv = fptosi fp128 %0 to i64 93 %idxprom = sext i32 %idx to i64 94 %arrayidx = getelementptr inbounds i64, i64* %res, i64 %idxprom 95 store i64 %conv, i64* %arrayidx, align 8 96 ret void 97 98; CHECK-LABEL: qpConv2sdw_testXForm 99; CHECK: xscvqpsdz v[[CONV:[0-9]+]], 100; CHECK-NEXT: stxsdx v[[CONV]], r3, r4 101; CHECK-NEXT: blr 102} 103 104; Function Attrs: norecurse nounwind readonly 105define i64 @qpConv2udw(fp128* nocapture readonly %a) { 106entry: 107 %0 = load fp128, fp128* %a, align 16 108 %conv = fptoui fp128 %0 to i64 109 ret i64 %conv 110 111; CHECK-LABEL: qpConv2udw 112; CHECK: lxv v[[REG:[0-9]+]], 0(r3) 113; CHECK-NEXT: xscvqpudz v[[CONV:[0-9]+]], v[[REG]] 114; CHECK-NEXT: mfvsrd r3, v[[CONV]] 115; CHECK-NEXT: blr 116} 117 118; Function Attrs: norecurse nounwind 119define void @qpConv2udw_02(i64* nocapture %res) { 120entry: 121 %0 = load fp128, fp128* getelementptr inbounds 122 ([4 x fp128], [4 x fp128]* @f128Array, i64 0, 123 i64 2), align 16 124 %conv = fptoui fp128 %0 to i64 125 store i64 %conv, i64* %res, align 8 126 ret void 127 128; CHECK-LABEL: qpConv2udw_02 129; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha 130; CHECK: ld r[[REG0]], .LC0@toc@l(r[[REG0]]) 131; CHECK: lxv v[[REG:[0-9]+]], 32(r[[REG0]]) 132; CHECK-NEXT: xscvqpudz v[[CONV:[0-9]+]], v[[REG]] 133; CHECK-NEXT: stxsd v[[CONV]], 0(r3) 134; CHECK-NEXT: blr 135} 136 137; Function Attrs: norecurse nounwind readonly 138define i64 @qpConv2udw_03(fp128* nocapture readonly %a) { 139entry: 140 %0 = load fp128, fp128* %a, align 16 141 %1 = load fp128, fp128* getelementptr inbounds 142 ([4 x fp128], [4 x fp128]* @f128Array, i64 0, 143 i64 1), align 16 144 %add = fadd fp128 %0, %1 145 %conv = fptoui fp128 %add to i64 146 ret i64 %conv 147 148; CHECK-LABEL: qpConv2udw_03 149; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha 150; CHECK-DAG: ld r[[REG0]], .LC0@toc@l(r[[REG0]]) 151; CHECK-DAG: lxv v[[REG1:[0-9]+]], 16(r[[REG0]]) 152; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3) 153; CHECK: xsaddqp v[[REG]], v[[REG]], v[[REG1]] 154; CHECK-NEXT: xscvqpudz v[[CONV:[0-9]+]], v[[REG]] 155; CHECK-NEXT: mfvsrd r3, v[[CONV]] 156; CHECK-NEXT: blr 157} 158 159; Function Attrs: norecurse nounwind 160define void @qpConv2udw_04(fp128* nocapture readonly %a, 161 fp128* nocapture readonly %b, i64* nocapture %res) { 162entry: 163 %0 = load fp128, fp128* %a, align 16 164 %1 = load fp128, fp128* %b, align 16 165 %add = fadd fp128 %0, %1 166 %conv = fptoui fp128 %add to i64 167 store i64 %conv, i64* %res, align 8 168 ret void 169 170; CHECK-LABEL: qpConv2udw_04 171; CHECK-DAG: lxv v[[REG1:[0-9]+]], 0(r4) 172; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3) 173; CHECK: xsaddqp v[[REG]], v[[REG]], v[[REG1]] 174; CHECK-NEXT: xscvqpudz v[[CONV:[0-9]+]], v[[REG]] 175; CHECK-NEXT: stxsd v[[CONV]], 0(r5) 176; CHECK-NEXT: blr 177} 178 179; Function Attrs: norecurse nounwind 180define void @qpConv2udw_testXForm(i64* nocapture %res, i32 signext %idx) { 181entry: 182 %0 = load fp128, fp128* getelementptr inbounds 183 ([4 x fp128], [4 x fp128]* @f128Array, 184 i64 0, i64 0), align 16 185 %conv = fptoui fp128 %0 to i64 186 %idxprom = sext i32 %idx to i64 187 %arrayidx = getelementptr inbounds i64, i64* %res, i64 %idxprom 188 store i64 %conv, i64* %arrayidx, align 8 189 ret void 190 191; CHECK-LABEL: qpConv2udw_testXForm 192; CHECK: xscvqpudz v[[CONV:[0-9]+]], 193; CHECK-NEXT: stxsdx v[[CONV]], r3, r4 194; CHECK-NEXT: blr 195} 196 197; Function Attrs: norecurse nounwind readonly 198define signext i32 @qpConv2sw(fp128* nocapture readonly %a) { 199entry: 200 %0 = load fp128, fp128* %a, align 16 201 %conv = fptosi fp128 %0 to i32 202 ret i32 %conv 203 204; CHECK-LABEL: qpConv2sw 205; CHECK: lxv v[[REG:[0-9]+]], 0(r3) 206; CHECK-NEXT: xscvqpswz v[[CONV:[0-9]+]], v[[REG]] 207; CHECK-NEXT: mfvsrwz r[[REG2:[0-9]+]], v[[CONV]] 208; CHECK-NEXT: extsw r3, r[[REG2]] 209; CHECK-NEXT: blr 210} 211 212; Function Attrs: norecurse nounwind 213define void @qpConv2sw_02(i32* nocapture %res) { 214entry: 215 %0 = load fp128, fp128* getelementptr inbounds 216 ([4 x fp128], [4 x fp128]* @f128Array, i64 0, 217 i64 2), align 16 218 %conv = fptosi fp128 %0 to i32 219 store i32 %conv, i32* %res, align 4 220 ret void 221 222; CHECK-LABEL: qpConv2sw_02 223; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha 224; CHECK: ld r[[REG0]], .LC0@toc@l(r[[REG0]]) 225; CHECK: lxv v[[REG:[0-9]+]], 32(r[[REG0]]) 226; CHECK-NEXT: xscvqpswz v[[CONV:[0-9]+]], v[[REG]] 227; CHECK-NEXT: stxsiwx v[[CONV]], 0, r3 228; CHECK-NEXT: blr 229} 230 231; Function Attrs: norecurse nounwind readonly 232define signext i32 @qpConv2sw_03(fp128* nocapture readonly %a) { 233entry: 234 %0 = load fp128, fp128* %a, align 16 235 %1 = load fp128, fp128* getelementptr inbounds 236 ([4 x fp128], [4 x fp128]* @f128Array, i64 0, 237 i64 1), align 16 238 %add = fadd fp128 %0, %1 239 %conv = fptosi fp128 %add to i32 240 ret i32 %conv 241 242; CHECK-LABEL: qpConv2sw_03 243; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha 244; CHECK-DAG: ld r[[REG0]], .LC0@toc@l(r[[REG0]]) 245; CHECK-DAG: lxv v[[REG1:[0-9]+]], 16(r[[REG0]]) 246; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3) 247; CHECK-NEXT: xsaddqp v[[ADD:[0-9]+]], v[[REG]], v[[REG1]] 248; CHECK-NEXT: xscvqpswz v[[CONV:[0-9]+]], v[[ADD]] 249; CHECK-NEXT: mfvsrwz r[[REG2:[0-9]+]], v[[CONV]] 250; CHECK-NEXT: extsw r3, r[[REG2]] 251; CHECK-NEXT: blr 252} 253 254; Function Attrs: norecurse nounwind 255define void @qpConv2sw_04(fp128* nocapture readonly %a, 256 fp128* nocapture readonly %b, i32* nocapture %res) { 257entry: 258 %0 = load fp128, fp128* %a, align 16 259 %1 = load fp128, fp128* %b, align 16 260 %add = fadd fp128 %0, %1 261 %conv = fptosi fp128 %add to i32 262 store i32 %conv, i32* %res, align 4 263 ret void 264 265; CHECK-LABEL: qpConv2sw_04 266; CHECK-DAG: lxv v[[REG1:[0-9]+]], 0(r4) 267; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3) 268; CHECK-NEXT: xsaddqp v[[ADD:[0-9]+]], v[[REG]], v[[REG1]] 269; CHECK-NEXT: xscvqpswz v[[CONV:[0-9]+]], v[[ADD]] 270; CHECK-NEXT: stxsiwx v[[CONV]], 0, r5 271; CHECK-NEXT: blr 272} 273 274; Function Attrs: norecurse nounwind readonly 275define zeroext i32 @qpConv2uw(fp128* nocapture readonly %a) { 276entry: 277 %0 = load fp128, fp128* %a, align 16 278 %conv = fptoui fp128 %0 to i32 279 ret i32 %conv 280 281; CHECK-LABEL: qpConv2uw 282; CHECK: lxv v[[REG:[0-9]+]], 0(r3) 283; CHECK-NEXT: xscvqpuwz v[[CONV:[0-9]+]], v[[REG]] 284; CHECK-NEXT: mfvsrwz r3, v[[CONV]] 285; CHECK: blr 286} 287 288; Function Attrs: norecurse nounwind 289define void @qpConv2uw_02(i32* nocapture %res) { 290entry: 291 %0 = load fp128, fp128* getelementptr inbounds 292 ([4 x fp128], [4 x fp128]* @f128Array, i64 0, 293 i64 2), align 16 294 %conv = fptoui fp128 %0 to i32 295 store i32 %conv, i32* %res, align 4 296 ret void 297 298; CHECK-LABEL: qpConv2uw_02 299; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha 300; CHECK: ld r[[REG0]], .LC0@toc@l(r[[REG0]]) 301; CHECK: lxv v[[REG:[0-9]+]], 32(r[[REG0]]) 302; CHECK-NEXT: xscvqpuwz v[[CONV:[0-9]+]], v[[REG]] 303; CHECK-NEXT: stxsiwx v[[CONV]], 0, r3 304; CHECK: blr 305} 306 307; Function Attrs: norecurse nounwind readonly 308define zeroext i32 @qpConv2uw_03(fp128* nocapture readonly %a) { 309entry: 310 %0 = load fp128, fp128* %a, align 16 311 %1 = load fp128, fp128* getelementptr inbounds 312 ([4 x fp128], [4 x fp128]* @f128Array, i64 0, 313 i64 1), align 16 314 %add = fadd fp128 %0, %1 315 %conv = fptoui fp128 %add to i32 316 ret i32 %conv 317 318; CHECK-LABEL: qpConv2uw_03 319; CHECK: addis r[[REG0:[0-9]+]], r2, .LC0@toc@ha 320; CHECK-DAG: ld r[[REG0]], .LC0@toc@l(r[[REG0]]) 321; CHECK-DAG: lxv v[[REG1:[0-9]+]], 16(r[[REG0]]) 322; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3) 323; CHECK-NEXT: xsaddqp v[[ADD:[0-9]+]], v[[REG]], v[[REG1]] 324; CHECK-NEXT: xscvqpuwz v[[CONV:[0-9]+]], v[[ADD]] 325; CHECK-NEXT: mfvsrwz r3, v[[CONV]] 326; CHECK: blr 327} 328 329; Function Attrs: norecurse nounwind 330define void @qpConv2uw_04(fp128* nocapture readonly %a, 331 fp128* nocapture readonly %b, i32* nocapture %res) { 332entry: 333 %0 = load fp128, fp128* %a, align 16 334 %1 = load fp128, fp128* %b, align 16 335 %add = fadd fp128 %0, %1 336 %conv = fptoui fp128 %add to i32 337 store i32 %conv, i32* %res, align 4 338 ret void 339 340; CHECK-LABEL: qpConv2uw_04 341; CHECK-DAG: lxv v[[REG1:[0-9]+]], 0(r4) 342; CHECK-DAG: lxv v[[REG:[0-9]+]], 0(r3) 343; CHECK-NEXT: xsaddqp v[[ADD:[0-9]+]], v[[REG]], v[[REG1]] 344; CHECK-NEXT: xscvqpuwz v[[CONV:[0-9]+]], v[[ADD]] 345; CHECK-NEXT: stxsiwx v[[CONV]], 0, r5 346; CHECK: blr 347} 348 349; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 350 351; Function Attrs: norecurse nounwind readonly 352define signext i16 @qpConv2shw(fp128* nocapture readonly %a) { 353; CHECK-LABEL: qpConv2shw: 354; CHECK: # %bb.0: # %entry 355; CHECK-NEXT: lxv v2, 0(r3) 356; CHECK-NEXT: xscvqpswz v2, v2 357; CHECK-NEXT: mfvsrwz r3, v2 358; CHECK-NEXT: extsh r3, r3 359; CHECK-NEXT: blr 360entry: 361 %0 = load fp128, fp128* %a, align 16 362 %conv = fptosi fp128 %0 to i16 363 ret i16 %conv 364} 365 366; Function Attrs: norecurse nounwind 367define void @qpConv2shw_02(i16* nocapture %res) { 368; CHECK-LABEL: qpConv2shw_02: 369; CHECK: # %bb.0: # %entry 370; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 371; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 372; CHECK-NEXT: lxv v2, 32(r4) 373; CHECK-NEXT: xscvqpswz v2, v2 374; CHECK-NEXT: stxsihx v2, 0, r3 375; CHECK-NEXT: blr 376entry: 377 %0 = load fp128, fp128* getelementptr inbounds 378 ([4 x fp128], [4 x fp128]* @f128Array, 379 i64 0, i64 2), align 16 380 %conv = fptosi fp128 %0 to i16 381 store i16 %conv, i16* %res, align 2 382 ret void 383} 384 385; Function Attrs: norecurse nounwind readonly 386define signext i16 @qpConv2shw_03(fp128* nocapture readonly %a) { 387; CHECK-LABEL: qpConv2shw_03: 388; CHECK: # %bb.0: # %entry 389; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 390; CHECK-NEXT: lxv v2, 0(r3) 391; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 392; CHECK-NEXT: lxv v3, 16(r4) 393; CHECK-NEXT: xsaddqp v2, v2, v3 394; CHECK-NEXT: xscvqpswz v2, v2 395; CHECK-NEXT: mfvsrwz r3, v2 396; CHECK-NEXT: extsh r3, r3 397; CHECK-NEXT: blr 398entry: 399 %0 = load fp128, fp128* %a, align 16 400 %1 = load fp128, fp128* getelementptr inbounds 401 ([4 x fp128], [4 x fp128]* @f128Array, 402 i64 0, i64 1), align 16 403 %add = fadd fp128 %0, %1 404 %conv = fptosi fp128 %add to i16 405 ret i16 %conv 406} 407 408; Function Attrs: norecurse nounwind 409define void @qpConv2shw_04(fp128* nocapture readonly %a, 410 fp128* nocapture readonly %b, i16* nocapture %res) { 411; CHECK-LABEL: qpConv2shw_04: 412; CHECK: # %bb.0: # %entry 413; CHECK-NEXT: lxv v2, 0(r3) 414; CHECK-NEXT: lxv v3, 0(r4) 415; CHECK-NEXT: xsaddqp v2, v2, v3 416; CHECK-NEXT: xscvqpswz v2, v2 417; CHECK-NEXT: stxsihx v2, 0, r5 418; CHECK-NEXT: blr 419entry: 420 %0 = load fp128, fp128* %a, align 16 421 %1 = load fp128, fp128* %b, align 16 422 %add = fadd fp128 %0, %1 423 %conv = fptosi fp128 %add to i16 424 store i16 %conv, i16* %res, align 2 425 ret void 426} 427 428; Function Attrs: norecurse nounwind readonly 429define zeroext i16 @qpConv2uhw(fp128* nocapture readonly %a) { 430; CHECK-LABEL: qpConv2uhw: 431; CHECK: # %bb.0: # %entry 432; CHECK-NEXT: lxv v2, 0(r3) 433; CHECK-NEXT: xscvqpswz v2, v2 434; CHECK-NEXT: mfvsrwz r3, v2 435; CHECK-NEXT: clrldi r3, r3, 32 436; CHECK-NEXT: blr 437entry: 438 %0 = load fp128, fp128* %a, align 16 439 %conv = fptoui fp128 %0 to i16 440 ret i16 %conv 441} 442 443; Function Attrs: norecurse nounwind 444define void @qpConv2uhw_02(i16* nocapture %res) { 445; CHECK-LABEL: qpConv2uhw_02: 446; CHECK: # %bb.0: # %entry 447; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 448; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 449; CHECK-NEXT: lxv v2, 32(r4) 450; CHECK-NEXT: xscvqpuwz v2, v2 451; CHECK-NEXT: stxsihx v2, 0, r3 452; CHECK-NEXT: blr 453entry: 454 %0 = load fp128, fp128* getelementptr inbounds 455 ([4 x fp128], [4 x fp128]* @f128Array, 456 i64 0, i64 2), align 16 457 %conv = fptoui fp128 %0 to i16 458 store i16 %conv, i16* %res, align 2 459 ret void 460} 461 462; Function Attrs: norecurse nounwind readonly 463define zeroext i16 @qpConv2uhw_03(fp128* nocapture readonly %a) { 464; CHECK-LABEL: qpConv2uhw_03: 465; CHECK: # %bb.0: # %entry 466; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 467; CHECK-NEXT: lxv v2, 0(r3) 468; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 469; CHECK-NEXT: lxv v3, 16(r4) 470; CHECK-NEXT: xsaddqp v2, v2, v3 471; CHECK-NEXT: xscvqpswz v2, v2 472; CHECK-NEXT: mfvsrwz r3, v2 473; CHECK-NEXT: clrldi r3, r3, 32 474; CHECK-NEXT: blr 475entry: 476 %0 = load fp128, fp128* %a, align 16 477 %1 = load fp128, fp128* getelementptr inbounds 478 ([4 x fp128], [4 x fp128]* @f128Array, 479 i64 0, i64 1), align 16 480 %add = fadd fp128 %0, %1 481 %conv = fptoui fp128 %add to i16 482 ret i16 %conv 483} 484 485; Function Attrs: norecurse nounwind 486define void @qpConv2uhw_04(fp128* nocapture readonly %a, 487 fp128* nocapture readonly %b, i16* nocapture %res) { 488; CHECK-LABEL: qpConv2uhw_04: 489; CHECK: # %bb.0: # %entry 490; CHECK-NEXT: lxv v2, 0(r3) 491; CHECK-NEXT: lxv v3, 0(r4) 492; CHECK-NEXT: xsaddqp v2, v2, v3 493; CHECK-NEXT: xscvqpuwz v2, v2 494; CHECK-NEXT: stxsihx v2, 0, r5 495; CHECK-NEXT: blr 496entry: 497 %0 = load fp128, fp128* %a, align 16 498 %1 = load fp128, fp128* %b, align 16 499 %add = fadd fp128 %0, %1 500 %conv = fptoui fp128 %add to i16 501 store i16 %conv, i16* %res, align 2 502 ret void 503} 504 505; Function Attrs: norecurse nounwind readonly 506define signext i8 @qpConv2sb(fp128* nocapture readonly %a) { 507; CHECK-LABEL: qpConv2sb: 508; CHECK: # %bb.0: # %entry 509; CHECK-NEXT: lxv v2, 0(r3) 510; CHECK-NEXT: xscvqpswz v2, v2 511; CHECK-NEXT: mfvsrwz r3, v2 512; CHECK-NEXT: extsb r3, r3 513; CHECK-NEXT: blr 514entry: 515 %0 = load fp128, fp128* %a, align 16 516 %conv = fptosi fp128 %0 to i8 517 ret i8 %conv 518} 519 520; Function Attrs: norecurse nounwind 521define void @qpConv2sb_02(i8* nocapture %res) { 522; CHECK-LABEL: qpConv2sb_02: 523; CHECK: # %bb.0: # %entry 524; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 525; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 526; CHECK-NEXT: lxv v2, 32(r4) 527; CHECK-NEXT: xscvqpswz v2, v2 528; CHECK-NEXT: stxsibx v2, 0, r3 529; CHECK-NEXT: blr 530entry: 531 %0 = load fp128, fp128* getelementptr inbounds 532 ([4 x fp128], [4 x fp128]* @f128Array, 533 i64 0, i64 2), align 16 534 %conv = fptosi fp128 %0 to i8 535 store i8 %conv, i8* %res, align 1 536 ret void 537} 538 539; Function Attrs: norecurse nounwind readonly 540define signext i8 @qpConv2sb_03(fp128* nocapture readonly %a) { 541; CHECK-LABEL: qpConv2sb_03: 542; CHECK: # %bb.0: # %entry 543; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 544; CHECK-NEXT: lxv v2, 0(r3) 545; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 546; CHECK-NEXT: lxv v3, 16(r4) 547; CHECK-NEXT: xsaddqp v2, v2, v3 548; CHECK-NEXT: xscvqpswz v2, v2 549; CHECK-NEXT: mfvsrwz r3, v2 550; CHECK-NEXT: extsb r3, r3 551; CHECK-NEXT: blr 552entry: 553 %0 = load fp128, fp128* %a, align 16 554 %1 = load fp128, fp128* getelementptr inbounds 555 ([4 x fp128], [4 x fp128]* @f128Array, 556 i64 0, i64 1), align 16 557 %add = fadd fp128 %0, %1 558 %conv = fptosi fp128 %add to i8 559 ret i8 %conv 560} 561 562; Function Attrs: norecurse nounwind 563define void @qpConv2sb_04(fp128* nocapture readonly %a, 564 fp128* nocapture readonly %b, i8* nocapture %res) { 565; CHECK-LABEL: qpConv2sb_04: 566; CHECK: # %bb.0: # %entry 567; CHECK-NEXT: lxv v2, 0(r3) 568; CHECK-NEXT: lxv v3, 0(r4) 569; CHECK-NEXT: xsaddqp v2, v2, v3 570; CHECK-NEXT: xscvqpswz v2, v2 571; CHECK-NEXT: stxsibx v2, 0, r5 572; CHECK-NEXT: blr 573entry: 574 %0 = load fp128, fp128* %a, align 16 575 %1 = load fp128, fp128* %b, align 16 576 %add = fadd fp128 %0, %1 577 %conv = fptosi fp128 %add to i8 578 store i8 %conv, i8* %res, align 1 579 ret void 580} 581 582; Function Attrs: norecurse nounwind readonly 583define zeroext i8 @qpConv2ub(fp128* nocapture readonly %a) { 584; CHECK-LABEL: qpConv2ub: 585; CHECK: # %bb.0: # %entry 586; CHECK-NEXT: lxv v2, 0(r3) 587; CHECK-NEXT: xscvqpswz v2, v2 588; CHECK-NEXT: mfvsrwz r3, v2 589; CHECK-NEXT: clrldi r3, r3, 32 590; CHECK-NEXT: blr 591entry: 592 %0 = load fp128, fp128* %a, align 16 593 %conv = fptoui fp128 %0 to i8 594 ret i8 %conv 595} 596 597; Function Attrs: norecurse nounwind 598define void @qpConv2ub_02(i8* nocapture %res) { 599; CHECK-LABEL: qpConv2ub_02: 600; CHECK: # %bb.0: # %entry 601; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 602; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 603; CHECK-NEXT: lxv v2, 32(r4) 604; CHECK-NEXT: xscvqpuwz v2, v2 605; CHECK-NEXT: stxsibx v2, 0, r3 606; CHECK-NEXT: blr 607entry: 608 %0 = load fp128, fp128* getelementptr inbounds 609 ([4 x fp128], [4 x fp128]* @f128Array, 610 i64 0, i64 2), align 16 611 %conv = fptoui fp128 %0 to i8 612 store i8 %conv, i8* %res, align 1 613 ret void 614} 615 616; Function Attrs: norecurse nounwind readonly 617define zeroext i8 @qpConv2ub_03(fp128* nocapture readonly %a) { 618; CHECK-LABEL: qpConv2ub_03: 619; CHECK: # %bb.0: # %entry 620; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 621; CHECK-NEXT: lxv v2, 0(r3) 622; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 623; CHECK-NEXT: lxv v3, 16(r4) 624; CHECK-NEXT: xsaddqp v2, v2, v3 625; CHECK-NEXT: xscvqpswz v2, v2 626; CHECK-NEXT: mfvsrwz r3, v2 627; CHECK-NEXT: clrldi r3, r3, 32 628; CHECK-NEXT: blr 629entry: 630 %0 = load fp128, fp128* %a, align 16 631 %1 = load fp128, fp128* getelementptr inbounds 632 ([4 x fp128], [4 x fp128]* @f128Array, 633 i64 0, i64 1), align 16 634 %add = fadd fp128 %0, %1 635 %conv = fptoui fp128 %add to i8 636 ret i8 %conv 637} 638 639; Function Attrs: norecurse nounwind 640define void @qpConv2ub_04(fp128* nocapture readonly %a, 641 fp128* nocapture readonly %b, i8* nocapture %res) { 642; CHECK-LABEL: qpConv2ub_04: 643; CHECK: # %bb.0: # %entry 644; CHECK-NEXT: lxv v2, 0(r3) 645; CHECK-NEXT: lxv v3, 0(r4) 646; CHECK-NEXT: xsaddqp v2, v2, v3 647; CHECK-NEXT: xscvqpuwz v2, v2 648; CHECK-NEXT: stxsibx v2, 0, r5 649; CHECK-NEXT: blr 650entry: 651 %0 = load fp128, fp128* %a, align 16 652 %1 = load fp128, fp128* %b, align 16 653 %add = fadd fp128 %0, %1 654 %conv = fptoui fp128 %add to i8 655 store i8 %conv, i8* %res, align 1 656 ret void 657} 658