Home
last modified time | relevance | path

Searched refs:mmio_clrsetbits_32 (Results 1 – 25 of 29) sorted by relevance

12

/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
Ddfs.c500 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff, in gen_rk3399_ctl_params_f0()
507 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
516 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
524 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
529 mmio_clrsetbits_32(CTL_REG(i, 23), (0x7f << 16), in gen_rk3399_ctl_params_f0()
531 mmio_clrsetbits_32(CTL_REG(i, 23), (0x1f << 24), in gen_rk3399_ctl_params_f0()
533 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f, pdram_timing->al); in gen_rk3399_ctl_params_f0()
534 mmio_clrsetbits_32(CTL_REG(i, 26), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
543 mmio_clrsetbits_32(CTL_REG(i, 31), 0xffu << 24, in gen_rk3399_ctl_params_f0()
547 mmio_clrsetbits_32(CTL_REG(i, 34), 0xff, in gen_rk3399_ctl_params_f0()
[all …]
Dsuspend.c151 mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 24, in set_cs_training_index()
172 mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 16, in override_write_leveling_value()
174 mmio_clrsetbits_32(PHY_REG(ch, 63 + (128 * byte)), in override_write_leveling_value()
180 mmio_clrsetbits_32(CTL_REG(ch, 200), 0x1 << 8, 0x1 << 8); in override_write_leveling_value()
224 mmio_clrsetbits_32(PI_REG(ch, 100), 0x3 << 8, 0x2 << 8); in data_training()
227 mmio_clrsetbits_32(PI_REG(ch, 92), in data_training()
265 mmio_clrsetbits_32(PI_REG(ch, 60), 0x3 << 8, 0x2 << 8); in data_training()
267 mmio_clrsetbits_32(PI_REG(ch, 59), in data_training()
311 mmio_clrsetbits_32(PI_REG(ch, 80), 0x3 << 24, in data_training()
317 mmio_clrsetbits_32(PI_REG(ch, 74), in data_training()
[all …]
/external/arm-trusted-firmware/plat/mediatek/mt8183/
Dbl31_plat_setup.c48 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, in platform_setup_cpu()
50 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, in platform_setup_cpu()
53 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config, in platform_setup_cpu()
59 mmio_clrsetbits_32( in platform_setup_cpu()
67 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config, in platform_setup_cpu()
73 mmio_clrsetbits_32( in platform_setup_cpu()
Dplat_mt_gic.c145 mmio_clrsetbits_32(GIC_SYNC_DCM, GIC_SYNC_DCM_MASK, GIC_SYNC_DCM_ON); in mt_gic_sync_dcm_enable()
150 mmio_clrsetbits_32(GIC_SYNC_DCM, GIC_SYNC_DCM_MASK, GIC_SYNC_DCM_OFF); in mt_gic_sync_dcm_disable()
/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/devapc/
Ddevapc.c46 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_master_domain()
60 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_master_domain_remap_infra()
66 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_master_domain_remap_infra()
71 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_master_domain_remap_infra()
75 mmio_clrsetbits_32(base, 0x1, set_bit); in set_master_domain_remap_infra()
90 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_master_domain_remap_mm()
116 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_module_apc()
/external/arm-trusted-firmware/plat/imx/imx8m/
Dgpc_common.c127 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CLK_ON_LPM, in imx_set_cluster_powerdown()
148 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, 0xf, A53_CLK_ON_LPM); in imx_set_cluster_powerdown()
152 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_AD, (L2PGE | EN_PLAT_PDN), in imx_set_cluster_powerdown()
175 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CORE_WUP_SRC(last_core), in imx_set_sys_wakeup()
178 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, IRQ_SRC_A53_WUP, in imx_set_sys_wakeup()
/external/arm-trusted-firmware/plat/allwinner/common/
Dsunxi_common.c107 mmio_clrsetbits_32(port_base + (pin / 8) * 4, in sunxi_set_gpio_out()
146 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x00, 0xffU, pin_func); in sunxi_init_platform_r_twi()
149 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x14, 0x0fU, 0xaU); in sunxi_init_platform_r_twi()
152 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x1c, 0x0fU, 0x5U); in sunxi_init_platform_r_twi()
/external/arm-trusted-firmware/plat/intel/soc/stratix10/soc/
Ds10_memory_controller.c226 mmio_clrsetbits_32( in configure_ddr_sched_ctrl_regs()
376 mmio_clrsetbits_32(S10_MPFE_HMC_ADP_DDRIOCTRL, in configure_hmc_adaptor_regs()
385 mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL1, in configure_hmc_adaptor_regs()
392 mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL2, in configure_hmc_adaptor_regs()
399 mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL1, in configure_hmc_adaptor_regs()
/external/arm-trusted-firmware/plat/intel/soc/agilex/soc/
Dagilex_memory_controller.c197 mmio_clrsetbits_32( in configure_ddr_sched_ctrl_regs()
373 mmio_clrsetbits_32(AGX_MPFE_HMC_ADP_ECCCTRL1, in configure_hmc_adaptor_regs()
380 mmio_clrsetbits_32(AGX_MPFE_HMC_ADP_ECCCTRL2, in configure_hmc_adaptor_regs()
387 mmio_clrsetbits_32(AGX_MPFE_HMC_ADP_ECCCTRL1, in configure_hmc_adaptor_regs()
/external/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/
Dspm_hotplug.c251 mmio_clrsetbits_32(SPM_PCM_RESERVE, in spm_hotplug_on()
271 mmio_clrsetbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK, in spm_hotplug_off()
Dspm.c171 mmio_clrsetbits_32(SPM_CLK_CON, CC_SRCLKENA_MASK_0, in spm_set_power_control()
294 mmio_clrsetbits_32(SPM_CLK_CON, CC_LOCK_INFRA_DCM, in spm_kick_pcm_to_run()
304 mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_WDT_EN, CON1_CFG_KEY); in spm_clean_after_wakeup()
308 mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_TIMER_EN, CON1_CFG_KEY); in spm_clean_after_wakeup()
/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/spm/
Dspm.c225 mmio_clrsetbits_32(PCM_CON1, PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); in spm_disable_pcm_timer()
256 mmio_clrsetbits_32(PCM_CON1, PCM_WDT_WAKE_MODE_LSB, in spm_set_pcm_wdt()
265 mmio_clrsetbits_32(PCM_CON1, PCM_WDT_EN_LSB, in spm_set_pcm_wdt()
349 mmio_clrsetbits_32(SPM_DVS_LEVEL, in spm_boot_init()
/external/arm-trusted-firmware/drivers/marvell/mochi/
Dcp110_setup.c322 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG, in cp110_rtc_init()
326 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG, in cp110_rtc_init()
331 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG, in cp110_rtc_init()
/external/arm-trusted-firmware/plat/imx/imx8m/imx8mq/
Dgpc.c57 mmio_clrsetbits_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 0xFFFFFFFF, in imx_pup_pdn_slot_config()
63 mmio_clrsetbits_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 0xFFFFFFFF, in imx_pup_pdn_slot_config()
/external/arm-trusted-firmware/drivers/st/clk/
Dstm32mp1_clk.c1122 mmio_clrsetbits_32(rcc_base + RCC_BDCR, in stm32mp1_lse_enable()
1190 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, in stm32mp1_set_hsidiv()
1309 mmio_clrsetbits_32(pllxcr, in stm32mp1_pll_start()
1451 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK, in stm32mp1_set_clksrc()
1470 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, in stm32mp1_set_clkdiv()
1498 mmio_clrsetbits_32(clksrc_address, in stm32mp1_mco_csg()
1501 mmio_clrsetbits_32(clksrc_address, in stm32mp1_mco_csg()
1514 mmio_clrsetbits_32(address, in stm32mp1_set_rtcsrc()
1586 mmio_clrsetbits_32(address, mask, value); in stm32mp1_pkcs_config()
1878 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR, in stm32mp1_clk_init()
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/include/
Drk3399_mcu.h22 #define mmio_clrsetbits_32(addr, clear, set) \ macro
/external/arm-trusted-firmware/drivers/st/spi/
Dstm32_qspi.c349 mmio_clrsetbits_32(qspi_base() + QSPI_CR, QSPI_CR_FSEL, cr); in stm32_qspi_claim_bus()
385 mmio_clrsetbits_32(qspi_base() + QSPI_CR, QSPI_CR_PRESCALER_MASK, in stm32_qspi_set_speed()
388 mmio_clrsetbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CSHT_MASK, csht); in stm32_qspi_set_speed()
/external/arm-trusted-firmware/include/lib/
Dmmio.h69 static inline void mmio_clrsetbits_32(uintptr_t addr, in mmio_clrsetbits_32() function
/external/arm-trusted-firmware/drivers/marvell/comphy/
Dphy-comphy-common.h150 mmio_clrsetbits_32(addr, mask, data); in reg_set()
/external/arm-trusted-firmware/drivers/st/crypto/
Dstm32_hash.c251 mmio_clrsetbits_32(hash_base() + HASH_STR, HASH_STR_NBLW_MASK, in stm32_hash_final()
/external/arm-trusted-firmware/drivers/st/fmc/
Dstm32_fmc2_nand.c334 mmio_clrsetbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_PWID_MASK, in stm32_fmc2_set_buswidth_16()
340 mmio_clrsetbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_ECCEN, in stm32_fmc2_set_ecc()
/external/arm-trusted-firmware/plat/mediatek/mt8173/
Dplat_pm.c458 mmio_clrsetbits_32(MTK_WDT_BASE, in plat_system_reset()
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/gpio/
Drk3399_gpio.c311 mmio_clrsetbits_32(gpio_port[port] + SWPORTA_DR, 1 << num, in set_value()
/external/arm-trusted-firmware/plat/intel/soc/common/drivers/qspi/
Dcadence_qspi.c35 mmio_clrsetbits_32(CAD_QSPI_OFFSET + CAD_QSPI_CFG, in cad_qspi_set_baudrate_div()
/external/arm-trusted-firmware/drivers/st/mmc/
Dstm32_sdmmc2.c511 mmio_clrsetbits_32(base + SDMMC_DCTRLR, in stm32_sdmmc2_prepare()

12