1 /*
2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdbool.h>
8
9 #include <arch.h>
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <lib/mmio.h>
13 #include <lib/psci/psci.h>
14
15 #include <gpc.h>
16 #include <imx8m_psci.h>
17 #include <plat_imx8.h>
18
19 static uint32_t gpc_imr_offset[] = { 0x30, 0x40, 0x1c0, 0x1d0, };
20
21 #pragma weak imx_set_cpu_pwr_off
22 #pragma weak imx_set_cpu_pwr_on
23 #pragma weak imx_set_cpu_lpm
24 #pragma weak imx_set_cluster_powerdown
25
imx_set_cpu_secure_entry(unsigned int core_id,uintptr_t sec_entrypoint)26 void imx_set_cpu_secure_entry(unsigned int core_id, uintptr_t sec_entrypoint)
27 {
28 uint64_t temp_base;
29
30 temp_base = (uint64_t) sec_entrypoint;
31 temp_base >>= 2;
32
33 mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3),
34 ((uint32_t)(temp_base >> 22) & 0xffff));
35 mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3) + 4,
36 ((uint32_t)temp_base & 0x003fffff));
37 }
38
imx_set_cpu_pwr_off(unsigned int core_id)39 void imx_set_cpu_pwr_off(unsigned int core_id)
40 {
41 /* enable the wfi power down of the core */
42 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id));
43 /* assert the pcg pcr bit of the core */
44 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
45 }
46
imx_set_cpu_pwr_on(unsigned int core_id)47 void imx_set_cpu_pwr_on(unsigned int core_id)
48 {
49 /* clear the wfi power down bit of the core */
50 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id));
51 /* assert the ncpuporeset */
52 mmio_clrbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id));
53 /* assert the pcg pcr bit of the core */
54 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
55 /* sw power up the core */
56 mmio_setbits_32(IMX_GPC_BASE + CPU_PGC_UP_TRG, (1 << core_id));
57
58 /* wait for the power up finished */
59 while ((mmio_read_32(IMX_GPC_BASE + CPU_PGC_UP_TRG) & (1 << core_id)) != 0)
60 ;
61
62 /* deassert the pcg pcr bit of the core */
63 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
64 /* deassert the ncpuporeset */
65 mmio_setbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id));
66 }
67
imx_set_cpu_lpm(unsigned int core_id,bool pdn)68 void imx_set_cpu_lpm(unsigned int core_id, bool pdn)
69 {
70 if (pdn) {
71 /* enable the core WFI PDN & IRQ PUP */
72 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
73 COREx_IRQ_WUP(core_id));
74 /* assert the pcg pcr bit of the core */
75 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
76 } else {
77 /* disbale CORE WFI PDN & IRQ PUP */
78 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
79 COREx_IRQ_WUP(core_id));
80 /* deassert the pcg pcr bit of the core */
81 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
82 }
83 }
84
85 /*
86 * the plat and noc can only be power up & down by slot method,
87 * slot0: plat power down; slot1: noc power down; slot2: noc power up;
88 * slot3: plat power up. plat's pup&pdn ack is used by default. if
89 * noc is config to power down, then noc's pdn ack should be used.
90 */
imx_a53_plat_slot_config(bool pdn)91 static void imx_a53_plat_slot_config(bool pdn)
92 {
93 if (pdn) {
94 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL);
95 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL);
96 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_PLAT_PDN_ACK |
97 A53_PLAT_PUP_ACK);
98 mmio_setbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1);
99 } else {
100 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL);
101 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL);
102 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_DUMMY_PUP_ACK |
103 A53_DUMMY_PDN_ACK);
104 mmio_clrbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1);
105 }
106 }
107
imx_set_cluster_standby(bool enter)108 void imx_set_cluster_standby(bool enter)
109 {
110 /*
111 * Enable BIT 6 of A53 AD register to make sure system
112 * don't enter LPM mode.
113 */
114 if (enter)
115 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6));
116 else
117 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6));
118 }
119
120 /* i.mx8mq need to override it */
imx_set_cluster_powerdown(unsigned int last_core,uint8_t power_state)121 void imx_set_cluster_powerdown(unsigned int last_core, uint8_t power_state)
122 {
123 uint32_t val;
124
125 if (!is_local_state_run(power_state)) {
126 /* config C0~1's LPM, enable a53 clock off in LPM */
127 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CLK_ON_LPM,
128 LPM_MODE(power_state));
129 /* config C2-3's LPM */
130 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, LPM_MODE(power_state));
131
132 /* enable PLAT/SCU power down */
133 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD);
134 val &= ~EN_L2_WFI_PDN;
135 /* L2 cache memory is on in WAIT mode */
136 if (is_local_state_off(power_state))
137 val |= (L2PGE | EN_PLAT_PDN);
138 else
139 val |= EN_PLAT_PDN;
140
141 mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val);
142
143 imx_a53_plat_slot_config(true);
144 } else {
145 /* clear the slot and ack for cluster power down */
146 imx_a53_plat_slot_config(false);
147 /* reverse the cluster level setting */
148 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, 0xf, A53_CLK_ON_LPM);
149 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, 0xf);
150
151 /* clear PLAT/SCU power down */
152 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_AD, (L2PGE | EN_PLAT_PDN),
153 EN_L2_WFI_PDN);
154 }
155 }
156
gicd_read_isenabler(uintptr_t base,unsigned int id)157 static unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id)
158 {
159 unsigned int n = id >> ISENABLER_SHIFT;
160
161 return mmio_read_32(base + GICD_ISENABLER + (n << 2));
162 }
163
164 /*
165 * gic's clock will be gated in system suspend, so gic has no ability to
166 * to wakeup the system, we need to config the imr based on the irq
167 * enable status in gic, then gpc will monitor the wakeup irq
168 */
imx_set_sys_wakeup(unsigned int last_core,bool pdn)169 void imx_set_sys_wakeup(unsigned int last_core, bool pdn)
170 {
171 uint32_t irq_mask;
172 uintptr_t gicd_base = PLAT_GICD_BASE;
173
174 if (pdn)
175 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CORE_WUP_SRC(last_core),
176 IRQ_SRC_A53_WUP);
177 else
178 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, IRQ_SRC_A53_WUP,
179 A53_CORE_WUP_SRC(last_core));
180
181 /* clear last core's IMR based on GIC's mask setting */
182 for (int i = 0; i < IRQ_IMR_NUM; i++) {
183 if (pdn)
184 /* set the wakeup irq base GIC */
185 irq_mask = ~gicd_read_isenabler(gicd_base, 32 * (i + 1));
186 else
187 irq_mask = IMR_MASK_ALL;
188
189 mmio_write_32(IMX_GPC_BASE + gpc_imr_offset[last_core] + i * 4,
190 irq_mask);
191 }
192 }
193
194 #pragma weak imx_noc_slot_config
195 /*
196 * this function only need to be override by platform
197 * that support noc power down, for example: imx8mm.
198 * otherwize, keep it empty.
199 */
imx_noc_slot_config(bool pdn)200 void imx_noc_slot_config(bool pdn)
201 {
202
203 }
204
205 /* this is common for all imx8m soc */
imx_set_sys_lpm(unsigned int last_core,bool retention)206 void imx_set_sys_lpm(unsigned int last_core, bool retention)
207 {
208 uint32_t val;
209
210 val = mmio_read_32(IMX_GPC_BASE + SLPCR);
211 val &= ~(SLPCR_EN_DSM | SLPCR_VSTBY | SLPCR_SBYOS |
212 SLPCR_BYPASS_PMIC_READY | SLPCR_A53_FASTWUP_STOP_MODE);
213
214 if (retention)
215 val |= (SLPCR_EN_DSM | SLPCR_VSTBY | SLPCR_SBYOS |
216 SLPCR_BYPASS_PMIC_READY | SLPCR_A53_FASTWUP_STOP_MODE);
217
218 mmio_write_32(IMX_GPC_BASE + SLPCR, val);
219
220 /* config the noc power down */
221 imx_noc_slot_config(retention);
222
223 /* config wakeup irqs' mask in gpc */
224 imx_set_sys_wakeup(last_core, retention);
225 }
226
imx_set_rbc_count(void)227 void imx_set_rbc_count(void)
228 {
229 mmio_setbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN |
230 (0x8 << SLPCR_RBC_COUNT_SHIFT));
231 }
232
imx_clear_rbc_count(void)233 void imx_clear_rbc_count(void)
234 {
235 mmio_clrbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN |
236 (0x3f << SLPCR_RBC_COUNT_SHIFT));
237 }
238