| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | mtvsrdd.ll | 4 ; This test case checks r0 is used as constant 0 in instruction mtvsrdd.
11 ; CHECK: mtvsrdd v2, 0, r3
21 ; CHECK: mtvsrdd v2, {{r[0-9]+}}, {{r[0-9]+}}
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| D | f128-aggregates.ll | 199 ; CHECK-NEXT: mtvsrdd v2, r8, r7
203 ; CHECK-BE: mtvsrdd v2, r8, r7
215 ; CHECK-NEXT: mtvsrdd v2, r6, r5
219 ; CHECK-BE: mtvsrdd v2, r6, r5
232 ; CHECK-DAG: mtvsrdd v3, r6, r5
292 ; CHECK-NEXT: mtvsrdd v2, r4, r3
296 ; CHECK-BE: mtvsrdd v2, r4, r3
308 ; CHECK-NEXT: mtvsrdd v2, r4, r3
312 ; CHECK-BE: mtvsrdd v2, r4, r3
324 ; CHECK-NEXT: mtvsrdd v2, r8, r7
[all …]
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| D | bswap64.ll | 5 ; CHECK: mtvsrdd
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| D | build-vector-tests.ll | 68 ;// P9: 2 x mtvsrdd, vmrgow //
98 ;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow //
103 ;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow //
239 ;// P9: 2 x mtvsrdd, vmrgow //
272 ;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow //
277 ;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow //
419 ;// P9: mtvsrdd //
449 ;// P9: 2 x ld, mtvsrdd //
454 ;// P9: sldi 3, add, 2 x ld, mtvsrdd //
459 ;// P9: mtvsrdd //
[all …]
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| D | power9-moves-and-splats.ll | 12 ; CHECK-NEXT: mtvsrdd v2, r4, r3
17 ; CHECK-BE-NEXT: mtvsrdd v2, r3, r4
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| D | ppc64-i128-abi.ll | 65 ; FIXME: mtvsrdd [[V1:v[0-9]+]], [[R2]], [[R1]]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-p9vector.txt | 3 # CHECK: mtvsrdd 6, 0, 3
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| D | vsx.txt | 851 # CHECK: mtvsrdd 34, 3, 12
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/ |
| D | vsx.s | 944 # CHECK-BE: mtvsrdd 34, 3, 12 # encoding: [0x7c,0x43,0x63,0x67]
945 # CHECK-LE: mtvsrdd 34, 3, 12 # encoding: [0x67,0x63,0x43,0x7c]
946 mtvsrdd 34, 3, 12
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| /external/llvm/test/MC/PowerPC/ |
| D | vsx.s | 958 # CHECK-BE: mtvsrdd 34, 3, 12 # encoding: [0x7c,0x43,0x63,0x67]
959 # CHECK-LE: mtvsrdd 34, 3, 12 # encoding: [0x67,0x63,0x43,0x7c]
960 mtvsrdd 34, 3, 12
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| /external/llvm/test/MC/Disassembler/PowerPC/ |
| D | vsx.txt | 866 # CHECK: mtvsrdd 34, 3, 12
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| /external/llvm/lib/Target/PowerPC/ |
| D | p9-instrs.txt | 153 [PO T RA RB XO TX] mtvsrdd XT,RA,RB
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| D | PPCInstrVSX.td | 1268 "mtvsrdd $XT, $rA, $rB", IIC_VecGeneral,
|
| /external/v8/src/codegen/ppc/ |
| D | assembler-ppc.h | 1022 void mtvsrdd(const Simd128Register rt, const Register ra, const Register rb);
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| D | constants-ppc.h | 418 V(mtvsrdd, MTVSRDD, 0x7C000366) \
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| D | assembler-ppc.cc | 1789 void Assembler::mtvsrdd(const Simd128Register rt, const Register ra, in mtvsrdd() function in v8::internal::Assembler
|
| /external/v8/src/compiler/backend/ppc/ |
| D | code-generator-ppc.cc | 3407 __ mtvsrdd(kScratchDoubleReg, temp, ip); in AssembleArchInstruction() local
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenAsmMatcher.inc | 4274 "mttcr\010mtvrsave\006mtvscr\006mtvsrd\007mtvsrdd\007mtvsrwa\007mtvsrws\007"
5983 …{ 7635 /* mtvsrdd */, PPC::MTVSRDD, Convert__RegVSRC1_0__RegG8RCNoX01_1__RegG8RC1_2, 0, { MCK_RegV…
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrVSX.td | 1530 "mtvsrdd $XT, $rA, $rB", IIC_VecGeneral,
|