| /external/arm-trusted-firmware/bl1/aarch32/ |
| D | bl1_context_mgmt.c | 74 next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0); in copy_cpu_ctx_to_smc_ctx()
75 next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1); in copy_cpu_ctx_to_smc_ctx()
76 next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2); in copy_cpu_ctx_to_smc_ctx()
77 next_smc_ctx->r3 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R3); in copy_cpu_ctx_to_smc_ctx()
78 next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR); in copy_cpu_ctx_to_smc_ctx()
79 next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR); in copy_cpu_ctx_to_smc_ctx()
80 next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR); in copy_cpu_ctx_to_smc_ctx()
154 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR); in bl1_prepare_next_image()
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| /external/arm-trusted-firmware/bl32/sp_min/ |
| D | sp_min_main.c | 112 next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0); in copy_cpu_ctx_to_smc_stx()
113 next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1); in copy_cpu_ctx_to_smc_stx()
114 next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2); in copy_cpu_ctx_to_smc_stx()
115 next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR); in copy_cpu_ctx_to_smc_stx()
116 next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR); in copy_cpu_ctx_to_smc_stx()
117 next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR); in copy_cpu_ctx_to_smc_stx()
148 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR); in sp_min_prepare_next_image_entry()
227 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR); in sp_min_warm_boot()
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| /external/arm-trusted-firmware/include/arch/aarch64/ |
| D | smccc_helpers.h | 60 read_ctx_reg((get_gpregs_ctx(_h)), (_g))
69 read_ctx_reg((get_el3state_ctx(_h)), (_e))
79 _x1 = read_ctx_reg(regs, CTX_GPREG_X1); \
80 _x2 = read_ctx_reg(regs, CTX_GPREG_X2); \
81 _x3 = read_ctx_reg(regs, CTX_GPREG_X3); \
82 _x4 = read_ctx_reg(regs, CTX_GPREG_X4); \
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| /external/arm-trusted-firmware/plat/nvidia/tegra/common/ |
| D | tegra_fiq_glue.c | 78 fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3)); in tegra_fiq_interrupt_handler()
79 fiq_state[cpu].spsr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_SPSR_EL3)); in tegra_fiq_interrupt_handler()
169 val = read_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_SP_EL0)); in tegra_fiq_get_intr_context()
172 val = read_ctx_reg((el1state_ctx), (uint32_t)(CTX_SP_EL1)); in tegra_fiq_get_intr_context()
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| /external/arm-trusted-firmware/services/spd/opteed/ |
| D | opteed_main.c | 251 read_ctx_reg(get_gpregs_ctx(handle), in opteed_smc_handler()
255 read_ctx_reg(get_gpregs_ctx(handle), in opteed_smc_handler()
259 read_ctx_reg(get_gpregs_ctx(handle), in opteed_smc_handler()
264 read_ctx_reg(get_gpregs_ctx(handle), in opteed_smc_handler()
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| /external/arm-trusted-firmware/plat/rockchip/rk3399/ |
| D | plat_sip_calls.c | 70 x5 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X5); in rockchip_plat_sip_handler()
71 x6 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X6); in rockchip_plat_sip_handler()
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| /external/arm-trusted-firmware/lib/el3_runtime/aarch64/ |
| D | context_mgmt.c | 337 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), in cm_prepare_el3_exit()
341 sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx), in cm_prepare_el3_exit()
637 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); in cm_write_scr_el3_bit()
657 return read_ctx_reg(state, CTX_SCR_EL3); in cm_get_scr_el3()
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| /external/arm-trusted-firmware/plat/arm/common/aarch64/ |
| D | execution_state_switch.c | 62 spsr = read_ctx_reg(el3_ctx, CTX_SPSR_EL3); in arm_execution_state_switch()
96 scr = read_ctx_reg(el3_ctx, CTX_SCR_EL3); in arm_execution_state_switch()
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| /external/arm-trusted-firmware/lib/el3_runtime/aarch32/ |
| D | context_mgmt.c | 186 scr = read_ctx_reg(get_regs_ctx(ctx), CTX_SCR); in cm_prepare_el3_exit()
189 hsctlr = read_ctx_reg(get_regs_ctx(ctx), in cm_prepare_el3_exit()
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| /external/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/drivers/mce/ |
| D | mce.c | 183 arg3 = read_ctx_reg(gp_regs, CTX_GPREG_X4); in mce_command_handler()
184 arg4 = read_ctx_reg(gp_regs, CTX_GPREG_X5); in mce_command_handler()
185 arg5 = read_ctx_reg(gp_regs, CTX_GPREG_X6); in mce_command_handler()
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| /external/arm-trusted-firmware/include/lib/el3_runtime/aarch32/ |
| D | context.h | 50 #define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> WORD_SHIFT]) macro
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| /external/arm-trusted-firmware/services/std_svc/sdei/ |
| D | sdei_intr_mgmt.c | 172 disp_ctx->spsr_el3 = read_ctx_reg(tgt_el3, CTX_SPSR_EL3); in save_event_ctx()
173 disp_ctx->elr_el3 = read_ctx_reg(tgt_el3, CTX_ELR_EL3); in save_event_ctx()
274 disp_ctx->disable_cve_2018_3639 = read_ctx_reg(tgt_cve_2018_3639, in setup_ns_dispatch()
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| D | sdei_private.h | 169 return ((read_ctx_reg(el3_ctx, CTX_SCR_EL3) & SCR_HCE_BIT) != 0U) ? in sdei_client_el()
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| /external/arm-trusted-firmware/services/spd/trusty/ |
| D | trusty.c | 153 ctx->fiq_sp_el1 = read_ctx_reg(get_sysregs_ctx(handle), CTX_SP_EL1); in trusty_fiq_handler()
182 uint64_t sp_el0 = read_ctx_reg(&ctx->fiq_gpregs, CTX_GPREG_SP_EL0); in trusty_get_fiq_regs()
292 uint64_t reg_width = GET_RW(read_ctx_reg(get_el3state_ctx(&ctx->cpu_ctx), in trusty_init()
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| /external/arm-trusted-firmware/services/std_svc/spm_mm/ |
| D | spm_mm_setup.c | 129 u_register_t sctlr_el1 = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1); in spm_sp_setup()
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| /external/arm-trusted-firmware/include/lib/el3_runtime/aarch64/ |
| D | context.h | 291 #define read_ctx_reg(ctx, offset) ((ctx)->_regs[(offset) >> DWORD_SHIFT]) macro
|