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Searched refs:reg_data (Results 1 – 25 of 38) sorted by relevance

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/external/u-boot/drivers/phy/marvell/
Dcomphy_core.h98 u32 reg_data; in reg_set_silent() local
100 reg_data = readl(addr); in reg_set_silent()
101 reg_data &= ~mask; in reg_set_silent()
102 reg_data |= data; in reg_set_silent()
103 writel(reg_data, addr); in reg_set_silent()
117 u16 reg_data; in reg_set_silent16() local
119 reg_data = readw(addr); in reg_set_silent16()
120 reg_data &= ~mask; in reg_set_silent16()
121 reg_data |= data; in reg_set_silent16()
122 writew(reg_data, addr); in reg_set_silent16()
/external/u-boot/arch/arm/mach-mvebu/serdes/a38x/
Dseq_exec.c32 u32 unit_base_reg, unit_offset, data, mask, reg_data, reg_addr; in write_op_execute() local
54 reg_data = reg_read(reg_addr); in write_op_execute()
55 reg_data &= (~mask); in write_op_execute()
59 reg_data |= data; in write_op_execute()
60 reg_write(reg_addr, reg_data); in write_op_execute()
63 printf(" - 0x%x\n", reg_data); in write_op_execute()
87 u32 reg_addr, reg_data; in poll_op_execute() local
113 reg_data = reg_read(reg_addr) & mask; in poll_op_execute()
116 } while ((reg_data != data) && (poll_counter < num_of_loops)); in poll_op_execute()
118 if ((poll_counter >= num_of_loops) && (reg_data != data)) { in poll_op_execute()
Dhigh_speed_env_spec.c1564 u32 reg_data; in serdes_pex_usb3_pipe_delay_w_a() local
1568 reg_data = reg_read(GENERAL_PURPOSE_RESERVED0_REG); in serdes_pex_usb3_pipe_delay_w_a()
1578 reg_data |= 1 << (7 + (serdes_num - 3)); in serdes_pex_usb3_pipe_delay_w_a()
1581 reg_data &= ~(1 << (7 + (serdes_num - 3))); in serdes_pex_usb3_pipe_delay_w_a()
1583 reg_write(GENERAL_PURPOSE_RESERVED0_REG, reg_data); in serdes_pex_usb3_pipe_delay_w_a()
1682 u32 reg_data; in serdes_power_up_ctrl() local
1724 reg_data = reg_read(SOC_CONTROL_REG1); in serdes_power_up_ctrl()
1726 reg_data |= 0x4000; in serdes_power_up_ctrl()
1728 reg_data &= ~0x4000; in serdes_power_up_ctrl()
1729 reg_write(SOC_CONTROL_REG1, reg_data); in serdes_power_up_ctrl()
[all …]
/external/u-boot/drivers/net/pfe_eth/
Dpfe_mdio.c22 u32 reg_data; in pfe_write_addr() local
28 reg_data = (EMAC_MII_DATA_TA | phy | devadr | reg_addr); in pfe_write_addr()
30 writel(reg_data, reg_base + EMAC_MII_DATA_REG); in pfe_write_addr()
56 u32 reg_data; in pfe_phy_read() local
72 reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD | in pfe_phy_read()
75 reg_data = (EMAC_MII_DATA_OP_CL45_RD | EMAC_MII_DATA_TA | in pfe_phy_read()
78 writel(reg_data, reg_base + EMAC_MII_DATA_REG); in pfe_phy_read()
111 u32 reg_data; in pfe_phy_write() local
126 reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR | in pfe_phy_write()
129 reg_data = (EMAC_MII_DATA_OP_CL45_WR | EMAC_MII_DATA_TA | in pfe_phy_write()
[all …]
/external/u-boot/drivers/gpio/
Dbcm6345_gpio.c18 void __iomem *reg_data; member
25 return !!(readl(priv->reg_data) & BIT(offset)); in bcm6345_gpio_get_value()
34 setbits_32(priv->reg_data, BIT(offset)); in bcm6345_gpio_set_value()
36 clrbits_32(priv->reg_data, BIT(offset)); in bcm6345_gpio_set_value()
96 priv->reg_data = dev_remap_addr_index(dev, 1); in bcm6345_gpio_probe()
97 if (!priv->reg_data) in bcm6345_gpio_probe()
/external/arm-trusted-firmware/drivers/renesas/rcar/ddr/
Ddram_sub_func.c39 uint32_t reg_data; in rcar_dram_get_boot_status() local
56 reg_data = mmio_read_32(gpio); in rcar_dram_get_boot_status()
57 if (reg_data & BIT(shift)) in rcar_dram_get_boot_status()
70 uint32_t reg_data; in rcar_dram_update_boot_status() local
137 reg_data = mmio_read_32(gpio); in rcar_dram_update_boot_status()
138 if (!(reg_data & BIT(trg))) in rcar_dram_update_boot_status()
/external/arm-trusted-firmware/drivers/marvell/
Dmci.c345 uint32_t reg_data, ret = 1; in mci_axi_set_pcie_mode() local
376 reg_data = mci_mmio_read_32( in mci_axi_set_pcie_mode()
378 if (reg_data & MCI_HB_CTRL_TX_CTRL_PCIE_MODE) in mci_axi_set_pcie_mode()
390 uint32_t reg_data, ret = 0; in mci_axi_set_fifo_thresh() local
401 reg_data = MCI_PHY_CTRL_PIDI_MODE | in mci_axi_set_fifo_thresh()
406 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), reg_data); in mci_axi_set_fifo_thresh()
423 reg_data = MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE | in mci_axi_set_fifo_thresh()
427 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), reg_data); in mci_axi_set_fifo_thresh()
434 reg_data = MCI_PHY_CTRL_PIDI_MODE | in mci_axi_set_fifo_thresh()
438 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), reg_data); in mci_axi_set_fifo_thresh()
[all …]
/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_debug.c514 u32 reg_data; in ddr3_tip_print_stability_log() local
572 csindex, &reg_data); in ddr3_tip_print_stability_log()
573 printf("%d,%d,", (reg_data & 0x1f), in ddr3_tip_print_stability_log()
574 ((reg_data & 0x3e0) >> 5)); in ddr3_tip_print_stability_log()
580 &reg_data); in ddr3_tip_print_stability_log()
582 (reg_data & 0x1f) + in ddr3_tip_print_stability_log()
583 ((reg_data & 0x1c0) >> 6) * 32, in ddr3_tip_print_stability_log()
584 (reg_data & 0x1f), in ddr3_tip_print_stability_log()
585 (reg_data & 0x1c0) >> 6); in ddr3_tip_print_stability_log()
600 &reg_data); in ddr3_tip_print_stability_log()
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Dddr3_training_ip_engine.c349 reg_data, pup_id; in ddr3_tip_ip_training() local
411 reg_data = (direction == OPER_READ) ? 0 : (0x3 << 30); in ddr3_tip_ip_training()
412 reg_data |= (direction == OPER_READ) ? 0x60 : 0xfa; in ddr3_tip_ip_training()
415 ODPG_WR_RD_MODE_ENA_REG, reg_data, in ddr3_tip_ip_training()
417 reg_data = (edge_comp == EDGE_PF || edge_comp == EDGE_FP) ? 0 : 1 << 6; in ddr3_tip_ip_training()
418 reg_data |= (edge_comp == EDGE_PF || edge_comp == EDGE_PFP) ? in ddr3_tip_ip_training()
423 reg_data |= 0xe << 14; in ddr3_tip_ip_training()
425 reg_data |= pup_num << 14; in ddr3_tip_ip_training()
429 reg_data |= (0 << 20); in ddr3_tip_ip_training()
431 reg_data |= (0 << 20); in ddr3_tip_ip_training()
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Dddr3_training_leveling.c807 u32 reg_data = 0, temp = 0, iter, if_id, bus_cnt; in ddr3_tip_dynamic_write_leveling() local
917 reg_data = data_read[0]; in ddr3_tip_dynamic_write_leveling()
920 reg_data = 0; in ddr3_tip_dynamic_write_leveling()
922 if (reg_data != PASS) in ddr3_tip_dynamic_write_leveling()
932 reg_data = data_read[0]; in ddr3_tip_dynamic_write_leveling()
934 0, bus_cnt, reg_data)); in ddr3_tip_dynamic_write_leveling()
935 if ((reg_data & (1 << 25)) == 0) in ddr3_tip_dynamic_write_leveling()
959 reg_data = wl_values[effective_cs][bus_cnt][if_id] + 16; in ddr3_tip_dynamic_write_leveling()
964 reg_data = (reg_data & 0x1f) | in ddr3_tip_dynamic_write_leveling()
965 (((reg_data & 0xe0) >> 5) << 6) | in ddr3_tip_dynamic_write_leveling()
[all …]
Dddr3_training_ip_def.h154 struct reg_data { struct
156 unsigned int reg_data; argument
Dddr3_training_hw_algo.c116 u32 reg_data; in get_valid_win_rx() local
129 &reg_data)); in get_valid_win_rx()
130 res[i] = (reg_data >> RESULT_PHY_RX_OFFS) & 0x1f; in get_valid_win_rx()
Dmv_ddr_plat.h216 u32 reg_data; member
/external/u-boot/arch/arm/mach-omap2/
Dvc.c94 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data) in omap_vc_bypass_send_value() argument
105 reg_data &= PRM_VC_VAL_BYPASS_DATA_MASK; in omap_vc_bypass_send_value()
110 reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT; in omap_vc_bypass_send_value()
/external/u-boot/drivers/net/
De1000.c1352 uint32_t reg_data = 0; in e1000_read_mac_addr_from_regs() local
1362 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0); in e1000_read_mac_addr_from_regs()
1364 reg_data >>= 16; in e1000_read_mac_addr_from_regs()
1366 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1); in e1000_read_mac_addr_from_regs()
1367 tmp = reg_data & 0xffff; in e1000_read_mac_addr_from_regs()
1853 uint32_t reg_data; in e1000_init_hw() local
1861 reg_data = E1000_READ_REG(hw, STATUS); in e1000_init_hw()
1862 reg_data &= ~0x80000000; in e1000_init_hw()
1863 E1000_WRITE_REG(hw, STATUS, reg_data); in e1000_init_hw()
2003 reg_data = E1000_READ_REG(hw, TCTL); in e1000_init_hw()
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Dks8851_mll.c189 u16 reg_data = 0; in ks_read_config() local
192 reg_data = ks_rdreg8(dev, KS_CCR) & 0x00FF; in ks_read_config()
193 reg_data |= ks_rdreg8(dev, KS_CCR + 1) << 8; in ks_read_config()
196 ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED; in ks_read_config()
202 if (reg_data & CCR_8BIT) { in ks_read_config()
205 } else if (reg_data & CCR_16BIT) { in ks_read_config()
Dmvgbe.c202 u32 reg_data; in stop_queue() local
204 reg_data = readl(qreg); in stop_queue()
206 if (reg_data & 0xFF) { in stop_queue()
208 writel((reg_data << 8), qreg); in stop_queue()
216 reg_data = readl(qreg); in stop_queue()
218 while (reg_data & 0xFF); in stop_queue()
/external/u-boot/drivers/sound/
Dwm8994.c292 unsigned short reg_data; in wm8994_hw_params() local
383 if (wm8994_i2c_read(priv, aif1_reg, &reg_data) != 0) { in wm8994_hw_params()
388 if ((channels == 1) && ((reg_data & 0x18) == 0x18)) in wm8994_hw_params()
654 unsigned short reg_data; in wm8994_device_init() local
659 ret = wm8994_i2c_read(priv, WM8994_SOFTWARE_RESET, &reg_data); in wm8994_device_init()
665 if (reg_data == WM8994_ID) { in wm8994_device_init()
674 ret = wm8994_i2c_read(priv, WM8994_CHIP_REVISION, &reg_data); in wm8994_device_init()
679 priv->revision = reg_data; in wm8994_device_init()
/external/u-boot/drivers/net/phy/
Dcortina.c129 char reg_data[0x50] = {0}; in cs4340_upload_firmware() local
215 memcpy(reg_data, &line_temp[i], column_cnt - i); in cs4340_upload_firmware()
217 strim(reg_data); in cs4340_upload_firmware()
219 fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) & in cs4340_upload_firmware()
/external/arm-trusted-firmware/drivers/renesas/rcar/iic_dvfs/
Diic_dvfs.c279 IIC_DVFS_FUNC(write_data, DVFS_STATE_T *state, uint32_t *err, uint8_t reg_data) in IIC_DVFS_FUNC() argument
292 mmio_write_8(IIC_DVFS_REG_ICDR, reg_data); in IIC_DVFS_FUNC()
467 IIC_DVFS_FUNC(read, DVFS_STATE_T *state, uint8_t *reg_data) in IIC_DVFS_FUNC() argument
478 *reg_data = mmio_read_8(IIC_DVFS_REG_ICDR); in IIC_DVFS_FUNC()
484 RCAR_DVFS_API(send, uint8_t slave, uint8_t reg_addr, uint8_t reg_data) in RCAR_DVFS_API() argument
504 result = dvfs_write_data(&state, &err, reg_data); in RCAR_DVFS_API()
/external/perfetto/src/profiling/memory/
Dunwinding_unittest.cc76 char reg_data[kMaxRegisterDataSize] = {}; in AssertFunctionOffset() local
77 unwindstack::AsmGetRegs(reg_data); in AssertFunctionOffset()
78 auto regs = CreateRegsFromRawData(unwindstack::Regs::CurrentArch(), reg_data); in AssertFunctionOffset()
/external/u-boot/drivers/power/pmic/
Drk8xx.c13 static struct reg_data rk817_init_reg[] = {
86 struct reg_data *init_data = NULL; in rk8xx_probe()
/external/v8/src/compiler/backend/
Dmid-tier-register-allocator.cc900 Register& reg_data(RegisterIndex reg);
1107 return reg_data(reg).virtual_register(); in VirtualRegisterForRegister()
1115 return reg_data(reg).is_phi_gap_move(); in IsPhiGapMove()
1123 reg_data(reg).Commit(allocated, data); in Commit()
1132 reg_data(reg).Spill(allocated, current_block, data); in Spill()
1141 reg_data(reg).SpillForDeferred(allocated, instr_index, data); in SpillForDeferred()
1149 reg_data(reg).MoveToSpillSlotOnDeferred(virtual_register, instr_index, data); in MoveToSpillSlotOnDeferred()
1156 reg_data(reg).Use(virtual_register, instr_index); in AllocateUse()
1163 reg_data(reg).PendingUse(operand, virtual_register, instr_index); in AllocatePendingUse()
1168 reg_data(reg).MarkAsPhiMove(); in UseForPhiGapMove()
[all …]
/external/u-boot/arch/arm/include/asm/arch-omap4/
Dsys_proto.h64 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
/external/u-boot/arch/arm/include/asm/arch-omap5/
Dsys_proto.h71 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);

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