1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright (C) 2015-2016 Marvell International Ltd.
4 */
5
6 #ifndef _COMPHY_CORE_H_
7 #define _COMPHY_CORE_H_
8
9 #include <fdtdec.h>
10 #include <mvebu/comphy.h>
11
12 #if defined(DEBUG)
13 #define debug_enter() printf("----> Enter %s\n", __func__);
14 #define debug_exit() printf("<---- Exit %s\n", __func__);
15 #else
16 #define debug_enter()
17 #define debug_exit()
18 #endif
19
20 /* COMPHY registers */
21 #define COMMON_PHY_CFG1_REG 0x0
22 #define COMMON_PHY_CFG1_PWR_UP_OFFSET 1
23 #define COMMON_PHY_CFG1_PWR_UP_MASK \
24 (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET)
25 #define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2
26 #define COMMON_PHY_CFG1_PIPE_SELECT_MASK \
27 (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET)
28 #define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 13
29 #define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \
30 (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET)
31 #define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14
32 #define COMMON_PHY_CFG1_CORE_RSTN_MASK \
33 (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
34 #define COMMON_PHY_PHY_MODE_OFFSET 15
35 #define COMMON_PHY_PHY_MODE_MASK \
36 (0x1 << COMMON_PHY_PHY_MODE_OFFSET)
37
38 #define COMMON_PHY_CFG6_REG 0x14
39 #define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18
40 #define COMMON_PHY_CFG6_IF_40_SEL_MASK \
41 (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
42
43 #define COMMON_SELECTOR_PHY_OFFSET 0x140
44 #define COMMON_SELECTOR_PIPE_OFFSET 0x144
45
46 #define COMMON_PHY_SD_CTRL1 0x148
47 #define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0
48 #define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF
49 #define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24
50 #define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \
51 (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
52 #define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25
53 #define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \
54 (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
55 #define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26
56 #define COMMON_PHY_SD_CTRL1_RXAUI1_MASK \
57 (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
58 #define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27
59 #define COMMON_PHY_SD_CTRL1_RXAUI0_MASK \
60 (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
61
62 /* ToDo: Get this address via DT */
63 #define MVEBU_CP0_REGS_BASE 0xF2000000UL
64
65 #define DFX_DEV_GEN_CTRL12 (MVEBU_CP0_REGS_BASE + 0x400280)
66 #define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7
67 #define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \
68 (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET)
69
70 #define MAX_LANE_OPTIONS 10
71 #define MAX_UTMI_PHY_COUNT 3
72
73 struct comphy_mux_options {
74 u32 type;
75 u32 mux_value;
76 };
77
78 struct comphy_mux_data {
79 u32 max_lane_values;
80 struct comphy_mux_options mux_values[MAX_LANE_OPTIONS];
81 };
82
83 struct chip_serdes_phy_config {
84 struct comphy_mux_data *mux_data;
85 int (*ptr_comphy_chip_init)(struct chip_serdes_phy_config *,
86 struct comphy_map *);
87 void __iomem *comphy_base_addr;
88 void __iomem *hpipe3_base_addr;
89 u32 comphy_lanes_count;
90 u32 comphy_mux_bitcount;
91 const fdt32_t *comphy_mux_lane_order;
92 u32 cp_index;
93 };
94
95 /* Register helper functions */
reg_set_silent(void __iomem * addr,u32 data,u32 mask)96 static inline void reg_set_silent(void __iomem *addr, u32 data, u32 mask)
97 {
98 u32 reg_data;
99
100 reg_data = readl(addr);
101 reg_data &= ~mask;
102 reg_data |= data;
103 writel(reg_data, addr);
104 }
105
reg_set(void __iomem * addr,u32 data,u32 mask)106 static inline void reg_set(void __iomem *addr, u32 data, u32 mask)
107 {
108 debug("Write to address = %#010lx, data = %#010x (mask = %#010x) - ",
109 (unsigned long)addr, data, mask);
110 debug("old value = %#010x ==> ", readl(addr));
111 reg_set_silent(addr, data, mask);
112 debug("new value %#010x\n", readl(addr));
113 }
114
reg_set_silent16(void __iomem * addr,u16 data,u16 mask)115 static inline void reg_set_silent16(void __iomem *addr, u16 data, u16 mask)
116 {
117 u16 reg_data;
118
119 reg_data = readw(addr);
120 reg_data &= ~mask;
121 reg_data |= data;
122 writew(reg_data, addr);
123 }
124
reg_set16(void __iomem * addr,u16 data,u16 mask)125 static inline void reg_set16(void __iomem *addr, u16 data, u16 mask)
126 {
127 debug("Write to address = %#010lx, data = %#06x (mask = %#06x) - ",
128 (unsigned long)addr, data, mask);
129 debug("old value = %#06x ==> ", readw(addr));
130 reg_set_silent16(addr, data, mask);
131 debug("new value %#06x\n", readw(addr));
132 }
133
134 /* SoC specific init functions */
135 #ifdef CONFIG_ARMADA_3700
136 int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
137 struct comphy_map *serdes_map);
138 #else
comphy_a3700_init(struct chip_serdes_phy_config * ptr_chip_cfg,struct comphy_map * serdes_map)139 static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
140 struct comphy_map *serdes_map)
141 {
142 /*
143 * This function should never be called in this configuration, so
144 * lets return an error here.
145 */
146 return -1;
147 }
148 #endif
149
150 #ifdef CONFIG_ARMADA_8K
151 int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
152 struct comphy_map *serdes_map);
153 #else
comphy_cp110_init(struct chip_serdes_phy_config * ptr_chip_cfg,struct comphy_map * serdes_map)154 static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
155 struct comphy_map *serdes_map)
156 {
157 /*
158 * This function should never be called in this configuration, so
159 * lets return an error here.
160 */
161 return -1;
162 }
163 #endif
164
165 void comphy_dedicated_phys_init(void);
166
167 /* MUX function */
168 void comphy_mux_init(struct chip_serdes_phy_config *ptr_chip_cfg,
169 struct comphy_map *comphy_map_data,
170 void __iomem *selector_base);
171
172 void comphy_pcie_config_set(u32 comphy_max_count,
173 struct comphy_map *serdes_map);
174 void comphy_pcie_config_detect(u32 comphy_max_count,
175 struct comphy_map *serdes_map);
176 void comphy_pcie_unit_general_config(u32 pex_index);
177
178 #endif /* _COMPHY_CORE_H_ */
179
180