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Searched refs:reg_set (Results 1 – 15 of 15) sorted by relevance

/external/u-boot/drivers/phy/marvell/
Dcomphy_cp110.c114 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, in comphy_pcie_power_up()
118 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, in comphy_pcie_power_up()
130 reg_set((void __iomem *)DFX_DEV_GEN_CTRL12, in comphy_pcie_power_up()
147 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_pcie_power_up()
154 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_pcie_power_up()
172 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in comphy_pcie_power_up()
182 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask); in comphy_pcie_power_up()
198 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask); in comphy_pcie_power_up()
200 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG, in comphy_pcie_power_up()
204 reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG, in comphy_pcie_power_up()
[all …]
Dcomphy_a3700.c205 reg_set(PCIE_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF); in comphy_pcie_power_up()
265 reg_set(rh_vsreg_addr, reg, 0xFFFFFFFF); in reg_set_indirect()
266 reg_set(rh_vsreg_data, data, mask); in reg_set_indirect()
314 reg_set(rh_vs0_a, vsata_ctrl_reg, 0xFFFFFFFF); in comphy_sata_power_up()
315 reg_set(rh_vs0_d, bs_phy_pu_pll, bs_phy_pu_pll); in comphy_sata_power_up()
321 reg_set(rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF); in comphy_sata_power_up()
370 reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); in comphy_usb3_power_up()
376 reg_set(USB3_CTRPUL_VAL_REG, 0x8 << 24, rb_usb3_ctr_100ns); in comphy_usb3_power_up()
486 reg_set(rh_vsreg_addr, in comphy_usb3_power_up()
516 reg_set(USB32_CTRL_BASE, in comphy_usb3_power_up()
[all …]
Dcomphy_mux.c106 reg_set(selector_base, value, mask); in comphy_mux_reg_write()
Dcomphy_core.h106 static inline void reg_set(void __iomem *addr, u32 data, u32 mask) in reg_set() function
/external/arm-trusted-firmware/drivers/marvell/comphy/
Dphy-comphy-cp110.c361 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
364 reg_set(comphy_addr + COMMON_PHY_CFG6_REG, in mvebu_cp110_comphy_sata_power_on()
373 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
381 reg_set(hpipe_addr + HPIPE_MISC_REG, in mvebu_cp110_comphy_sata_power_on()
390 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
392 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, in mvebu_cp110_comphy_sata_power_on()
396 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, in mvebu_cp110_comphy_sata_power_on()
415 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
427 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
444 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
[all …]
Dphy-comphy-3700.c258 reg_set(addr + COMPHY_LANE2_INDIR_DATA_OFFSET, data, mask); in comphy_set_indirect()
411 reg_set(offset, data, mask); in mvebu_a3700_comphy_sgmii_power_on()
416 reg_set(offset, data, mask); in mvebu_a3700_comphy_sgmii_power_on()
437 reg_set(offset, data, mask); in mvebu_a3700_comphy_sgmii_power_on()
536 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), in mvebu_a3700_comphy_sgmii_power_on()
555 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), in mvebu_a3700_comphy_sgmii_power_on()
565 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index), in mvebu_a3700_comphy_sgmii_power_on()
599 reg_set(offset, data, mask); in mvebu_a3700_comphy_sgmii_power_off()
Dphy-comphy-common.h145 static inline void reg_set(uintptr_t addr, uint32_t data, uint32_t mask) in reg_set() function
/external/u-boot/drivers/gpio/
Dmxs_gpio.c73 writel(1 << PAD_PIN(gpio), &reg->reg_set); in gpio_set_value()
99 writel(1 << PAD_PIN(gpio), &reg->reg_set); in gpio_direction_output()
186 writel(BIT(offset), &reg->reg_set); in mxs_gpio_set_value()
215 writel(BIT(offset), &reg->reg_set); in mxs_gpio_direction_output()
/external/u-boot/arch/arm/cpu/arm926ejs/mxs/
Diomux.c62 writel(1 << bp, &mxs_reg->reg_set); in mxs_iomux_setup_pad()
74 writel(1 << bp, &mxs_reg->reg_set); in mxs_iomux_setup_pad()
/external/arm-trusted-firmware/drivers/rpi3/gpio/
Drpi3_gpio.c125 uintptr_t reg_set = reg_base + RPI3_GPIO_GPSET(regN); in rpi3_gpio_set_value() local
133 mmio_write_32(reg_set, U(1) << shift); in rpi3_gpio_set_value()
/external/u-boot/drivers/usb/host/
Dehci-mxs.c65 pll_offset = offsetof(struct mxs_register_32, reg_set); in ehci_mxs_toggle_clock()
71 dig_offset = offsetof(struct mxs_register_32, reg_set); in ehci_mxs_toggle_clock()
/external/u-boot/arch/arm/mach-imx/
Dmisc.c56 writel(MXS_BLOCK_SFTRST, &reg->reg_set); in mxs_reset_block()
/external/mesa3d/src/freedreno/decode/
Dcffdec.h84 void reg_set(uint32_t regbase, uint32_t val);
Dcffdec.c327 reg_set(uint32_t regbase, uint32_t val) in reg_set() function
893 reg_set(regbase, *dwords); in dump_registers()
1153 reg_set(reg, dwords[i]); in cp_wide_reg_write()
2203 reg_set(val, (reg_val(val) & and) | or); in cp_rmw()
2523 reg_set(dwords[i+0], dwords[i+1]); in cp_context_reg_bunch()
2535 reg_set(reg, dwords[2]); in cp_reg_write()
Dcrashdec.c435 reg_set(offset/4, value); in decode_registers()