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Searched refs:reg_write (Results 1 – 25 of 30) sorted by relevance

12

/external/u-boot/arch/arm/mach-mvebu/serdes/axp/
Dhigh_speed_env_lib.c315 reg_write(CPU_AVS_CONTROL0_REG, tmp2); in serdes_phy_config()
333 reg_write(CORE_AVS_CONTROL_0REG, core_avs); in serdes_phy_config()
339 reg_write(CORE_AVS_CONTROL_2REG, core_avs); in serdes_phy_config()
346 reg_write(GENERAL_PURPOSE_RESERVED0_REG, tmp2); in serdes_phy_config()
351 reg_write(CPU_AVS_CONTROL2_REG, cpu_avs); in serdes_phy_config()
369 reg_write(SERDES_LINE_MUX_REG_0_7, 0x11111111); in serdes_phy_config()
373 reg_write(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d); /* SETM0 - start calibration */ in serdes_phy_config()
375 reg_write(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d); /* SETM1 - start calibration */ in serdes_phy_config()
377 reg_write(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801); /* SETM0 - SATA mode & 25MHz ref clk */ in serdes_phy_config()
379 reg_write(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801); /* SETM1 - SATA mode & 25MHz ref clk */ in serdes_phy_config()
[all …]
/external/u-boot/board/Synology/ds414/
Dds414.c133 reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW); in board_early_init_f()
134 reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID); in board_early_init_f()
135 reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH); in board_early_init_f()
138 reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW); in board_early_init_f()
139 reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID); in board_early_init_f()
140 reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH); in board_early_init_f()
143 reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW); in board_early_init_f()
144 reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID); in board_early_init_f()
145 reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH); in board_early_init_f()
148 reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]); in board_early_init_f()
[all …]
Dcmd_syno.c192 reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg); in do_syno_clk_gate()
/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_write_leveling.c78 reg_write(REG_DUNIT_CTRL_LOW_ADDR, in ddr3_write_leveling_hw()
87 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw()
91 reg_write(REG_DRAM_TRAINING_SHADOW_ADDR, reg); in ddr3_write_leveling_hw()
164 reg_write(REG_DUNIT_CTRL_LOW_ADDR, reg); in ddr3_write_leveling_hw()
223 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_wl_supplement()
226 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_wl_supplement()
258 reg_write(REG_DRAM_TRAINING_2_ADDR, in ddr3_wl_supplement()
403 reg_write(REG_DRAM_TRAINING_2_ADDR, in ddr3_wl_supplement()
453 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_wl_supplement()
457 reg_write(REG_DRAM_TRAINING_1_ADDR, reg); in ddr3_wl_supplement()
[all …]
Dddr3_init.c159 reg_write((win_ctrl_reg + 0x4 * ui), win_backup[ui]); in ddr3_restore_and_set_final_windows()
165 reg_write(0x8c04, 0x40000000); in ddr3_restore_and_set_final_windows()
175 reg_write(REG_FASTPATH_WIN_CTRL_ADDR(cs), reg); in ddr3_restore_and_set_final_windows()
179 reg_write(REG_FASTPATH_WIN_BASE_ADDR(cs), reg); in ddr3_restore_and_set_final_windows()
192 reg_write(REG_FASTPATH_WIN_0_CTRL_ADDR, reg); in ddr3_restore_and_set_final_windows()
205 reg_write(0x8c04, 0); in ddr3_save_and_set_training_windows()
222 reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0); in ddr3_save_and_set_training_windows()
250 reg_write(win_ctrl_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
253 reg_write(win_base_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
257 reg_write(win_remap_reg + in ddr3_save_and_set_training_windows()
[all …]
Dxor.c41 reg_write(XOR_WINDOW_CTRL_REG(0, 0), reg); in mv_sys_xor_init()
45 reg_write(XOR_BASE_ADDR_REG(0, dram_info->num_cs), base); in mv_sys_xor_init()
47 reg_write(XOR_SIZE_MASK_REG(0, dram_info->num_cs), 0x03FF0000); in mv_sys_xor_init()
71 reg_write(XOR_BASE_ADDR_REG(0, cs_count), base); in mv_sys_xor_init()
74 reg_write(XOR_SIZE_MASK_REG(0, cs_count), 0x0FFF0000); in mv_sys_xor_init()
88 reg_write(XOR_WINDOW_CTRL_REG(0, 0), xor_regs_ctrl_backup); in mv_sys_xor_finish()
90 reg_write(XOR_BASE_ADDR_REG(0, ui), xor_regs_base_backup[ui]); in mv_sys_xor_finish()
92 reg_write(XOR_SIZE_MASK_REG(0, ui), xor_regs_mask_backup[ui]); in mv_sys_xor_finish()
94 reg_write(XOR_ADDR_OVRD_REG(0, 0), 0); in mv_sys_xor_finish()
149 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), xor_ctrl); in mv_xor_ctrl_set()
[all …]
Dddr3_spd.c776 reg_write(REG_SDRAM_CONFIG_ADDR, reg);
783 reg_write(REG_DUNIT_CTRL_LOW_ADDR, reg);
849 reg_write(REG_SDRAM_TIMING_LOW_ADDR, reg);
863 reg_write(REG_SDRAM_TIMING_HIGH_ADDR, reg);
932 reg_write(REG_SDRAM_ADDRESS_CTRL_ADDR, reg);
940 reg_write(REG_SDRAM_OPERATION_ADDR, reg);
944 reg_write(REG_SDRAM_EXT_MODE_ADDR, reg);
952 reg_write(REG_DDR_CONT_HIGH_ADDR, reg);
959 reg_write(0x142C, reg);
964 reg_write(REG_MBUS_CPU_BLOCK_ADDR, 0x0000E907);
[all …]
Dddr3_hw_training.c109 reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_hw_training()
541 reg_write(REG_SDRAM_TIMING_HIGH_ADDR, reg); in ddr3_set_performance_params()
562 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_write_pup_reg()
564 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_write_pup_reg()
583 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_write_pup_reg()
585 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_write_pup_reg()
603 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_read_pup_reg()
606 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_read_pup_reg()
629 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_load_patterns()
632 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_load_patterns()
[all …]
Dddr3_read_leveling.c76 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_read_leveling_hw()
80 reg_write(REG_DRAM_TRAINING_SHADOW_ADDR, reg); in ddr3_read_leveling_hw()
193 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
198 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_read_leveling_sw()
211 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
224 reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, reg); in ddr3_read_leveling_sw()
239 reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg); in ddr3_read_leveling_sw()
301 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
311 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
314 reg_write(REG_DRAM_TRAINING_ADDR, 0); /* 0x15B0 - Training Register */ in ddr3_read_leveling_sw()
[all …]
Dddr3_pbs.c112 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_tx()
116 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_pbs_tx()
163 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_tx()
287 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_tx()
384 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_tx()
388 reg_write(REG_DRAM_TRAINING_1_ADDR, reg); in ddr3_pbs_tx()
555 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_rx()
559 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_pbs_rx()
605 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_rx()
677 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_pbs_rx()
[all …]
Dddr3_dqs.c143 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_rx()
147 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_dqs_centralization_rx()
162 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_rx()
189 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_rx()
196 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_rx()
200 reg_write(REG_DRAM_TRAINING_1_ADDR, reg); in ddr3_dqs_centralization_rx()
225 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_tx()
229 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_dqs_centralization_tx()
242 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_tx()
269 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_tx()
[all …]
Dddr3_sdram.c70 reg_write(XOR_CAUSE_REG(XOR_UNIT(chan)), in xor_waiton_eng()
511 reg_write(XOR_ADDR_OVRD_REG(0, 0), in ddr3_dram_sram_burst()
518 reg_write(XOR_ADDR_OVRD_REG(0, 0), in ddr3_dram_sram_burst()
646 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_reset_phy_read_fifo()
654 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_reset_phy_read_fifo()
667 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_reset_phy_read_fifo()
Dddr3_init.h122 static inline void reg_write(u32 addr, u32 val) in reg_write() function
/external/u-boot/drivers/ddr/marvell/a38x/
Dxor.c46 reg_write(XOR_WINDOW_CTRL_REG(0, 0), reg); in mv_sys_xor_init()
81 reg_write(XOR_BASE_ADDR_REG(0, ui), (u32)base); in mv_sys_xor_init()
85 reg_write(XOR_SIZE_MASK_REG(0, ui), (u32)size_mask); in mv_sys_xor_init()
98 reg_write(XOR_WINDOW_CTRL_REG(0, 0), ui_xor_regs_ctrl_backup); in mv_sys_xor_finish()
100 reg_write(XOR_BASE_ADDR_REG(0, ui), in mv_sys_xor_finish()
103 reg_write(XOR_SIZE_MASK_REG(0, ui), in mv_sys_xor_finish()
106 reg_write(XOR_ADDR_OVRD_REG(0, 0), 0); in mv_sys_xor_finish()
160 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), xor_ctrl); in mv_xor_ctrl_set()
188 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), temp); in mv_xor_mem_init()
194 reg_write(XOR_DST_PTR_REG(XOR_UNIT(chan), XOR_CHAN(chan)), start_ptr); in mv_xor_mem_init()
[all …]
Dmv_ddr_plat.c201 reg_write(TSEN_CONTROL_LSB_REG, reg); in ddr3_ctrl_get_junc_temp()
256 reg_write(addr, reg_val); in dunit_write()
375 reg_write(DUAL_DUNIT_CFG_REG, reg); in ddr3_tip_a38x_select_ddr_controller()
1075 reg_write(REG_FASTPATH_WIN_CTRL_ADDR(cs), reg); in ddr3_fast_path_dynamic_cs_size_config()
1080 reg_write(REG_FASTPATH_WIN_BASE_ADDR(cs), reg); in ddr3_fast_path_dynamic_cs_size_config()
1099 reg_write(ADDRESS_FILTERING_END_REGISTER, mem_total_size); in ddr3_fast_path_dynamic_cs_size_config()
1115 reg_write((win_ctrl_reg + 0x4 * ui), win[ui]); in ddr3_restore_and_set_final_windows()
1133 reg_write(REG_FASTPATH_WIN_CTRL_ADDR(0), reg); in ddr3_restore_and_set_final_windows()
1157 reg_write(ADDRESS_FILTERING_END_REGISTER, 0); in ddr3_save_and_set_training_windows()
1164 reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0); in ddr3_save_and_set_training_windows()
[all …]
Dmv_ddr_sys_env_lib.c71 reg_write(MPP_CONTROL_REG(MPP_REG_NUM(gpio)), reg); in mv_ddr_sys_env_suspend_wakeup_check()
76 reg_write(GPP_DATA_OUT_EN_REG(GPP_REG_NUM(gpio)), reg); in mv_ddr_sys_env_suspend_wakeup_check()
Dddr_ml_wrapper.h128 static inline void reg_write(u32 addr, u32 val) in reg_write() function
/external/u-boot/drivers/spi/
Dmxc_spi.c35 #define reg_write(a, v) writel(v, a) macro
166 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
168 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
222 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
224 reg_write(&regs->cfg, reg_config); in spi_cfg_mxc()
231 reg_write(&regs->intr, 0); in spi_cfg_mxc()
232 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
254 reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); in spi_xchg_single()
256 reg_write(&regs->cfg, mxcs->cfg_reg); in spi_xchg_single()
260 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
[all …]
/external/u-boot/arch/arm/mach-mvebu/
Ddram.c133 reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN), reg); in mv_xor_init2()
140 reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), in mv_xor_init2()
146 reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), size); in mv_xor_init2()
156 reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN), in mv_xor_finish2()
158 reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), in mv_xor_finish2()
160 reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), in mv_xor_finish2()
180 reg_write(REG_SDRAM_CONFIG_ADDR, temp); in dram_ecc_scrubbing()
210 reg_write(REG_SDRAM_CONFIG_ADDR, temp); in dram_ecc_scrubbing()
/external/u-boot/arch/arm/mach-mvebu/serdes/a38x/
Dctrl_pex.c47 reg_write(PEX_CAPABILITIES_REG(pex_idx), tmp); in hws_pex_config()
80 reg_write(SOC_CTRL_REG, tmp); in hws_pex_config()
176 reg_write(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp); in hws_pex_config()
182 reg_write(PEX_CTRL_REG(pex_idx), tmp); in hws_pex_config()
219 reg_write(PEX_CFG_DIRECT_ACCESS in hws_pex_config()
243 reg_write(PEX_STATUS_REG(pex_if), pex_status); in pex_local_bus_num_set()
258 reg_write(PEX_STATUS_REG(pex_if), pex_status); in pex_local_dev_num_set()
334 reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data); in pex_config_read()
Dsys_env_lib.c124 reg_write(MPP_CONTROL_REG(MPP_REG_NUM(gpio)), reg); in sys_env_suspend_wakeup_check()
129 reg_write(GPP_DATA_OUT_EN_REG(GPP_REG_NUM(gpio)), reg); in sys_env_suspend_wakeup_check()
267 reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE); in mv_avs_init()
268 reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE); in mv_avs_init()
282 reg_write(AVS_ENABLED_CONTROL, avs_reg_data); in mv_avs_init()
Dhigh_speed_env_spec.c1402 reg_write(CORE_PLL_PARAMETERS_REG, 0x42e9f003); in hws_pre_serdes_init_config()
1407 reg_write(CORE_PLL_CONFIG_REG, data); in hws_pre_serdes_init_config()
1465 reg_write(reg_addr, data); in serdes_polarity_config()
1583 reg_write(GENERAL_PURPOSE_RESERVED0_REG, reg_data); in serdes_pex_usb3_pipe_delay_w_a()
1729 reg_write(SOC_CONTROL_REG1, reg_data); in serdes_power_up_ctrl()
1739 reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c), in serdes_power_up_ctrl()
1747 reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x6c), in serdes_power_up_ctrl()
1755 reg_write(((PEX_IF_REGS_BASE(pex_idx)) + 0x70), in serdes_power_up_ctrl()
1866 reg_write(GBE_CONFIGURATION_REG, reg_data); in serdes_power_up_ctrl()
2005 reg_write(COMMON_PHYS_SELECTORS_REG, reg_data); in hws_update_serdes_phy_selectors()
[all …]
Dseq_exec.c60 reg_write(reg_addr, reg_data); in write_op_execute()
/external/mesa3d/src/intel/tools/
Daub_read.h51 void (*reg_write)(void *user_data, uint32_t reg_offset, uint32_t reg_value); member
Daub_read.c183 if (read->reg_write) in handle_memtrace_reg_write()
184 read->reg_write(read->user_data, offset, value); in handle_memtrace_reg_write()

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