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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/msa/
Dtest_elm.s8 sldi.b $w0, $w29[4] # CHECK: sldi.b $w0, $w29[4] # encoding: [0x78,0x04,0xe8,0x19]
9 sldi.h $w8, $w17[0] # CHECK: sldi.h $w8, $w17[0] # encoding: [0x78,0x20,0x8a,0x19]
10 sldi.w $w20, $w27[2] # CHECK: sldi.w $w20, $w27[2] # encoding: [0x78,0x32,0xdd,0x19]
11 sldi.d $w4, $w12[0] # CHECK: sldi.d $w4, $w12[0] # encoding: [0x78,0x38,0x61,0x19]
Dinvalid-64.s43 sldi.b $w0, $w29[-1] # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate
44 sldi.b $w0, $w29[16] # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate
45 sldi.d $w4, $w12[-1] # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate
46 sldi.d $w4, $w12[2] # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate
47 sldi.h $w8, $w17[-1] # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate
48 sldi.h $w8, $w17[8] # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate
49 sldi.w $w20, $w27[-1] # CHECK: :[[@LINE]]:23: error: expected 2-bit unsigned immediate
50 sldi.w $w20, $w27[4] # CHECK: :[[@LINE]]:23: error: expected 2-bit unsigned immediate
/external/llvm/test/MC/Mips/msa/
Dtest_elm.s8 sldi.b $w0, $w29[4] # CHECK: sldi.b $w0, $w29[4] # encoding: [0x78,0x04,0xe8,0x19]
9 sldi.h $w8, $w17[0] # CHECK: sldi.h $w8, $w17[0] # encoding: [0x78,0x20,0x8a,0x19]
10 sldi.w $w20, $w27[2] # CHECK: sldi.w $w20, $w27[2] # encoding: [0x78,0x32,0xdd,0x19]
11 sldi.d $w4, $w12[0] # CHECK: sldi.d $w4, $w12[0] # encoding: [0x78,0x38,0x61,0x19]
Dinvalid-64.s43 sldi.b $w0, $w29[-1] # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate
44 sldi.b $w0, $w29[16] # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate
45 sldi.d $w4, $w12[-1] # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate
46 sldi.d $w4, $w12[2] # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate
47 sldi.h $w8, $w17[-1] # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate
48 sldi.h $w8, $w17[8] # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate
49 sldi.w $w20, $w27[-1] # CHECK: :[[@LINE]]:23: error: expected 2-bit unsigned immediate
50 sldi.w $w20, $w27[4] # CHECK: :[[@LINE]]:23: error: expected 2-bit unsigned immediate
/external/llvm/test/CodeGen/PowerPC/
Dvariable_elem_vec_extracts.ll17 ; CHECK-DAG: sldi [[SHIFTREG:[0-9]+]], [[MASKREG]], 2
22 ; CHECK-DAG: sldi [[SHAMREG:[0-9]+]], [[ELEMSREG]], 5
26 ; CHECK-P7-DAG: sldi [[ELEMOFFREG:[0-9]+]], 5, 2
30 ; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 2
35 ; CHECK-BE-DAG: sldi [[SHAMREG:[0-9]+]], [[ANDCREG]], 5
51 ; CHECK-DAG: sldi [[SHIFTREG:[0-9]+]], [[MASKREG]], 3
55 ; CHECK-P7-DAG: sldi [[ELEMOFFREG:[0-9]+]], 5, 3
59 ; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 3
78 ; CHECK-P7-DAG: sldi [[ELEMOFFREG:[0-9]+]], 5, 2
81 ; CHECK-BE: sldi [[ELNOREG:[0-9]+]], 5, 2
[all …]
Dfp128-bitcast-after-operation.ll15 ; PPC64: sldi [[MASK_REG]], [[MASK_REG]], 63
27 ; PPC64-P8-DAG: sldi [[SHIFT_REG:[0-9]+]], [[MASK_REG]], 63
57 ; PPC64-DAG: sldi [[FLIP_BIT]], [[FLIP_BIT]], 63
69 ; PPC64-P8-DAG: sldi [[FLIP_BIT]], [[IMM1]], 63
97 ; PPC64-DAG: sldi [[SIGN]], [[SIGN]], 63
99 ; PPC64-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
101 ; PPC64-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
112 ; PPC64-P8-DAG: sldi [[SIGN]], [[SIGN]], 63
114 ; PPC64-P8-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
116 ; PPC64-P8-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
Dbperm.ll50 ; CHECK-DAG: sldi [[REG2:[0-9]+]], [[REG1]], 19
65 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32
81 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 34
108 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 19
153 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 19
173 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32
194 ; CHECK-DAG: sldi [[REG4:[0-9]+]], [[REG2]], 25
195 ; CHECK-DAG: sldi [[REG5:[0-9]+]], [[REG3]], 37
Darr-fp-arg-no-copy.ll14 ; CHECK-DAG: sldi 3, [[REG1]], 52
15 ; CHECK-DAG: sldi 4, [[REG2]], 62
Dstore-update.ll47 ; CHECK-NEXT: sldi
70 ; CHECK-NEXT: sldi
119 ; CHECK-NEXT: sldi
144 ; CHECK-NEXT: sldi
167 ; CHECK-NEXT: sldi
Dqpx-load-splat.ll27 ; CHECK: sldi [[REG1:[0-9]+]], 4, 3
42 ; CHECK: sldi [[REG1:[0-9]+]], 4, 3
69 ; CHECK: sldi [[REG1:[0-9]+]], 4, 2
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
DtestBitReverse.ll52 ; CHECK-NEXT: sldi 8, 3, 1
58 ; CHECK-NEXT: sldi 4, 4, 32
59 ; CHECK-NEXT: sldi 5, 5, 32
66 ; CHECK-NEXT: sldi 5, 6, 32
67 ; CHECK-NEXT: sldi 6, 7, 32
74 ; CHECK-NEXT: sldi 8, 3, 2
81 ; CHECK-NEXT: sldi 5, 6, 32
82 ; CHECK-NEXT: sldi 6, 7, 32
86 ; CHECK-NEXT: sldi 6, 3, 4
100 ; CHECK-NEXT: sldi 3, 5, 32
Dvariable_elem_vec_extracts.ll17 ; CHECK-DAG: sldi [[SHIFTREG:[0-9]+]], [[MASKREG]], 2
22 ; CHECK-DAG: sldi [[SHAMREG:[0-9]+]], [[ELEMSREG]], 5
30 ; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 2
35 ; CHECK-BE-DAG: sldi [[SHAMREG:[0-9]+]], [[ANDCREG]], 5
51 ; CHECK-DAG: sldi [[SHIFTREG:[0-9]+]], [[MASKREG]], 3
59 ; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 3
74 ; CHECK: sldi [[SHIFTREG:[0-9]+]], [[TRUNCREG]], 2
81 ; CHECK-BE: sldi [[ELNOREG:[0-9]+]], 5, 2
97 ; CHECK: sldi [[SHIFTREG:[0-9]+]], [[MASKREG]], 3
103 ; CHECK-P7-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 3
[all …]
Dpr33093.ll76 ; CHECK-NEXT: sldi 8, 3, 1
82 ; CHECK-NEXT: sldi 4, 4, 32
83 ; CHECK-NEXT: sldi 5, 5, 32
90 ; CHECK-NEXT: sldi 5, 6, 32
91 ; CHECK-NEXT: sldi 6, 7, 32
98 ; CHECK-NEXT: sldi 8, 3, 2
105 ; CHECK-NEXT: sldi 5, 6, 32
106 ; CHECK-NEXT: sldi 6, 7, 32
110 ; CHECK-NEXT: sldi 6, 3, 4
124 ; CHECK-NEXT: sldi 3, 5, 32
Dstore_fptoi.ll195 ; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 3
202 ; CHECK-PWR8: sldi [[REG:[0-9]+]], 5, 3
221 ; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 2
228 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2
247 ; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 1
254 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
299 ; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 3
306 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 3
325 ; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 2
332 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2
[all …]
Dfp128-bitcast-after-operation.ll52 ; PPC64-DAG: sldi [[FLIP_BIT]], [[FLIP_BIT]], 63
64 ; PPC64-P8-DAG: sldi [[FLIP_BIT:[0-9]+]], [[IMM1]], 63
93 ; PPC64-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
94 ; PPC64-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
106 ; PPC64-P8-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
107 ; PPC64-P8-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
Dbperm.ll50 ; CHECK-DAG: sldi [[REG2:[0-9]+]], [[REG1]], 19
65 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32
81 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 34
108 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 19
153 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 19
173 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32
194 ; CHECK-DAG: sldi [[REG4:[0-9]+]], [[REG2]], 25
195 ; CHECK-DAG: sldi [[REG5:[0-9]+]], [[REG3]], 37
Dbuild-vector-tests.ll87 ;// P8: sldi 2, lxvd2x, xxswapd //
88 ;// P9: sldi 2, lxvx //
92 ;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm //
93 ;// P9: sldi 2, 2 x lxvx, vperm //
102 ;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
103 ;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow //
145 ;// sldi 2, load, xvcvspuxws //
152 ;// sldi 2, 2 x load, vperm, xvcvspuxws //
259 ;// P8: sldi 2, lxvd2x, xxswapd //
260 ;// P9: sldi 2, lxvx //
[all …]
Darr-fp-arg-no-copy.ll14 ; CHECK-DAG: sldi 3, [[REG1]], 52
15 ; CHECK-DAG: sldi 4, [[REG2]], 62
Dstore-update.ll47 ; CHECK-NEXT: sldi
70 ; CHECK-NEXT: sldi
119 ; CHECK-NEXT: sldi
144 ; CHECK-NEXT: sldi
167 ; CHECK-NEXT: sldi
/external/capstone/suite/MC/Mips/
Dtest_elm.s.cs8 0x78,0x04,0xe8,0x19 = sldi.b $w0, $w29[4]
9 0x78,0x20,0x8a,0x19 = sldi.h $w8, $w17[0]
10 0x78,0x32,0xdd,0x19 = sldi.w $w20, $w27[2]
11 0x78,0x38,0x61,0x19 = sldi.d $w4, $w12[0]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/
Delm_shift_slide.ll15 %2 = tail call <16 x i8> @llvm.mips.sldi.b(<16 x i8> %0, <16 x i8> %1, i32 1)
20 declare <16 x i8> @llvm.mips.sldi.b(<16 x i8>, <16 x i8>, i32) nounwind
24 ; CHECK: sldi.b
36 %2 = tail call <8 x i16> @llvm.mips.sldi.h(<8 x i16> %0, <8 x i16> %1, i32 1)
41 declare <8 x i16> @llvm.mips.sldi.h(<8 x i16>, <8 x i16>, i32) nounwind
45 ; CHECK: sldi.h
57 %2 = tail call <4 x i32> @llvm.mips.sldi.w(<4 x i32> %0, <4 x i32> %1, i32 1)
62 declare <4 x i32> @llvm.mips.sldi.w(<4 x i32>, <4 x i32>, i32) nounwind
66 ; CHECK: sldi.w
78 %2 = tail call <2 x i64> @llvm.mips.sldi.d(<2 x i64> %0, <2 x i64> %1, i32 1)
[all …]
/external/llvm/test/CodeGen/Mips/msa/
Delm_shift_slide.ll15 %2 = tail call <16 x i8> @llvm.mips.sldi.b(<16 x i8> %0, <16 x i8> %1, i32 1)
20 declare <16 x i8> @llvm.mips.sldi.b(<16 x i8>, <16 x i8>, i32) nounwind
24 ; CHECK: sldi.b
36 %2 = tail call <8 x i16> @llvm.mips.sldi.h(<8 x i16> %0, <8 x i16> %1, i32 1)
41 declare <8 x i16> @llvm.mips.sldi.h(<8 x i16>, <8 x i16>, i32) nounwind
45 ; CHECK: sldi.h
57 %2 = tail call <4 x i32> @llvm.mips.sldi.w(<4 x i32> %0, <4 x i32> %1, i32 1)
62 declare <4 x i32> @llvm.mips.sldi.w(<4 x i32>, <4 x i32>, i32) nounwind
66 ; CHECK: sldi.w
78 %2 = tail call <2 x i64> @llvm.mips.sldi.d(<2 x i64> %0, <2 x i64> %1, i32 1)
[all …]
/external/llvm/test/MC/Disassembler/Mips/msa/
Dtest_elm.txt8 0x78 0x04 0xe8 0x19 # CHECK: sldi.b $w0, $w29[4]
9 0x78 0x20 0x8a 0x19 # CHECK: sldi.h $w8, $w17[0]
10 0x78 0x32 0xdd 0x19 # CHECK: sldi.w $w20, $w27[2]
11 0x78 0x38 0x61 0x19 # CHECK: sldi.d $w4, $w12[0]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/msa/
Dtest_elm.txt8 0x78 0x04 0xe8 0x19 # CHECK: sldi.b $w0, $w29[4]
9 0x78 0x20 0x8a 0x19 # CHECK: sldi.h $w8, $w17[0]
10 0x78 0x32 0xdd 0x19 # CHECK: sldi.w $w20, $w27[2]
11 0x78 0x38 0x61 0x19 # CHECK: sldi.d $w4, $w12[0]
/external/linux-kselftest/tools/testing/selftests/powerpc/security/
Dbranch_loops.S39 sldi r4, r4, ITER_SHIFT
47 sldi r5, r3, 2
68 sldi r3, r3, ITER_SHIFT

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