1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s 3; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s 4declare i32 @llvm.bitreverse.i32(i32) 5define i32 @testBitReverseIntrinsicI32(i32 %arg) { 6; CHECK-LABEL: testBitReverseIntrinsicI32: 7; CHECK: # %bb.0: 8; CHECK-NEXT: lis 4, -21846 9; CHECK-NEXT: lis 5, 21845 10; CHECK-NEXT: slwi 6, 3, 1 11; CHECK-NEXT: srwi 3, 3, 1 12; CHECK-NEXT: ori 4, 4, 43690 13; CHECK-NEXT: ori 5, 5, 21845 14; CHECK-NEXT: and 4, 6, 4 15; CHECK-NEXT: and 3, 3, 5 16; CHECK-NEXT: lis 5, 13107 17; CHECK-NEXT: or 3, 3, 4 18; CHECK-NEXT: lis 4, -13108 19; CHECK-NEXT: ori 5, 5, 13107 20; CHECK-NEXT: slwi 6, 3, 2 21; CHECK-NEXT: ori 4, 4, 52428 22; CHECK-NEXT: srwi 3, 3, 2 23; CHECK-NEXT: and 4, 6, 4 24; CHECK-NEXT: and 3, 3, 5 25; CHECK-NEXT: lis 5, 3855 26; CHECK-NEXT: or 3, 3, 4 27; CHECK-NEXT: lis 4, -3856 28; CHECK-NEXT: ori 5, 5, 3855 29; CHECK-NEXT: slwi 6, 3, 4 30; CHECK-NEXT: ori 4, 4, 61680 31; CHECK-NEXT: srwi 3, 3, 4 32; CHECK-NEXT: and 4, 6, 4 33; CHECK-NEXT: and 3, 3, 5 34; CHECK-NEXT: or 3, 3, 4 35; CHECK-NEXT: rotlwi 4, 3, 24 36; CHECK-NEXT: rlwimi 4, 3, 8, 8, 15 37; CHECK-NEXT: rlwimi 4, 3, 8, 24, 31 38; CHECK-NEXT: rldicl 3, 4, 0, 32 39; CHECK-NEXT: blr 40 %res = call i32 @llvm.bitreverse.i32(i32 %arg) 41 ret i32 %res 42} 43 44declare i64 @llvm.bitreverse.i64(i64) 45define i64 @testBitReverseIntrinsicI64(i64 %arg) { 46; CHECK-LABEL: testBitReverseIntrinsicI64: 47; CHECK: # %bb.0: 48; CHECK-NEXT: lis 4, -21846 49; CHECK-NEXT: lis 5, 21845 50; CHECK-NEXT: lis 6, -13108 51; CHECK-NEXT: lis 7, 13107 52; CHECK-NEXT: sldi 8, 3, 1 53; CHECK-NEXT: rldicl 3, 3, 63, 1 54; CHECK-NEXT: ori 4, 4, 43690 55; CHECK-NEXT: ori 5, 5, 21845 56; CHECK-NEXT: ori 6, 6, 52428 57; CHECK-NEXT: ori 7, 7, 13107 58; CHECK-NEXT: sldi 4, 4, 32 59; CHECK-NEXT: sldi 5, 5, 32 60; CHECK-NEXT: oris 4, 4, 43690 61; CHECK-NEXT: oris 5, 5, 21845 62; CHECK-NEXT: ori 4, 4, 43690 63; CHECK-NEXT: ori 5, 5, 21845 64; CHECK-NEXT: and 4, 8, 4 65; CHECK-NEXT: and 3, 3, 5 66; CHECK-NEXT: sldi 5, 6, 32 67; CHECK-NEXT: sldi 6, 7, 32 68; CHECK-NEXT: lis 7, 3855 69; CHECK-NEXT: or 3, 3, 4 70; CHECK-NEXT: oris 4, 5, 52428 71; CHECK-NEXT: oris 5, 6, 13107 72; CHECK-NEXT: lis 6, -3856 73; CHECK-NEXT: ori 7, 7, 3855 74; CHECK-NEXT: sldi 8, 3, 2 75; CHECK-NEXT: ori 4, 4, 52428 76; CHECK-NEXT: rldicl 3, 3, 62, 2 77; CHECK-NEXT: ori 5, 5, 13107 78; CHECK-NEXT: ori 6, 6, 61680 79; CHECK-NEXT: and 4, 8, 4 80; CHECK-NEXT: and 3, 3, 5 81; CHECK-NEXT: sldi 5, 6, 32 82; CHECK-NEXT: sldi 6, 7, 32 83; CHECK-NEXT: or 3, 3, 4 84; CHECK-NEXT: oris 4, 5, 61680 85; CHECK-NEXT: oris 5, 6, 3855 86; CHECK-NEXT: sldi 6, 3, 4 87; CHECK-NEXT: ori 4, 4, 61680 88; CHECK-NEXT: rldicl 3, 3, 60, 4 89; CHECK-NEXT: ori 5, 5, 3855 90; CHECK-NEXT: and 4, 6, 4 91; CHECK-NEXT: and 3, 3, 5 92; CHECK-NEXT: or 3, 3, 4 93; CHECK-NEXT: rldicl 4, 3, 32, 32 94; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31 95; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31 96; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15 97; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31 98; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15 99; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31 100; CHECK-NEXT: sldi 3, 5, 32 101; CHECK-NEXT: or 3, 3, 6 102; CHECK-NEXT: blr 103 %res = call i64 @llvm.bitreverse.i64(i64 %arg) 104 ret i64 %res 105} 106