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Searched refs:swizzle_mode (Results 1 – 25 of 37) sorted by relevance

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/external/igt-gpu-tools/tests/i915/
Dgem_tiled_wb.c119 uint32_t swizzle_mode; in get_tiling() member
128 igt_require(arg.phys_swizzle_mode == arg.swizzle_mode); in get_tiling()
131 *swizzle = arg.swizzle_mode; in get_tiling()
Dgem_tiled_partial_pwrite_pread.c258 return arg.phys_swizzle_mode == arg.swizzle_mode; in known_swizzling()
Dgem_mmap_gtt.c576 uint32_t swizzle_mode; in known_swizzling() member
586 return arg.phys_swizzle_mode == arg.swizzle_mode; in known_swizzling()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_clear.c283 assert(tex->surface.u.gfx9.surf.swizzle_mode >= 4); in si_set_optimal_micro_tile_mode()
293 assert(tex->surface.u.gfx9.surf.swizzle_mode % 4 != 0); in si_set_optimal_micro_tile_mode()
297 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
298 tex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */ in si_set_optimal_micro_tile_mode()
301 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
302 tex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */ in si_set_optimal_micro_tile_mode()
305 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
306 tex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */ in si_set_optimal_micro_tile_mode()
Dsi_test_dma.c124 switch (surf->u.gfx9.surf.swizzle_mode) { in array_mode_to_string()
136 printf("Unhandled swizzle mode = %u\n", surf->u.gfx9.surf.swizzle_mode); in array_mode_to_string()
/external/mesa3d/src/amd/common/
Dac_surface.c96 unsigned swizzle_mode; member
127 unsigned bpp, unsigned swizzle_mode, bool rb_aligned, in ac_compute_dcc_retile_tile_indices() argument
135 key.swizzle_mode = swizzle_mode; in ac_compute_dcc_retile_tile_indices()
151 din.swizzleMode = swizzle_mode; in ac_compute_dcc_retile_tile_indices()
165 addrin.swizzleMode = swizzle_mode; in ac_compute_dcc_retile_tile_indices()
1230 AddrSwizzleMode *swizzle_mode) in gfx9_get_preferred_swizzle_mode() argument
1277 *swizzle_mode = sout.swizzleMode; in gfx9_get_preferred_swizzle_mode()
1380 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode; in gfx9_compute_miptree()
1389 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode; in gfx9_compute_miptree()
1395 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3; in gfx9_compute_miptree()
[all …]
Dac_surface.h138 uint16_t swizzle_mode; /* tile mode */ member
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_bufmgr.h168 uint32_t swizzle_mode; member
323 uint32_t *swizzle_mode);
Dbrw_bufmgr.c649 bo->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; in bo_alloc_internal()
830 bo->swizzle_mode = get_tiling.swizzle_mode; in brw_bo_gem_create_from_name()
1451 bo->swizzle_mode = set_tiling.swizzle_mode; in bo_set_tiling_internal()
1458 uint32_t *swizzle_mode) in brw_bo_get_tiling() argument
1461 *swizzle_mode = bo->swizzle_mode; in brw_bo_get_tiling()
1529 bo->swizzle_mode = get_tiling.swizzle_mode; in brw_bo_gem_create_from_prime_internal()
/external/libdrm/intel/
Dintel_bufmgr.c251 uint32_t * swizzle_mode) in drm_intel_bo_get_tiling() argument
254 return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode); in drm_intel_bo_get_tiling()
257 *swizzle_mode = I915_BIT_6_SWIZZLE_NONE; in drm_intel_bo_get_tiling()
Dintel_bufmgr_gem.c192 uint32_t swizzle_mode; member
294 uint32_t * swizzle_mode);
822 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; in drm_intel_gem_bo_alloc_internal()
983 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; in drm_intel_gem_bo_alloc_userptr()
1158 bo_gem->swizzle_mode = get_tiling.swizzle_mode; in drm_intel_bo_gem_create_from_name()
2574 bo_gem->swizzle_mode = set_tiling.swizzle_mode; in drm_intel_gem_bo_set_tiling_internal()
2609 uint32_t * swizzle_mode) in drm_intel_gem_bo_get_tiling() argument
2614 *swizzle_mode = bo_gem->swizzle_mode; in drm_intel_gem_bo_get_tiling()
2699 bo_gem->swizzle_mode = get_tiling.swizzle_mode; in drm_intel_bo_gem_create_from_prime()
Dintel_bufmgr_priv.h241 uint32_t * swizzle_mode);
Dintel_bufmgr.h163 uint32_t * swizzle_mode);
/external/mesa3d/src/amd/vulkan/
Dradv_image.c326 if (md->u.gfx9.swizzle_mode > 0) in radv_patch_surface_from_metadata()
331 surface->u.gfx9.surf.swizzle_mode = md->u.gfx9.swizzle_mode; in radv_patch_surface_from_metadata()
682 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode); in si_set_mutable_tex_desc_fields()
684 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode); in si_set_mutable_tex_desc_fields()
709 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode); in si_set_mutable_tex_desc_fields()
712 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode); in si_set_mutable_tex_desc_fields()
919 S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode) | in gfx10_make_texture_descriptor()
1106 fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode); in si_make_texture_descriptor()
1230 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode; in radv_init_metadata()
Dradv_radeon_winsys.h148 unsigned swizzle_mode:5; member
/external/mesa3d/src/gallium/drivers/radeon/
Dradeon_vcn_enc_2_0.c300 enc->enc_pic.ctx_buf.swizzle_mode = 0; in radeon_enc_ctx()
324 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode); in radeon_enc_ctx()
Dradeon_uvd_enc.h296 uint32_t swizzle_mode; member
/external/igt-gpu-tools/lib/stubs/drm/
Dintel_bufmgr.c64 uint32_t * swizzle_mode) in drm_intel_bo_get_tiling() argument
Dintel_bufmgr.h163 uint32_t * swizzle_mode);
/external/libdrm/include/drm/
Di915_drm.h1275 __u32 swizzle_mode; member
1292 __u32 swizzle_mode; member
/external/igt-gpu-tools/lib/
Dioctl_wrappers.c158 *swizzle = get_tiling.swizzle_mode; in gem_get_tiling()
160 return get_tiling.phys_swizzle_mode == get_tiling.swizzle_mode; in gem_get_tiling()
/external/igt-gpu-tools/include/drm-uapi/
Di915_drm.h1308 __u32 swizzle_mode; member
1325 __u32 swizzle_mode; member
/external/kernel-headers/original/uapi/drm/
Di915_drm.h1316 __u32 swizzle_mode; member
1333 __u32 swizzle_mode; member
/external/mesa3d/include/drm-uapi/
Di915_drm.h1401 __u32 swizzle_mode; member
1418 __u32 swizzle_mode; member
/external/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_bo.c790 tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, md->u.gfx9.swizzle_mode); in radv_amdgpu_winsys_bo_set_metadata()
835 md->u.gfx9.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); in radv_amdgpu_winsys_bo_get_metadata()

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