1 /**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include "pipe/p_video_codec.h"
29 #include "radeon_vcn_enc.h"
30 #include "radeon_video.h"
31 #include "si_pipe.h"
32 #include "util/u_video.h"
33
34 #include <stdio.h>
35
36 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
37 #define RENCODE_FW_INTERFACE_MINOR_VERSION 1
38
39 #define RENCODE_IB_PARAM_SESSION_INFO 0x00000001
40 #define RENCODE_IB_PARAM_TASK_INFO 0x00000002
41 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003
42 #define RENCODE_IB_PARAM_LAYER_CONTROL 0x00000004
43 #define RENCODE_IB_PARAM_LAYER_SELECT 0x00000005
44 #define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
45 #define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT 0x00000007
46 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x00000008
47 #define RENCODE_IB_PARAM_QUALITY_PARAMS 0x00000009
48 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU 0x0000000a
49 #define RENCODE_IB_PARAM_SLICE_HEADER 0x0000000b
50 #define RENCODE_IB_PARAM_INPUT_FORMAT 0x0000000c
51 #define RENCODE_IB_PARAM_OUTPUT_FORMAT 0x0000000d
52 #define RENCODE_IB_PARAM_ENCODE_PARAMS 0x0000000f
53 #define RENCODE_IB_PARAM_INTRA_REFRESH 0x00000010
54 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x00000011
55 #define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x00000012
56 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER 0x00000015
57
58 #define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL 0x00100001
59 #define RENCODE_HEVC_IB_PARAM_SPEC_MISC 0x00100002
60 #define RENCODE_HEVC_IB_PARAM_LOOP_FILTER 0x00100003
61
62 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL 0x00200001
63 #define RENCODE_H264_IB_PARAM_SPEC_MISC 0x00200002
64 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS 0x00200003
65 #define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER 0x00200004
66
67 #define RENCODE_COLOR_VOLUME_G22_BT709 0
68 #define RENCODE_COLOR_VOLUME_G10_BT2020 3
69
70 #define RENCODE_COLOR_BIT_DEPTH_8_BIT 0
71 #define RENCODE_COLOR_BIT_DEPTH_10_BIT 1
72
73 #define RENCODE_COLOR_PACKING_FORMAT_NV12 0
74 #define RENCODE_COLOR_PACKING_FORMAT_P010 1
75
radeon_enc_quality_params(struct radeon_encoder * enc)76 static void radeon_enc_quality_params(struct radeon_encoder *enc)
77 {
78 enc->enc_pic.quality_params.vbaq_mode = 0;
79 enc->enc_pic.quality_params.scene_change_sensitivity = 0;
80 enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
81 enc->enc_pic.quality_params.two_pass_search_center_map_mode = 0;
82
83 RADEON_ENC_BEGIN(enc->cmd.quality_params);
84 RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
85 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
86 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
87 RADEON_ENC_CS(enc->enc_pic.quality_params.two_pass_search_center_map_mode);
88 RADEON_ENC_END();
89 }
90
radeon_enc_loop_filter_hevc(struct radeon_encoder * enc)91 static void radeon_enc_loop_filter_hevc(struct radeon_encoder *enc)
92 {
93 RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc);
94 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
95 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
96 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
97 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
98 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
99 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
100 RADEON_ENC_CS(1);
101 RADEON_ENC_END();
102 }
103
radeon_enc_nalu_sps_hevc(struct radeon_encoder * enc)104 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
105 {
106 RADEON_ENC_BEGIN(enc->cmd.nalu);
107 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
108 uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
109 int i;
110
111 radeon_enc_reset(enc);
112 radeon_enc_set_emulation_prevention(enc, false);
113 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
114 radeon_enc_code_fixed_bits(enc, 0x4201, 16);
115 radeon_enc_byte_align(enc);
116 radeon_enc_set_emulation_prevention(enc, true);
117 radeon_enc_code_fixed_bits(enc, 0x0, 4);
118 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
119 radeon_enc_code_fixed_bits(enc, 0x1, 1);
120 radeon_enc_code_fixed_bits(enc, 0x0, 2);
121 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
122 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
123
124 if (enc->enc_pic.general_profile_idc == 2)
125 radeon_enc_code_fixed_bits(enc, 0x20000000, 32);
126 else
127 radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
128
129 radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
130 radeon_enc_code_fixed_bits(enc, 0x0, 16);
131 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
132
133 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
134 radeon_enc_code_fixed_bits(enc, 0x0, 2);
135
136 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
137 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
138 radeon_enc_code_fixed_bits(enc, 0x0, 2);
139 }
140
141 radeon_enc_code_ue(enc, 0x0);
142 radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
143 radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
144 radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
145
146 if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) ||
147 (enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) {
148 radeon_enc_code_fixed_bits(enc, 0x1, 1);
149 radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
150 radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
151 radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
152 radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
153 } else
154 radeon_enc_code_fixed_bits(enc, 0x0, 1);
155
156 radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
157 radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
158 radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
159 radeon_enc_code_fixed_bits(enc, 0x0, 1);
160 radeon_enc_code_ue(enc, 1);
161 radeon_enc_code_ue(enc, 0x0);
162 radeon_enc_code_ue(enc, 0x0);
163 radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
164 // Only support CTBSize 64
165 radeon_enc_code_ue(enc,
166 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
167 radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
168 radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
169 radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
170 radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra);
171
172 radeon_enc_code_fixed_bits(enc, 0x0, 1);
173 radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
174 radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
175 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
176
177 radeon_enc_code_ue(enc, 1);
178 radeon_enc_code_ue(enc, 1);
179 radeon_enc_code_ue(enc, 0);
180 radeon_enc_code_ue(enc, 0);
181 radeon_enc_code_fixed_bits(enc, 0x1, 1);
182
183 radeon_enc_code_fixed_bits(enc, 0x0, 1);
184
185 radeon_enc_code_fixed_bits(enc, 0, 1);
186 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1);
187
188 radeon_enc_code_fixed_bits(enc, 0x0, 1);
189
190 radeon_enc_code_fixed_bits(enc, 0x0, 1);
191
192 radeon_enc_code_fixed_bits(enc, 0x1, 1);
193
194 radeon_enc_byte_align(enc);
195 radeon_enc_flush_headers(enc);
196 *size_in_bytes = (enc->bits_output + 7) / 8;
197 RADEON_ENC_END();
198 }
199
radeon_enc_nalu_pps_hevc(struct radeon_encoder * enc)200 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
201 {
202 RADEON_ENC_BEGIN(enc->cmd.nalu);
203 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
204 uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
205 radeon_enc_reset(enc);
206 radeon_enc_set_emulation_prevention(enc, false);
207 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
208 radeon_enc_code_fixed_bits(enc, 0x4401, 16);
209 radeon_enc_byte_align(enc);
210 radeon_enc_set_emulation_prevention(enc, true);
211 radeon_enc_code_ue(enc, 0x0);
212 radeon_enc_code_ue(enc, 0x0);
213 radeon_enc_code_fixed_bits(enc, 0x1, 1);
214 radeon_enc_code_fixed_bits(enc, 0x0, 4);
215 radeon_enc_code_fixed_bits(enc, 0x0, 1);
216 radeon_enc_code_fixed_bits(enc, 0x1, 1);
217 radeon_enc_code_ue(enc, 0x0);
218 radeon_enc_code_ue(enc, 0x0);
219 radeon_enc_code_se(enc, 0x0);
220 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
221 radeon_enc_code_fixed_bits(enc, 0x0, 1);
222 if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE)
223 radeon_enc_code_fixed_bits(enc, 0x0, 1);
224 else {
225 radeon_enc_code_fixed_bits(enc, 0x1, 1);
226 radeon_enc_code_ue(enc, 0x0);
227 }
228 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
229 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
230 radeon_enc_code_fixed_bits(enc, 0x0, 1);
231 radeon_enc_code_fixed_bits(enc, 0x0, 2);
232 radeon_enc_code_fixed_bits(enc, 0x0, 1);
233 radeon_enc_code_fixed_bits(enc, 0x0, 1);
234 radeon_enc_code_fixed_bits(enc, 0x0, 1);
235 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
236 radeon_enc_code_fixed_bits(enc, 0x1, 1);
237 radeon_enc_code_fixed_bits(enc, 0x0, 1);
238 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
239
240 if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
241 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
242 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
243 }
244
245 radeon_enc_code_fixed_bits(enc, 0x0, 1);
246 radeon_enc_code_fixed_bits(enc, 0x0, 1);
247 radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
248 radeon_enc_code_fixed_bits(enc, 0x0, 2);
249
250 radeon_enc_code_fixed_bits(enc, 0x1, 1);
251
252 radeon_enc_byte_align(enc);
253 radeon_enc_flush_headers(enc);
254 *size_in_bytes = (enc->bits_output + 7) / 8;
255 RADEON_ENC_END();
256 }
257
radeon_enc_input_format(struct radeon_encoder * enc)258 static void radeon_enc_input_format(struct radeon_encoder *enc)
259 {
260 RADEON_ENC_BEGIN(enc->cmd.input_format);
261 if (enc->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
262 RADEON_ENC_CS(RENCODE_COLOR_VOLUME_G10_BT2020);
263 RADEON_ENC_CS(0);
264 RADEON_ENC_CS(0);
265 RADEON_ENC_CS(0);
266 RADEON_ENC_CS(0);
267 RADEON_ENC_CS(RENCODE_COLOR_BIT_DEPTH_10_BIT);
268 RADEON_ENC_CS(RENCODE_COLOR_PACKING_FORMAT_P010);
269 } else {
270 RADEON_ENC_CS(RENCODE_COLOR_VOLUME_G22_BT709);
271 RADEON_ENC_CS(0);
272 RADEON_ENC_CS(0);
273 RADEON_ENC_CS(0);
274 RADEON_ENC_CS(0);
275 RADEON_ENC_CS(RENCODE_COLOR_BIT_DEPTH_8_BIT);
276 RADEON_ENC_CS(RENCODE_COLOR_PACKING_FORMAT_NV12);
277 }
278 RADEON_ENC_END();
279 }
280
radeon_enc_output_format(struct radeon_encoder * enc)281 static void radeon_enc_output_format(struct radeon_encoder *enc)
282 {
283 RADEON_ENC_BEGIN(enc->cmd.output_format);
284 if (enc->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
285 RADEON_ENC_CS(RENCODE_COLOR_VOLUME_G10_BT2020);
286 RADEON_ENC_CS(0);
287 RADEON_ENC_CS(0);
288 RADEON_ENC_CS(RENCODE_COLOR_BIT_DEPTH_10_BIT);
289 } else {
290 RADEON_ENC_CS(RENCODE_COLOR_VOLUME_G22_BT709);
291 RADEON_ENC_CS(0);
292 RADEON_ENC_CS(0);
293 RADEON_ENC_CS(RENCODE_COLOR_BIT_DEPTH_8_BIT);
294 }
295 RADEON_ENC_END();
296 }
297
radeon_enc_ctx(struct radeon_encoder * enc)298 static void radeon_enc_ctx(struct radeon_encoder *enc)
299 {
300 enc->enc_pic.ctx_buf.swizzle_mode = 0;
301
302 uint32_t aligned_width = enc->enc_pic.session_init.aligned_picture_width;
303 uint32_t aligned_height = enc->enc_pic.session_init.aligned_picture_height;
304
305 enc->enc_pic.ctx_buf.rec_luma_pitch = align(aligned_width, enc->alignment);
306 enc->enc_pic.ctx_buf.rec_chroma_pitch = align(aligned_width, enc->alignment);
307
308 int luma_size = enc->enc_pic.ctx_buf.rec_luma_pitch * align(aligned_height, enc->alignment);
309 if (enc->enc_pic.bit_depth_luma_minus8 == 2)
310 luma_size *= 2;
311 int chroma_size = align(luma_size / 2, enc->alignment);
312 int offset = 0;
313
314 enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2;
315 for (int i = 0; i < enc->enc_pic.ctx_buf.num_reconstructed_pictures; i++) {
316 enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset = offset;
317 offset += luma_size;
318 enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset = offset;
319 offset += chroma_size;
320 }
321
322 RADEON_ENC_BEGIN(enc->cmd.ctx);
323 RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0);
324 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
325 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
326 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
327 RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
328
329 for (int i = 0; i < enc->enc_pic.ctx_buf.num_reconstructed_pictures; i++) {
330 RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset);
331 RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset);
332 }
333
334 for (int i = 0; i < 136; i++)
335 RADEON_ENC_CS(0x00000000);
336
337 RADEON_ENC_END();
338 }
339
encode(struct radeon_encoder * enc)340 static void encode(struct radeon_encoder *enc)
341 {
342 enc->session_info(enc);
343 enc->total_task_size = 0;
344 enc->task_info(enc, enc->need_feedback);
345
346 enc->encode_headers(enc);
347 enc->ctx(enc);
348 enc->bitstream(enc);
349 enc->feedback(enc);
350 enc->intra_refresh(enc);
351 enc->input_format(enc);
352 enc->output_format(enc);
353
354 enc->op_speed(enc);
355 enc->op_enc(enc);
356 *enc->p_task_size = (enc->total_task_size);
357 }
358
radeon_enc_2_0_init(struct radeon_encoder * enc)359 void radeon_enc_2_0_init(struct radeon_encoder *enc)
360 {
361 radeon_enc_1_2_init(enc);
362 enc->encode = encode;
363 enc->ctx = radeon_enc_ctx;
364 enc->quality_params = radeon_enc_quality_params;
365 enc->input_format = radeon_enc_input_format;
366 enc->output_format = radeon_enc_output_format;
367
368 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
369 enc->deblocking_filter = radeon_enc_loop_filter_hevc;
370 enc->nalu_sps = radeon_enc_nalu_sps_hevc;
371 enc->nalu_pps = radeon_enc_nalu_pps_hevc;
372 }
373
374 enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO;
375 enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO;
376 enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT;
377 enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
378 enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
379 enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
380 enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
381 enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE;
382 enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
383 enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
384 enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
385 enc->cmd.input_format = RENCODE_IB_PARAM_INPUT_FORMAT;
386 enc->cmd.output_format = RENCODE_IB_PARAM_OUTPUT_FORMAT;
387 enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
388 enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
389 enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
390 enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
391 enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
392 enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
393 enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
394 enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_LOOP_FILTER;
395 enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
396 enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
397 enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
398 enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
399
400 enc->enc_pic.session_info.interface_version =
401 ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
402 (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
403 }
404