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Searched refs:sxtl2 (Results 1 – 25 of 25) sorted by relevance

/external/llvm/test/MC/AArch64/
Dneon-sxtl.s20 sxtl2 v0.8h, v1.16b
21 sxtl2 v0.4s, v1.8h
22 sxtl2 v0.2d, v1.4s
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-sxtl.s20 sxtl2 v0.8h, v1.16b
21 sxtl2 v0.4s, v1.8h
22 sxtl2 v0.2d, v1.4s
/external/v8/src/execution/arm64/
Dsimulator-logic-arm64.cc1361 LogicVRegister extendedreg = sxtl2(vform, temp2, src); in sshll2()
2096 LogicVRegister Simulator::sxtl2(VectorFormat vform, LogicVRegister dst, in sxtl2() function in v8::internal::Simulator
2373 sxtl2(vform, temp1, src1); in saddl2()
2374 sxtl2(vform, temp2, src2); in saddl2()
2392 sxtl2(vform, temp, src2); in saddw2()
2449 sxtl2(vform, temp1, src1); in ssubl2()
2450 sxtl2(vform, temp2, src2); in ssubl2()
2468 sxtl2(vform, temp, src2); in ssubw2()
2507 sxtl2(vform, temp1, src1); in sabal2()
2508 sxtl2(vform, temp2, src2); in sabal2()
[all …]
Dsimulator-arm64.h1774 LogicVRegister sxtl2(VectorFormat vform, LogicVRegister dst,
/external/vixl/src/aarch64/
Dlogic-aarch64.cc1480 LogicVRegister extendedreg = sxtl2(vform, temp2, src); in sshll2()
2557 LogicVRegister Simulator::sxtl2(VectorFormat vform, in sxtl2() function in vixl::aarch64::Simulator
2913 sxtl2(vform, temp1, src1); in saddl2()
2914 sxtl2(vform, temp2, src2); in saddl2()
2936 sxtl2(vform, temp, src2); in saddw2()
3005 sxtl2(vform, temp1, src1); in ssubl2()
3006 sxtl2(vform, temp2, src2); in ssubl2()
3028 sxtl2(vform, temp, src2); in ssubw2()
3075 sxtl2(vform, temp1, src1); in sabal2()
3076 sxtl2(vform, temp2, src2); in sabal2()
[all …]
Dsimulator-aarch64.h2436 LogicVRegister sxtl2(VectorFormat vform,
Dassembler-aarch64.h3009 void sxtl2(const VRegister& vd, const VRegister& vn);
Dmacro-assembler-aarch64.h2819 V(sxtl2, Sxtl2) \
Dassembler-aarch64.cc4983 void Assembler::sxtl2(const VRegister& vd, const VRegister& vn) { in sxtl2() function in vixl::aarch64::Assembler
/external/libhevc/common/arm64/
Dihevc_intra_pred_luma_vert.s206 sxtl2 v28.8h, v26.16b
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td4877 // Vector shift sxtl2 aliases
4878 def : InstAlias<"sxtl2.8h $dst, $src1",
4880 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4882 def : InstAlias<"sxtl2.4s $dst, $src1",
4884 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4886 def : InstAlias<"sxtl2.2d $dst, $src1",
4888 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td5247 // Vector shift sxtl2 aliases
5248 def : InstAlias<"sxtl2.8h $dst, $src1",
5250 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
5252 def : InstAlias<"sxtl2.4s $dst, $src1",
5254 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
5256 def : InstAlias<"sxtl2.2d $dst, $src1",
5258 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
/external/v8/src/codegen/arm64/
Dmacro-assembler-arm64.h310 V(sxtl2, Sxtl2) \
Dassembler-arm64.h1952 void sxtl2(const VRegister& vd, const VRegister& vn);
Dassembler-arm64.cc1656 void Assembler::sxtl2(const VRegister& vd, const VRegister& vn) { in sxtl2() function in v8::internal::Assembler
/external/vixl/test/test-trace-reference/
Dlog-disasm1795 0x~~~~~~~~~~~~~~~~ 4f20a4e6 sxtl2 v6.2d, v7.4s
1796 0x~~~~~~~~~~~~~~~~ 4f10a769 sxtl2 v9.4s, v27.8h
1797 0x~~~~~~~~~~~~~~~~ 4f08a610 sxtl2 v16.8h, v16.16b
Dlog-disasm-colour1795 0x~~~~~~~~~~~~~~~~ 4f20a4e6 sxtl2 v6.2d, v7.4s
1796 0x~~~~~~~~~~~~~~~~ 4f10a769 sxtl2 v9.4s, v27.8h
1797 0x~~~~~~~~~~~~~~~~ 4f08a610 sxtl2 v16.8h, v16.16b
Dlog-cpufeatures-custom1794 0x~~~~~~~~~~~~~~~~ 4f20a4e6 sxtl2 v6.2d, v7.4s ### {NEON} ###
1795 0x~~~~~~~~~~~~~~~~ 4f10a769 sxtl2 v9.4s, v27.8h ### {NEON} ###
1796 0x~~~~~~~~~~~~~~~~ 4f08a610 sxtl2 v16.8h, v16.16b ### {NEON} ###
Dlog-cpufeatures1794 0x~~~~~~~~~~~~~~~~ 4f20a4e6 sxtl2 v6.2d, v7.4s // Needs: NEON
1795 0x~~~~~~~~~~~~~~~~ 4f10a769 sxtl2 v9.4s, v27.8h // Needs: NEON
1796 0x~~~~~~~~~~~~~~~~ 4f08a610 sxtl2 v16.8h, v16.16b // Needs: NEON
Dlog-cpufeatures-colour1794 0x~~~~~~~~~~~~~~~~ 4f20a4e6 sxtl2 v6.2d, v7.4s NEON
1795 0x~~~~~~~~~~~~~~~~ 4f10a769 sxtl2 v9.4s, v27.8h NEON
1796 0x~~~~~~~~~~~~~~~~ 4f08a610 sxtl2 v16.8h, v16.16b NEON
Dlog-all4893 0x~~~~~~~~~~~~~~~~ 4f20a4e6 sxtl2 v6.2d, v7.4s
4895 0x~~~~~~~~~~~~~~~~ 4f10a769 sxtl2 v9.4s, v27.8h
4897 0x~~~~~~~~~~~~~~~~ 4f08a610 sxtl2 v16.8h, v16.16b
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc2132 __ sxtl2(v6.V2D(), v7.V4S()); in GenerateTestSequenceNEON() local
2133 __ sxtl2(v9.V4S(), v27.V8H()); in GenerateTestSequenceNEON() local
2134 __ sxtl2(v16.V8H(), v16.V16B()); in GenerateTestSequenceNEON() local
Dtest-cpu-features-aarch64.cc2405 TEST_NEON(sxtl2_0, sxtl2(v0.V8H(), v1.V16B()))
2406 TEST_NEON(sxtl2_1, sxtl2(v0.V4S(), v1.V8H()))
2407 TEST_NEON(sxtl2_2, sxtl2(v0.V2D(), v1.V4S()))
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc11928 "th\004sxtl\005sxtl2\004sxtw\003sys\004sysl\003tbl\004tbnz\003tbx\003tbz"
17711 …{ 5234 /* sxtl2 */, AArch64::SSHLLv4i32_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
17712 …{ 5234 /* sxtl2 */, AArch64::SSHLLv8i16_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
17713 …{ 5234 /* sxtl2 */, AArch64::SSHLLv16i8_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
17714 …{ 5234 /* sxtl2 */, AArch64::SSHLLv4i32_shift, Convert__VectorReg1281_0__VectorReg1281_2__imm_95_0…
17715 …{ 5234 /* sxtl2 */, AArch64::SSHLLv8i16_shift, Convert__VectorReg1281_0__VectorReg1281_2__imm_95_0…
17716 …{ 5234 /* sxtl2 */, AArch64::SSHLLv16i8_shift, Convert__VectorReg1281_0__VectorReg1281_2__imm_95_0…
24180 …{ 5234 /* sxtl2 */, AArch64::SSHLLv4i32_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
24181 …{ 5234 /* sxtl2 */, AArch64::SSHLLv8i16_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
24182 …{ 5234 /* sxtl2 */, AArch64::SSHLLv16i8_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
[all …]
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md5567 void sxtl2(const VRegister& vd, const VRegister& vn)