Searched refs:tzdram_base (Results 1 – 10 of 10) sorted by relevance
170 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; in bl31_early_platform_setup2()181 if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) && in bl31_early_platform_setup2()228 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, in bl31_early_platform_setup2()241 tzdram_start = plat_bl31_params_from_bl2.tzdram_base; in bl31_early_platform_setup2()242 tzdram_end = plat_bl31_params_from_bl2.tzdram_base + in bl31_early_platform_setup2()426 mmap_add_region(params_from_bl2->tzdram_base, in bl31_plat_arch_setup()427 params_from_bl2->tzdram_base, in bl31_plat_arch_setup()
268 tegra_memctrl_tzdram_setup(plat_params->tzdram_base, in tegra_pwr_domain_on_finish()
39 memcpy((void *)((uintptr_t)params_from_bl2->tzdram_base), in plat_secondary_setup()44 addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64; in plat_secondary_setup()45 addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU); in plat_secondary_setup()
161 smmu_ctx_base = params_from_bl2->tzdram_base + in tegra_soc_pwr_domain_suspend()312 val = params_from_bl2->tzdram_base + in tegra_soc_pwr_domain_power_down_wfi()
46 (void)memcpy16((void *)(uintptr_t)params_from_bl2->tzdram_base, in plat_secondary_setup()51 addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64; in plat_secondary_setup()52 addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU); in plat_secondary_setup()
127 smmu_ctx_base = params_from_bl2->tzdram_base + in tegra_soc_pwr_domain_suspend()283 val = params_from_bl2->tzdram_base + in tegra_soc_pwr_domain_power_down_wfi()
82 uint64_t tzdram_base = params_from_bl2->tzdram_base; in tegra_smmu_save_context() local83 uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size; in tegra_smmu_save_context()93 assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end)); in tegra_smmu_save_context()
190 assert(plat_params->tzdram_base > plat_params->sc7entry_fw_base); in plat_late_platform_setup()194 assert(sc7entry_end < plat_params->tzdram_base); in plat_late_platform_setup()197 offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base; in plat_late_platform_setup()
473 offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base; in tegra_soc_pwr_domain_on_finish()
43 uint64_t tzdram_base; member