1 /*
2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_helpers.h>
8 #include <common/debug.h>
9 #include <lib/mmio.h>
10 #include <mce.h>
11 #include <string.h>
12 #include <tegra194_private.h>
13 #include <tegra_def.h>
14 #include <tegra_private.h>
15
16 #define MISCREG_AA64_RST_LOW 0x2004U
17 #define MISCREG_AA64_RST_HIGH 0x2008U
18
19 #define CPU_RESET_MODE_AA64 1U
20
21 /*******************************************************************************
22 * Setup secondary CPU vectors
23 ******************************************************************************/
plat_secondary_setup(void)24 void plat_secondary_setup(void)
25 {
26 uint32_t addr_low, addr_high;
27 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
28 uint64_t cpu_reset_handler_base, cpu_reset_handler_size;
29
30 INFO("Setting up secondary CPU boot\n");
31
32 /*
33 * The BL31 code resides in the TZSRAM which loses state
34 * when we enter System Suspend. Copy the wakeup trampoline
35 * code to TZDRAM to help us exit from System Suspend.
36 */
37 cpu_reset_handler_base = tegra194_get_cpu_reset_handler_base();
38 cpu_reset_handler_size = tegra194_get_cpu_reset_handler_size();
39 memcpy((void *)((uintptr_t)params_from_bl2->tzdram_base),
40 (void *)((uintptr_t)cpu_reset_handler_base),
41 cpu_reset_handler_size);
42
43 /* TZDRAM base will be used as the "resume" address */
44 addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64;
45 addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU);
46
47 /* write lower 32 bits first, then the upper 11 bits */
48 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low);
49 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high);
50
51 /* save reset vector to be used during SYSTEM_SUSPEND exit */
52 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO,
53 addr_low);
54 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI,
55 addr_high);
56 }
57