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Searched refs:uxtl2 (Results 1 – 24 of 24) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-uxtl.s20 uxtl2 v0.8h, v1.16b
21 uxtl2 v0.4s, v1.8h
22 uxtl2 v0.2d, v1.4s
/external/llvm/test/MC/AArch64/
Dneon-uxtl.s20 uxtl2 v0.8h, v1.16b
21 uxtl2 v0.4s, v1.8h
22 uxtl2 v0.2d, v1.4s
/external/v8/src/execution/arm64/
Dsimulator-logic-arm64.cc1391 LogicVRegister extendedreg = uxtl2(vform, temp2, src); in ushll2()
2084 LogicVRegister Simulator::uxtl2(VectorFormat vform, LogicVRegister dst, in uxtl2() function in v8::internal::Simulator
2335 uxtl2(vform, temp1, src1); in uaddl2()
2336 uxtl2(vform, temp2, src2); in uaddl2()
2354 uxtl2(vform, temp, src2); in uaddw2()
2411 uxtl2(vform, temp1, src1); in usubl2()
2412 uxtl2(vform, temp2, src2); in usubl2()
2430 uxtl2(vform, temp, src2); in usubw2()
2487 uxtl2(vform, temp1, src1); in uabal2()
2488 uxtl2(vform, temp2, src2); in uabal2()
[all …]
Dsimulator-arm64.h1770 LogicVRegister uxtl2(VectorFormat vform, LogicVRegister dst,
/external/vixl/src/aarch64/
Dlogic-aarch64.cc1520 LogicVRegister extendedreg = uxtl2(vform, temp2, src); in ushll2()
2543 LogicVRegister Simulator::uxtl2(VectorFormat vform, in uxtl2() function in vixl::aarch64::Simulator
2867 uxtl2(vform, temp1, src1); in uaddl2()
2868 uxtl2(vform, temp2, src2); in uaddl2()
2890 uxtl2(vform, temp, src2); in uaddw2()
2959 uxtl2(vform, temp1, src1); in usubl2()
2960 uxtl2(vform, temp2, src2); in usubl2()
2982 uxtl2(vform, temp, src2); in usubw2()
3051 uxtl2(vform, temp1, src1); in uabal2()
3052 uxtl2(vform, temp2, src2); in uabal2()
[all …]
Dsimulator-aarch64.h2430 LogicVRegister uxtl2(VectorFormat vform,
Dassembler-aarch64.h3027 void uxtl2(const VRegister& vd, const VRegister& vn);
Dmacro-assembler-aarch64.h2831 V(uxtl2, Uxtl2) \
Dassembler-aarch64.cc5009 void Assembler::uxtl2(const VRegister& vd, const VRegister& vn) { in uxtl2() function in vixl::aarch64::Assembler
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td4905 // Vector shift uxtl2 aliases
4906 def : InstAlias<"uxtl2.8h $dst, $src1",
4908 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4910 def : InstAlias<"uxtl2.4s $dst, $src1",
4912 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4914 def : InstAlias<"uxtl2.2d $dst, $src1",
4916 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td5275 // Vector shift uxtl2 aliases
5276 def : InstAlias<"uxtl2.8h $dst, $src1",
5278 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
5280 def : InstAlias<"uxtl2.4s $dst, $src1",
5282 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
5284 def : InstAlias<"uxtl2.2d $dst, $src1",
5286 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
/external/v8/src/codegen/arm64/
Dmacro-assembler-arm64.h322 V(uxtl2, Uxtl2) \
Dassembler-arm64.h1970 void uxtl2(const VRegister& vd, const VRegister& vn);
Dassembler-arm64.cc1674 void Assembler::uxtl2(const VRegister& vd, const VRegister& vn) { in uxtl2() function in v8::internal::Assembler
/external/vixl/test/test-trace-reference/
Dlog-disasm2130 0x~~~~~~~~~~~~~~~~ 6f20a606 uxtl2 v6.2d, v16.4s
2131 0x~~~~~~~~~~~~~~~~ 6f10a696 uxtl2 v22.4s, v20.8h
2132 0x~~~~~~~~~~~~~~~~ 6f08a6b4 uxtl2 v20.8h, v21.16b
Dlog-disasm-colour2130 0x~~~~~~~~~~~~~~~~ 6f20a606 uxtl2 v6.2d, v16.4s
2131 0x~~~~~~~~~~~~~~~~ 6f10a696 uxtl2 v22.4s, v20.8h
2132 0x~~~~~~~~~~~~~~~~ 6f08a6b4 uxtl2 v20.8h, v21.16b
Dlog-cpufeatures-custom2129 0x~~~~~~~~~~~~~~~~ 6f20a606 uxtl2 v6.2d, v16.4s ### {NEON} ###
2130 0x~~~~~~~~~~~~~~~~ 6f10a696 uxtl2 v22.4s, v20.8h ### {NEON} ###
2131 0x~~~~~~~~~~~~~~~~ 6f08a6b4 uxtl2 v20.8h, v21.16b ### {NEON} ###
Dlog-cpufeatures2129 0x~~~~~~~~~~~~~~~~ 6f20a606 uxtl2 v6.2d, v16.4s // Needs: NEON
2130 0x~~~~~~~~~~~~~~~~ 6f10a696 uxtl2 v22.4s, v20.8h // Needs: NEON
2131 0x~~~~~~~~~~~~~~~~ 6f08a6b4 uxtl2 v20.8h, v21.16b // Needs: NEON
Dlog-cpufeatures-colour2129 0x~~~~~~~~~~~~~~~~ 6f20a606 uxtl2 v6.2d, v16.4s NEON
2130 0x~~~~~~~~~~~~~~~~ 6f10a696 uxtl2 v22.4s, v20.8h NEON
2131 0x~~~~~~~~~~~~~~~~ 6f08a6b4 uxtl2 v20.8h, v21.16b NEON
Dlog-all5563 0x~~~~~~~~~~~~~~~~ 6f20a606 uxtl2 v6.2d, v16.4s
5565 0x~~~~~~~~~~~~~~~~ 6f10a696 uxtl2 v22.4s, v20.8h
5567 0x~~~~~~~~~~~~~~~~ 6f08a6b4 uxtl2 v20.8h, v21.16b
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc2472 __ uxtl2(v6.V2D(), v16.V4S()); in GenerateTestSequenceNEON() local
2473 __ uxtl2(v22.V4S(), v20.V8H()); in GenerateTestSequenceNEON() local
2474 __ uxtl2(v20.V8H(), v21.V16B()); in GenerateTestSequenceNEON() local
Dtest-cpu-features-aarch64.cc2747 TEST_NEON(uxtl2_0, uxtl2(v0.V8H(), v1.V16B()))
2748 TEST_NEON(uxtl2_1, uxtl2(v0.V4S(), v1.V8H()))
2749 TEST_NEON(uxtl2_2, uxtl2(v0.V2D(), v1.V4S()))
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc11939 "bw\006usubw2\007uunpkhi\007uunpklo\004uxtb\004uxth\004uxtl\005uxtl2\004"
18324 …{ 5794 /* uxtl2 */, AArch64::USHLLv4i32_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
18325 …{ 5794 /* uxtl2 */, AArch64::USHLLv8i16_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
18326 …{ 5794 /* uxtl2 */, AArch64::USHLLv16i8_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
18327 …{ 5794 /* uxtl2 */, AArch64::USHLLv4i32_shift, Convert__VectorReg1281_0__VectorReg1281_2__imm_95_0…
18328 …{ 5794 /* uxtl2 */, AArch64::USHLLv8i16_shift, Convert__VectorReg1281_0__VectorReg1281_2__imm_95_0…
18329 …{ 5794 /* uxtl2 */, AArch64::USHLLv16i8_shift, Convert__VectorReg1281_0__VectorReg1281_2__imm_95_0…
24793 …{ 5794 /* uxtl2 */, AArch64::USHLLv4i32_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
24794 …{ 5794 /* uxtl2 */, AArch64::USHLLv8i16_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
24795 …{ 5794 /* uxtl2 */, AArch64::USHLLv16i8_shift, Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0…
[all …]
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md6151 void uxtl2(const VRegister& vd, const VRegister& vn)