/external/llvm/test/CodeGen/SystemZ/ |
D | asm-17.ll | 6 ; Test i32 GPRs. 17 ; Test i64 GPRs. 63 ; Test clobbers of GPRs and CC.
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D | args-08.ll | 5 ; Up to four integer return values fit into GPRs. 32 ; Up to four floating-point return values fit into GPRs.
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D | fp-move-02.ll | 1 ; Test moves between FPRs and GPRs. The 32-bit cases test the z10 11 ; Test 32-bit moves from GPRs to FPRs. The GPR must be moved into the high 57 ; Test 64-bit moves from GPRs to FPRs. 65 ; Test 128-bit moves from GPRs to FPRs. i128 isn't a legitimate type, 80 ; Test 32-bit moves from FPRs to GPRs. The high 32 bits of the FPR should 90 ; Test 64-bit moves from FPRs to GPRs. 98 ; Test 128-bit moves from FPRs to GPRs, with the same restriction as f6.
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D | frame-05.ll | 1 ; Test saving and restoring of call-saved GPRs. 5 ; This function should require all GPRs, but no other spill slots. The caller 81 ; Like f1, but requires one fewer GPR. We allocate the call-saved GPRs 188 ; This function should use all call-clobbered GPRs but no call-saved ones.
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D | int-move-01.ll | 1 ; Test moves between GPRs.
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D | frame-06.ll | 7 ; This function should require all GPRs, but no other spill slots. The caller 78 ; Like f1, but requires one fewer GPR. We allocate the call-saved GPRs 185 ; This function should use all call-clobbered GPRs but no call-saved ones.
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/ |
D | asm-17.ll | 6 ; Test i32 GPRs. 17 ; Test i64 GPRs. 63 ; Test clobbers of GPRs and CC.
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D | fp-move-13.ll | 21 ; Test 128-bit moves from GPRs to VRs. i128 isn't a legitimate type, 34 ; Test 128-bit moves from VRs to GPRs, with the same restriction as f2.
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D | args-08.ll | 5 ; Up to four integer return values fit into GPRs. 32 ; Up to four floating-point return values fit into GPRs.
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D | fp-move-02.ll | 1 ; Test moves between FPRs and GPRs. The 32-bit cases test the z10 11 ; Test 32-bit moves from GPRs to FPRs. The GPR must be moved into the high 57 ; Test 64-bit moves from GPRs to FPRs. 65 ; Test 128-bit moves from GPRs to FPRs. i128 isn't a legitimate type, 80 ; Test 32-bit moves from FPRs to GPRs. The high 32 bits of the FPR should 90 ; Test 64-bit moves from FPRs to GPRs. 98 ; Test 128-bit moves from FPRs to GPRs, with the same restriction as f6.
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D | frame-05.ll | 1 ; Test saving and restoring of call-saved GPRs. 5 ; This function should require all GPRs, but no other spill slots. The caller 81 ; Like f1, but requires one fewer GPR. We allocate the call-saved GPRs 188 ; This function should use all call-clobbered GPRs but no call-saved ones.
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D | int-move-01.ll | 1 ; Test moves between GPRs.
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D | frame-06.ll | 7 ; This function should require all GPRs, but no other spill slots. The caller 78 ; Like f1, but requires one fewer GPR. We allocate the call-saved GPRs 185 ; This function should use all call-clobbered GPRs but no call-saved ones.
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
D | inlineasm-operand-implicit-cast.ll | 85 ; Check support for returning several floats in GPRs with matching float inputs 98 ; Check support for returning several double in GPRs with matching double input 111 ; Check support for returning several float in specific GPRs with matching 124 ; Check support for returning several double in specific GPRs with matching 235 ; Check support for returning several floats in GPRs with matching float inputs 253 ; Check support for returning several double in GPRs with matching double input 271 ; Check support for returning several float in specific GPRs with matching 289 ; Check support for returning several double in specific GPRs with matching
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/external/llvm/test/CodeGen/X86/ |
D | mmx-copy-gprs.ll | 6 ; This test should use GPRs to copy the mmx value, not MMX regs. Using mmx regs,
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
D | mmx-copy-gprs.ll | 6 ; This test should use GPRs to copy the mmx value, not MMX regs. Using mmx regs,
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/external/libunwind_llvm/src/ |
D | Registers.hpp | 79 struct GPRs { struct in libunwind::Registers_x86 98 GPRs _registers; 286 struct GPRs { struct in libunwind::Registers_x86_64 312 GPRs _registers; 1799 struct GPRs { struct in libunwind::Registers_arm64 1808 GPRs _registers; 1820 static_assert(sizeof(GPRs) == 0x110, in Registers_arm64() 1823 static_cast<const uint8_t *>(registers) + sizeof(GPRs), in Registers_arm64() 2099 struct GPRs { struct in libunwind::Registers_arm 2121 GPRs _registers;
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/external/llvm/test/CodeGen/Thumb/ |
D | 2011-06-16-NoGPRs.ll | 5 ; register, but we cannot have live GPRs in thumb mode because we don't know how
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb/ |
D | 2011-06-16-NoGPRs.ll | 5 ; register, but we cannot have live GPRs in thumb mode because we don't know how
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/external/llvm/test/CodeGen/PowerPC/ |
D | ppc64-align-long-double.ll | 5 ; argument comes in in GPR3; GPR4 is skipped; GPRs 5 and 6 contain
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/external/libffi/src/powerpc/ |
D | darwin_closure.S | 39 ; Define some pseudo-opcodes for size-independent load & store of GPRs ... 45 ; ... and the size of GPRs and their storage indicator.
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/external/python/cpython2/Modules/_ctypes/libffi/src/powerpc/ |
D | darwin_closure.S | 39 ; Define some pseudo-opcodes for size-independent load & store of GPRs ... 45 ; ... and the size of GPRs and their storage indicator.
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/external/swiftshader/third_party/subzero/src/ |
D | IceInstX8664.def | 21 // Scratch GPRs: rax, rcx, rdx, rsi, rdi, r8, r9, r10, r11 22 // Callee-save GPRs: rbx, rbp, r12, r13, r14, r15 26 // Scratch GPRs: rax, rcx, rdx, r8, r9, r10, r11 27 // Callee-save GPRs: rbx, rbp, rsi, rdi, r12, r13, r14, r15
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/ |
D | avoid-predspill.ll | 3 ; This checks that predicate registers are moved to GPRs instead of spilling
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/external/llvm/test/CodeGen/Hexagon/ |
D | avoid-predspill.ll | 3 ; This checks that predicate registers are moved to GPRs instead of spilling
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