| /external/u-boot/arch/arm/mach-sunxi/dram_timings/ |
| D | h6_lpddr3.c | 29 u8 tfaw = max(ns_to_t(50), 4); in mctl_set_timing_params() local
87 writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, in mctl_set_timing_params()
113 writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]); in mctl_set_timing_params()
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| D | h6_ddr3_1333.c | 50 u8 tfaw = ns_to_t(50); /* JEDEC: 30 ns w/ 1K pages */ in mctl_set_timing_params() local
99 writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, in mctl_set_timing_params()
125 writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]); in mctl_set_timing_params()
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| D | lpddr3_stock.c | 11 u8 tfaw = max(ns_to_t(50), 4); in mctl_set_timing_params() local
53 writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | in mctl_set_timing_params()
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| D | ddr3_1333.c | 11 u8 tfaw = ns_to_t(50); in mctl_set_timing_params() local
57 writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | in mctl_set_timing_params()
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| D | ddr2_v3s.c | 11 u8 tfaw = ns_to_t(50); in mctl_set_timing_params() local
54 writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | in mctl_set_timing_params()
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| /external/u-boot/arch/arm/mach-imx/mx6/ |
| D | ddr.c | 999 u8 twl, txp, tfaw, tcl; in mx6_lpddr2_cfg() local
1044 tfaw = DIV_ROUND_UP(60000, clkper) - 1; in mx6_lpddr2_cfg()
1046 tfaw = DIV_ROUND_UP(50000, clkper) - 1; in mx6_lpddr2_cfg()
1086 debug("tfaw=%d\n", tfaw); in mx6_lpddr2_cfg()
1141 (tfaw << 4) | tcl; in mx6_lpddr2_cfg()
1229 u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; in mx6_ddr3_cfg() local
1304 tfaw = DIV_ROUND_UP(40000, clkper) - 1; in mx6_ddr3_cfg()
1307 tfaw = DIV_ROUND_UP(50000, clkper) - 1; in mx6_ddr3_cfg()
1315 tfaw = DIV_ROUND_UP(37500, clkper) - 1; in mx6_ddr3_cfg()
1318 tfaw = DIV_ROUND_UP(50000, clkper) - 1; in mx6_ddr3_cfg()
[all …]
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| /external/u-boot/arch/arm/mach-sunxi/ |
| D | dram_sun8i_a83t.c | 93 u8 tfaw = ns_to_t(50); in auto_set_timing_para() local
145 tfaw = max(ns_to_t(50), 4); in auto_set_timing_para()
170 reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); in auto_set_timing_para()
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| D | dram_sun8i_a33.c | 93 u8 tfaw = ns_to_t(50); in auto_set_timing_para() local
138 reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); in auto_set_timing_para()
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| /external/u-boot/board/phytec/pcm052/ |
| D | pcm052.c | 103 .tfaw = 18, in dram_init()
158 .tfaw = 16, in dram_init()
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| /external/u-boot/arch/arm/include/asm/arch-vf610/ |
| D | ddrmc-vf610.h | 25 u8 tfaw; member
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| /external/u-boot/arch/arm/include/asm/arch-tegra20/ |
| D | emc.h | 51 u32 tfaw; /* 0x98: EMC_TFAW */ member
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| /external/u-boot/doc/device-tree-bindings/misc/ |
| D | intel,baytrail-fsp.txt | 87 - fsp,dimm-tfaw
150 fsp,dimm-tfaw = <0x14>;
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| /external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/ |
| D | dram_spec_timing.c | 309 pdram_timing->tfaw = in ddr3_get_parameter()
538 pdram_timing->tfaw = (LPDDR2_TFAW_LITTLE_200MHZ * nmhz + 999) in lpddr2_get_parameter()
541 pdram_timing->tfaw = (LPDDR2_TFAW_GREAT_200MHZ * nmhz + 999) in lpddr2_get_parameter()
805 pdram_timing->tfaw = max(8, tmp); in lpddr3_get_parameter()
1188 pdram_timing->tfaw = (LPDDR4_TFAW * nmhz + 999) / 1000; in lpddr4_get_parameter()
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| D | dram_spec_timing.h | 91 uint32_t tfaw; member
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| D | dfs.c | 538 (pdram_timing->tfaw << 24) | in gen_rk3399_ctl_params_f0()
792 (pdram_timing->tfaw << 16) | in gen_rk3399_ctl_params_f1()
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| /external/u-boot/arch/arm/mach-imx/ |
| D | ddrmc-vf610.c | 130 writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) | in ddrmc_ctrl_init_ddr3()
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| /external/u-boot/board/toradex/colibri_vf/ |
| D | colibri_vf.c | 99 .tfaw = 20, in dram_init()
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| /external/u-boot/board/freescale/vf610twr/ |
| D | vf610twr.c | 97 .tfaw = 20, in dram_init()
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| /external/u-boot/arch/x86/dts/ |
| D | conga-qeval20-qa3-e3845.dts | 297 fsp,dimm-tfaw = <22>;
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| D | minnowmax.dts | 314 fsp,dimm-tfaw = <0x14>;
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| D | dfi-bt700.dtsi | 315 fsp,dimm-tfaw = <22>;
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| /external/u-boot/arch/x86/cpu/quark/ |
| D | smc.c | 66 uint8_t trp, trcd, tras, twr, twtr, trrd, trtp, tfaw; in prog_ddr_timing_control() local
94 tfaw = MCEIL(mrc_params->params.faw, tck); in prog_ddr_timing_control()
122 dtr1 |= ((((tfaw + 1) >> 1) - 5) << 16);/* 4 bit DRAM Clock */ in prog_ddr_timing_control()
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