1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI_I915_DRM_H_ 20 #define _UAPI_I915_DRM_H_ 21 #include "drm.h" 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 26 #define I915_ERROR_UEVENT "ERROR" 27 #define I915_RESET_UEVENT "RESET" 28 struct i915_user_extension { 29 __u64 next_extension; 30 __u32 name; 31 __u32 flags; 32 __u32 rsvd[4]; 33 }; 34 enum i915_mocs_table_index { 35 I915_MOCS_UNCACHED, 36 I915_MOCS_PTE, 37 I915_MOCS_CACHED, 38 }; 39 enum drm_i915_gem_engine_class { 40 I915_ENGINE_CLASS_RENDER = 0, 41 I915_ENGINE_CLASS_COPY = 1, 42 I915_ENGINE_CLASS_VIDEO = 2, 43 I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, 44 I915_ENGINE_CLASS_INVALID = - 1 45 }; 46 struct i915_engine_class_instance { 47 __u16 engine_class; 48 __u16 engine_instance; 49 #define I915_ENGINE_CLASS_INVALID_NONE - 1 50 #define I915_ENGINE_CLASS_INVALID_VIRTUAL - 2 51 }; 52 enum drm_i915_pmu_engine_sample { 53 I915_SAMPLE_BUSY = 0, 54 I915_SAMPLE_WAIT = 1, 55 I915_SAMPLE_SEMA = 2 56 }; 57 #define I915_PMU_SAMPLE_BITS (4) 58 #define I915_PMU_SAMPLE_MASK (0xf) 59 #define I915_PMU_SAMPLE_INSTANCE_BITS (8) 60 #define I915_PMU_CLASS_SHIFT (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) 61 #define __I915_PMU_ENGINE(class,instance,sample) ((class) << I915_PMU_CLASS_SHIFT | (instance) << I915_PMU_SAMPLE_BITS | (sample)) 62 #define I915_PMU_ENGINE_BUSY(class,instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY) 63 #define I915_PMU_ENGINE_WAIT(class,instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT) 64 #define I915_PMU_ENGINE_SEMA(class,instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) 65 #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) 66 #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) 67 #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) 68 #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) 69 #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) 70 #define I915_PMU_LAST I915_PMU_RC6_RESIDENCY 71 #define I915_NR_TEX_REGIONS 255 72 #define I915_LOG_MIN_TEX_REGION_SIZE 14 73 typedef struct _drm_i915_init { 74 enum { 75 I915_INIT_DMA = 0x01, 76 I915_CLEANUP_DMA = 0x02, 77 I915_RESUME_DMA = 0x03 78 } func; 79 unsigned int mmio_offset; 80 int sarea_priv_offset; 81 unsigned int ring_start; 82 unsigned int ring_end; 83 unsigned int ring_size; 84 unsigned int front_offset; 85 unsigned int back_offset; 86 unsigned int depth_offset; 87 unsigned int w; 88 unsigned int h; 89 unsigned int pitch; 90 unsigned int pitch_bits; 91 unsigned int back_pitch; 92 unsigned int depth_pitch; 93 unsigned int cpp; 94 unsigned int chipset; 95 } drm_i915_init_t; 96 typedef struct _drm_i915_sarea { 97 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 98 int last_upload; 99 int last_enqueue; 100 int last_dispatch; 101 int ctxOwner; 102 int texAge; 103 int pf_enabled; 104 int pf_active; 105 int pf_current_page; 106 int perf_boxes; 107 int width, height; 108 drm_handle_t front_handle; 109 int front_offset; 110 int front_size; 111 drm_handle_t back_handle; 112 int back_offset; 113 int back_size; 114 drm_handle_t depth_handle; 115 int depth_offset; 116 int depth_size; 117 drm_handle_t tex_handle; 118 int tex_offset; 119 int tex_size; 120 int log_tex_granularity; 121 int pitch; 122 int rotation; 123 int rotated_offset; 124 int rotated_size; 125 int rotated_pitch; 126 int virtualX, virtualY; 127 unsigned int front_tiled; 128 unsigned int back_tiled; 129 unsigned int depth_tiled; 130 unsigned int rotated_tiled; 131 unsigned int rotated2_tiled; 132 int pipeA_x; 133 int pipeA_y; 134 int pipeA_w; 135 int pipeA_h; 136 int pipeB_x; 137 int pipeB_y; 138 int pipeB_w; 139 int pipeB_h; 140 drm_handle_t unused_handle; 141 __u32 unused1, unused2, unused3; 142 __u32 front_bo_handle; 143 __u32 back_bo_handle; 144 __u32 unused_bo_handle; 145 __u32 depth_bo_handle; 146 } drm_i915_sarea_t; 147 #define planeA_x pipeA_x 148 #define planeA_y pipeA_y 149 #define planeA_w pipeA_w 150 #define planeA_h pipeA_h 151 #define planeB_x pipeB_x 152 #define planeB_y pipeB_y 153 #define planeB_w pipeB_w 154 #define planeB_h pipeB_h 155 #define I915_BOX_RING_EMPTY 0x1 156 #define I915_BOX_FLIP 0x2 157 #define I915_BOX_WAIT 0x4 158 #define I915_BOX_TEXTURE_LOAD 0x8 159 #define I915_BOX_LOST_CONTEXT 0x10 160 #define DRM_I915_INIT 0x00 161 #define DRM_I915_FLUSH 0x01 162 #define DRM_I915_FLIP 0x02 163 #define DRM_I915_BATCHBUFFER 0x03 164 #define DRM_I915_IRQ_EMIT 0x04 165 #define DRM_I915_IRQ_WAIT 0x05 166 #define DRM_I915_GETPARAM 0x06 167 #define DRM_I915_SETPARAM 0x07 168 #define DRM_I915_ALLOC 0x08 169 #define DRM_I915_FREE 0x09 170 #define DRM_I915_INIT_HEAP 0x0a 171 #define DRM_I915_CMDBUFFER 0x0b 172 #define DRM_I915_DESTROY_HEAP 0x0c 173 #define DRM_I915_SET_VBLANK_PIPE 0x0d 174 #define DRM_I915_GET_VBLANK_PIPE 0x0e 175 #define DRM_I915_VBLANK_SWAP 0x0f 176 #define DRM_I915_HWS_ADDR 0x11 177 #define DRM_I915_GEM_INIT 0x13 178 #define DRM_I915_GEM_EXECBUFFER 0x14 179 #define DRM_I915_GEM_PIN 0x15 180 #define DRM_I915_GEM_UNPIN 0x16 181 #define DRM_I915_GEM_BUSY 0x17 182 #define DRM_I915_GEM_THROTTLE 0x18 183 #define DRM_I915_GEM_ENTERVT 0x19 184 #define DRM_I915_GEM_LEAVEVT 0x1a 185 #define DRM_I915_GEM_CREATE 0x1b 186 #define DRM_I915_GEM_PREAD 0x1c 187 #define DRM_I915_GEM_PWRITE 0x1d 188 #define DRM_I915_GEM_MMAP 0x1e 189 #define DRM_I915_GEM_SET_DOMAIN 0x1f 190 #define DRM_I915_GEM_SW_FINISH 0x20 191 #define DRM_I915_GEM_SET_TILING 0x21 192 #define DRM_I915_GEM_GET_TILING 0x22 193 #define DRM_I915_GEM_GET_APERTURE 0x23 194 #define DRM_I915_GEM_MMAP_GTT 0x24 195 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 196 #define DRM_I915_GEM_MADVISE 0x26 197 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 198 #define DRM_I915_OVERLAY_ATTRS 0x28 199 #define DRM_I915_GEM_EXECBUFFER2 0x29 200 #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 201 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 202 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 203 #define DRM_I915_GEM_WAIT 0x2c 204 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 205 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 206 #define DRM_I915_GEM_SET_CACHING 0x2f 207 #define DRM_I915_GEM_GET_CACHING 0x30 208 #define DRM_I915_REG_READ 0x31 209 #define DRM_I915_GET_RESET_STATS 0x32 210 #define DRM_I915_GEM_USERPTR 0x33 211 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 212 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 213 #define DRM_I915_PERF_OPEN 0x36 214 #define DRM_I915_PERF_ADD_CONFIG 0x37 215 #define DRM_I915_PERF_REMOVE_CONFIG 0x38 216 #define DRM_I915_QUERY 0x39 217 #define DRM_I915_GEM_VM_CREATE 0x3a 218 #define DRM_I915_GEM_VM_DESTROY 0x3b 219 #define DRM_IOCTL_I915_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 220 #define DRM_IOCTL_I915_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLUSH) 221 #define DRM_IOCTL_I915_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLIP) 222 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 223 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 224 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 225 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 226 #define DRM_IOCTL_I915_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 227 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 228 #define DRM_IOCTL_I915_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 229 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 230 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 231 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 232 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 233 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 234 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 235 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 236 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 237 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 238 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 239 #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) 240 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 241 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 242 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 243 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 244 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 245 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 246 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 247 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 248 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 249 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 250 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 251 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 252 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 253 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 254 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 255 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 256 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 257 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 258 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 259 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 260 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 261 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 262 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 263 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 264 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 265 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 266 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext) 267 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 268 #define DRM_IOCTL_I915_REG_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 269 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 270 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 271 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 272 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 273 #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) 274 #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) 275 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) 276 #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query) 277 #define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control) 278 #define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control) 279 typedef struct drm_i915_batchbuffer { 280 int start; 281 int used; 282 int DR1; 283 int DR4; 284 int num_cliprects; 285 struct drm_clip_rect __user * cliprects; 286 } drm_i915_batchbuffer_t; 287 typedef struct _drm_i915_cmdbuffer { 288 char __user * buf; 289 int sz; 290 int DR1; 291 int DR4; 292 int num_cliprects; 293 struct drm_clip_rect __user * cliprects; 294 } drm_i915_cmdbuffer_t; 295 typedef struct drm_i915_irq_emit { 296 int __user * irq_seq; 297 } drm_i915_irq_emit_t; 298 typedef struct drm_i915_irq_wait { 299 int irq_seq; 300 } drm_i915_irq_wait_t; 301 #define I915_GEM_PPGTT_NONE 0 302 #define I915_GEM_PPGTT_ALIASING 1 303 #define I915_GEM_PPGTT_FULL 2 304 #define I915_PARAM_IRQ_ACTIVE 1 305 #define I915_PARAM_ALLOW_BATCHBUFFER 2 306 #define I915_PARAM_LAST_DISPATCH 3 307 #define I915_PARAM_CHIPSET_ID 4 308 #define I915_PARAM_HAS_GEM 5 309 #define I915_PARAM_NUM_FENCES_AVAIL 6 310 #define I915_PARAM_HAS_OVERLAY 7 311 #define I915_PARAM_HAS_PAGEFLIPPING 8 312 #define I915_PARAM_HAS_EXECBUF2 9 313 #define I915_PARAM_HAS_BSD 10 314 #define I915_PARAM_HAS_BLT 11 315 #define I915_PARAM_HAS_RELAXED_FENCING 12 316 #define I915_PARAM_HAS_COHERENT_RINGS 13 317 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 318 #define I915_PARAM_HAS_RELAXED_DELTA 15 319 #define I915_PARAM_HAS_GEN7_SOL_RESET 16 320 #define I915_PARAM_HAS_LLC 17 321 #define I915_PARAM_HAS_ALIASING_PPGTT 18 322 #define I915_PARAM_HAS_WAIT_TIMEOUT 19 323 #define I915_PARAM_HAS_SEMAPHORES 20 324 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 325 #define I915_PARAM_HAS_VEBOX 22 326 #define I915_PARAM_HAS_SECURE_BATCHES 23 327 #define I915_PARAM_HAS_PINNED_BATCHES 24 328 #define I915_PARAM_HAS_EXEC_NO_RELOC 25 329 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 330 #define I915_PARAM_HAS_WT 27 331 #define I915_PARAM_CMD_PARSER_VERSION 28 332 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 333 #define I915_PARAM_MMAP_VERSION 30 334 #define I915_PARAM_HAS_BSD2 31 335 #define I915_PARAM_REVISION 32 336 #define I915_PARAM_SUBSLICE_TOTAL 33 337 #define I915_PARAM_EU_TOTAL 34 338 #define I915_PARAM_HAS_GPU_RESET 35 339 #define I915_PARAM_HAS_RESOURCE_STREAMER 36 340 #define I915_PARAM_HAS_EXEC_SOFTPIN 37 341 #define I915_PARAM_HAS_POOLED_EU 38 342 #define I915_PARAM_MIN_EU_IN_POOL 39 343 #define I915_PARAM_MMAP_GTT_VERSION 40 344 #define I915_PARAM_HAS_SCHEDULER 41 345 #define I915_SCHEDULER_CAP_ENABLED (1ul << 0) 346 #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) 347 #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) 348 #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) 349 #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) 350 #define I915_PARAM_HUC_STATUS 42 351 #define I915_PARAM_HAS_EXEC_ASYNC 43 352 #define I915_PARAM_HAS_EXEC_FENCE 44 353 #define I915_PARAM_HAS_EXEC_CAPTURE 45 354 #define I915_PARAM_SLICE_MASK 46 355 #define I915_PARAM_SUBSLICE_MASK 47 356 #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 357 #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 358 #define I915_PARAM_HAS_CONTEXT_ISOLATION 50 359 #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 360 #define I915_PARAM_MMAP_GTT_COHERENT 52 361 #define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53 362 #define I915_PARAM_PERF_REVISION 54 363 typedef struct drm_i915_getparam { 364 __s32 param; 365 int __user * value; 366 } drm_i915_getparam_t; 367 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 368 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 369 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 370 #define I915_SETPARAM_NUM_USED_FENCES 4 371 typedef struct drm_i915_setparam { 372 int param; 373 int value; 374 } drm_i915_setparam_t; 375 #define I915_MEM_REGION_AGP 1 376 typedef struct drm_i915_mem_alloc { 377 int region; 378 int alignment; 379 int size; 380 int __user * region_offset; 381 } drm_i915_mem_alloc_t; 382 typedef struct drm_i915_mem_free { 383 int region; 384 int region_offset; 385 } drm_i915_mem_free_t; 386 typedef struct drm_i915_mem_init_heap { 387 int region; 388 int size; 389 int start; 390 } drm_i915_mem_init_heap_t; 391 typedef struct drm_i915_mem_destroy_heap { 392 int region; 393 } drm_i915_mem_destroy_heap_t; 394 #define DRM_I915_VBLANK_PIPE_A 1 395 #define DRM_I915_VBLANK_PIPE_B 2 396 typedef struct drm_i915_vblank_pipe { 397 int pipe; 398 } drm_i915_vblank_pipe_t; 399 typedef struct drm_i915_vblank_swap { 400 drm_drawable_t drawable; 401 enum drm_vblank_seq_type seqtype; 402 unsigned int sequence; 403 } drm_i915_vblank_swap_t; 404 typedef struct drm_i915_hws_addr { 405 __u64 addr; 406 } drm_i915_hws_addr_t; 407 struct drm_i915_gem_init { 408 __u64 gtt_start; 409 __u64 gtt_end; 410 }; 411 struct drm_i915_gem_create { 412 __u64 size; 413 __u32 handle; 414 __u32 pad; 415 }; 416 struct drm_i915_gem_pread { 417 __u32 handle; 418 __u32 pad; 419 __u64 offset; 420 __u64 size; 421 __u64 data_ptr; 422 }; 423 struct drm_i915_gem_pwrite { 424 __u32 handle; 425 __u32 pad; 426 __u64 offset; 427 __u64 size; 428 __u64 data_ptr; 429 }; 430 struct drm_i915_gem_mmap { 431 __u32 handle; 432 __u32 pad; 433 __u64 offset; 434 __u64 size; 435 __u64 addr_ptr; 436 __u64 flags; 437 #define I915_MMAP_WC 0x1 438 }; 439 struct drm_i915_gem_mmap_gtt { 440 __u32 handle; 441 __u32 pad; 442 __u64 offset; 443 }; 444 struct drm_i915_gem_set_domain { 445 __u32 handle; 446 __u32 read_domains; 447 __u32 write_domain; 448 }; 449 struct drm_i915_gem_sw_finish { 450 __u32 handle; 451 }; 452 struct drm_i915_gem_relocation_entry { 453 __u32 target_handle; 454 __u32 delta; 455 __u64 offset; 456 __u64 presumed_offset; 457 __u32 read_domains; 458 __u32 write_domain; 459 }; 460 #define I915_GEM_DOMAIN_CPU 0x00000001 461 #define I915_GEM_DOMAIN_RENDER 0x00000002 462 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 463 #define I915_GEM_DOMAIN_COMMAND 0x00000008 464 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 465 #define I915_GEM_DOMAIN_VERTEX 0x00000020 466 #define I915_GEM_DOMAIN_GTT 0x00000040 467 #define I915_GEM_DOMAIN_WC 0x00000080 468 struct drm_i915_gem_exec_object { 469 __u32 handle; 470 __u32 relocation_count; 471 __u64 relocs_ptr; 472 __u64 alignment; 473 __u64 offset; 474 }; 475 struct drm_i915_gem_execbuffer { 476 __u64 buffers_ptr; 477 __u32 buffer_count; 478 __u32 batch_start_offset; 479 __u32 batch_len; 480 __u32 DR1; 481 __u32 DR4; 482 __u32 num_cliprects; 483 __u64 cliprects_ptr; 484 }; 485 struct drm_i915_gem_exec_object2 { 486 __u32 handle; 487 __u32 relocation_count; 488 __u64 relocs_ptr; 489 __u64 alignment; 490 __u64 offset; 491 #define EXEC_OBJECT_NEEDS_FENCE (1 << 0) 492 #define EXEC_OBJECT_NEEDS_GTT (1 << 1) 493 #define EXEC_OBJECT_WRITE (1 << 2) 494 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1 << 3) 495 #define EXEC_OBJECT_PINNED (1 << 4) 496 #define EXEC_OBJECT_PAD_TO_SIZE (1 << 5) 497 #define EXEC_OBJECT_ASYNC (1 << 6) 498 #define EXEC_OBJECT_CAPTURE (1 << 7) 499 #define __EXEC_OBJECT_UNKNOWN_FLAGS - (EXEC_OBJECT_CAPTURE << 1) 500 __u64 flags; 501 union { 502 __u64 rsvd1; 503 __u64 pad_to_size; 504 }; 505 __u64 rsvd2; 506 }; 507 struct drm_i915_gem_exec_fence { 508 __u32 handle; 509 #define I915_EXEC_FENCE_WAIT (1 << 0) 510 #define I915_EXEC_FENCE_SIGNAL (1 << 1) 511 #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (- (I915_EXEC_FENCE_SIGNAL << 1)) 512 __u32 flags; 513 }; 514 struct drm_i915_gem_execbuffer2 { 515 __u64 buffers_ptr; 516 __u32 buffer_count; 517 __u32 batch_start_offset; 518 __u32 batch_len; 519 __u32 DR1; 520 __u32 DR4; 521 __u32 num_cliprects; 522 __u64 cliprects_ptr; 523 #define I915_EXEC_RING_MASK (0x3f) 524 #define I915_EXEC_DEFAULT (0 << 0) 525 #define I915_EXEC_RENDER (1 << 0) 526 #define I915_EXEC_BSD (2 << 0) 527 #define I915_EXEC_BLT (3 << 0) 528 #define I915_EXEC_VEBOX (4 << 0) 529 #define I915_EXEC_CONSTANTS_MASK (3 << 6) 530 #define I915_EXEC_CONSTANTS_REL_GENERAL (0 << 6) 531 #define I915_EXEC_CONSTANTS_ABSOLUTE (1 << 6) 532 #define I915_EXEC_CONSTANTS_REL_SURFACE (2 << 6) 533 __u64 flags; 534 __u64 rsvd1; 535 __u64 rsvd2; 536 }; 537 #define I915_EXEC_GEN7_SOL_RESET (1 << 8) 538 #define I915_EXEC_SECURE (1 << 9) 539 #define I915_EXEC_IS_PINNED (1 << 10) 540 #define I915_EXEC_NO_RELOC (1 << 11) 541 #define I915_EXEC_HANDLE_LUT (1 << 12) 542 #define I915_EXEC_BSD_SHIFT (13) 543 #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 544 #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 545 #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 546 #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 547 #define I915_EXEC_RESOURCE_STREAMER (1 << 15) 548 #define I915_EXEC_FENCE_IN (1 << 16) 549 #define I915_EXEC_FENCE_OUT (1 << 17) 550 #define I915_EXEC_BATCH_FIRST (1 << 18) 551 #define I915_EXEC_FENCE_ARRAY (1 << 19) 552 #define I915_EXEC_FENCE_SUBMIT (1 << 20) 553 #define __I915_EXEC_UNKNOWN_FLAGS (- (I915_EXEC_FENCE_SUBMIT << 1)) 554 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 555 #define i915_execbuffer2_set_context_id(eb2,context) (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 556 #define i915_execbuffer2_get_context_id(eb2) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 557 struct drm_i915_gem_pin { 558 __u32 handle; 559 __u32 pad; 560 __u64 alignment; 561 __u64 offset; 562 }; 563 struct drm_i915_gem_unpin { 564 __u32 handle; 565 __u32 pad; 566 }; 567 struct drm_i915_gem_busy { 568 __u32 handle; 569 __u32 busy; 570 }; 571 #define I915_CACHING_NONE 0 572 #define I915_CACHING_CACHED 1 573 #define I915_CACHING_DISPLAY 2 574 struct drm_i915_gem_caching { 575 __u32 handle; 576 __u32 caching; 577 }; 578 #define I915_TILING_NONE 0 579 #define I915_TILING_X 1 580 #define I915_TILING_Y 2 581 #define I915_TILING_LAST I915_TILING_Y 582 #define I915_BIT_6_SWIZZLE_NONE 0 583 #define I915_BIT_6_SWIZZLE_9 1 584 #define I915_BIT_6_SWIZZLE_9_10 2 585 #define I915_BIT_6_SWIZZLE_9_11 3 586 #define I915_BIT_6_SWIZZLE_9_10_11 4 587 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 588 #define I915_BIT_6_SWIZZLE_9_17 6 589 #define I915_BIT_6_SWIZZLE_9_10_17 7 590 struct drm_i915_gem_set_tiling { 591 __u32 handle; 592 __u32 tiling_mode; 593 __u32 stride; 594 __u32 swizzle_mode; 595 }; 596 struct drm_i915_gem_get_tiling { 597 __u32 handle; 598 __u32 tiling_mode; 599 __u32 swizzle_mode; 600 __u32 phys_swizzle_mode; 601 }; 602 struct drm_i915_gem_get_aperture { 603 __u64 aper_size; 604 __u64 aper_available_size; 605 }; 606 struct drm_i915_get_pipe_from_crtc_id { 607 __u32 crtc_id; 608 __u32 pipe; 609 }; 610 #define I915_MADV_WILLNEED 0 611 #define I915_MADV_DONTNEED 1 612 #define __I915_MADV_PURGED 2 613 struct drm_i915_gem_madvise { 614 __u32 handle; 615 __u32 madv; 616 __u32 retained; 617 }; 618 #define I915_OVERLAY_TYPE_MASK 0xff 619 #define I915_OVERLAY_YUV_PLANAR 0x01 620 #define I915_OVERLAY_YUV_PACKED 0x02 621 #define I915_OVERLAY_RGB 0x03 622 #define I915_OVERLAY_DEPTH_MASK 0xff00 623 #define I915_OVERLAY_RGB24 0x1000 624 #define I915_OVERLAY_RGB16 0x2000 625 #define I915_OVERLAY_RGB15 0x3000 626 #define I915_OVERLAY_YUV422 0x0100 627 #define I915_OVERLAY_YUV411 0x0200 628 #define I915_OVERLAY_YUV420 0x0300 629 #define I915_OVERLAY_YUV410 0x0400 630 #define I915_OVERLAY_SWAP_MASK 0xff0000 631 #define I915_OVERLAY_NO_SWAP 0x000000 632 #define I915_OVERLAY_UV_SWAP 0x010000 633 #define I915_OVERLAY_Y_SWAP 0x020000 634 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 635 #define I915_OVERLAY_FLAGS_MASK 0xff000000 636 #define I915_OVERLAY_ENABLE 0x01000000 637 struct drm_intel_overlay_put_image { 638 __u32 flags; 639 __u32 bo_handle; 640 __u16 stride_Y; 641 __u16 stride_UV; 642 __u32 offset_Y; 643 __u32 offset_U; 644 __u32 offset_V; 645 __u16 src_width; 646 __u16 src_height; 647 __u16 src_scan_width; 648 __u16 src_scan_height; 649 __u32 crtc_id; 650 __u16 dst_x; 651 __u16 dst_y; 652 __u16 dst_width; 653 __u16 dst_height; 654 }; 655 #define I915_OVERLAY_UPDATE_ATTRS (1 << 0) 656 #define I915_OVERLAY_UPDATE_GAMMA (1 << 1) 657 #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1 << 2) 658 struct drm_intel_overlay_attrs { 659 __u32 flags; 660 __u32 color_key; 661 __s32 brightness; 662 __u32 contrast; 663 __u32 saturation; 664 __u32 gamma0; 665 __u32 gamma1; 666 __u32 gamma2; 667 __u32 gamma3; 668 __u32 gamma4; 669 __u32 gamma5; 670 }; 671 #define I915_SET_COLORKEY_NONE (1 << 0) 672 #define I915_SET_COLORKEY_DESTINATION (1 << 1) 673 #define I915_SET_COLORKEY_SOURCE (1 << 2) 674 struct drm_intel_sprite_colorkey { 675 __u32 plane_id; 676 __u32 min_value; 677 __u32 channel_mask; 678 __u32 max_value; 679 __u32 flags; 680 }; 681 struct drm_i915_gem_wait { 682 __u32 bo_handle; 683 __u32 flags; 684 __s64 timeout_ns; 685 }; 686 struct drm_i915_gem_context_create { 687 __u32 ctx_id; 688 __u32 pad; 689 }; 690 struct drm_i915_gem_context_create_ext { 691 __u32 ctx_id; 692 __u32 flags; 693 #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0) 694 #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1) 695 #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN (- (I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)) 696 __u64 extensions; 697 }; 698 struct drm_i915_gem_context_param { 699 __u32 ctx_id; 700 __u32 size; 701 __u64 param; 702 #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 703 #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 704 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 705 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 706 #define I915_CONTEXT_PARAM_BANNABLE 0x5 707 #define I915_CONTEXT_PARAM_PRIORITY 0x6 708 #define I915_CONTEXT_MAX_USER_PRIORITY 1023 709 #define I915_CONTEXT_DEFAULT_PRIORITY 0 710 #define I915_CONTEXT_MIN_USER_PRIORITY - 1023 711 #define I915_CONTEXT_PARAM_SSEU 0x7 712 #define I915_CONTEXT_PARAM_RECOVERABLE 0x8 713 #define I915_CONTEXT_PARAM_VM 0x9 714 #define I915_CONTEXT_PARAM_ENGINES 0xa 715 #define I915_CONTEXT_PARAM_PERSISTENCE 0xb 716 __u64 value; 717 }; 718 struct drm_i915_gem_context_param_sseu { 719 struct i915_engine_class_instance engine; 720 __u32 flags; 721 #define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0) 722 __u64 slice_mask; 723 __u64 subslice_mask; 724 __u16 min_eus_per_subslice; 725 __u16 max_eus_per_subslice; 726 __u32 rsvd; 727 }; 728 struct i915_context_engines_load_balance { 729 struct i915_user_extension base; 730 __u16 engine_index; 731 __u16 num_siblings; 732 __u32 flags; 733 __u64 mbz64; 734 struct i915_engine_class_instance engines[0]; 735 } __attribute__((packed)); 736 #define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__,N__) struct { struct i915_user_extension base; __u16 engine_index; __u16 num_siblings; __u32 flags; __u64 mbz64; struct i915_engine_class_instance engines[N__]; \ 737 } __attribute__((packed)) name__ 738 struct i915_context_engines_bond { 739 struct i915_user_extension base; 740 struct i915_engine_class_instance master; 741 __u16 virtual_index; 742 __u16 num_bonds; 743 __u64 flags; 744 __u64 mbz64[4]; 745 struct i915_engine_class_instance engines[0]; 746 } __attribute__((packed)); 747 #define I915_DEFINE_CONTEXT_ENGINES_BOND(name__,N__) struct { struct i915_user_extension base; struct i915_engine_class_instance master; __u16 virtual_index; __u16 num_bonds; __u64 flags; __u64 mbz64[4]; struct i915_engine_class_instance engines[N__]; \ 748 } __attribute__((packed)) name__ 749 struct i915_context_param_engines { 750 __u64 extensions; 751 #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 752 #define I915_CONTEXT_ENGINES_EXT_BOND 1 753 struct i915_engine_class_instance engines[0]; 754 } __attribute__((packed)); 755 #define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__,N__) struct { __u64 extensions; struct i915_engine_class_instance engines[N__]; \ 756 } __attribute__((packed)) name__ 757 struct drm_i915_gem_context_create_ext_setparam { 758 #define I915_CONTEXT_CREATE_EXT_SETPARAM 0 759 struct i915_user_extension base; 760 struct drm_i915_gem_context_param param; 761 }; 762 struct drm_i915_gem_context_create_ext_clone { 763 #define I915_CONTEXT_CREATE_EXT_CLONE 1 764 struct i915_user_extension base; 765 __u32 clone_id; 766 __u32 flags; 767 #define I915_CONTEXT_CLONE_ENGINES (1u << 0) 768 #define I915_CONTEXT_CLONE_FLAGS (1u << 1) 769 #define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2) 770 #define I915_CONTEXT_CLONE_SSEU (1u << 3) 771 #define I915_CONTEXT_CLONE_TIMELINE (1u << 4) 772 #define I915_CONTEXT_CLONE_VM (1u << 5) 773 #define I915_CONTEXT_CLONE_UNKNOWN - (I915_CONTEXT_CLONE_VM << 1) 774 __u64 rsvd; 775 }; 776 struct drm_i915_gem_context_destroy { 777 __u32 ctx_id; 778 __u32 pad; 779 }; 780 struct drm_i915_gem_vm_control { 781 __u64 extensions; 782 __u32 flags; 783 __u32 vm_id; 784 }; 785 struct drm_i915_reg_read { 786 __u64 offset; 787 #define I915_REG_READ_8B_WA (1ul << 0) 788 __u64 val; 789 }; 790 struct drm_i915_reset_stats { 791 __u32 ctx_id; 792 __u32 flags; 793 __u32 reset_count; 794 __u32 batch_active; 795 __u32 batch_pending; 796 __u32 pad; 797 }; 798 struct drm_i915_gem_userptr { 799 __u64 user_ptr; 800 __u64 user_size; 801 __u32 flags; 802 #define I915_USERPTR_READ_ONLY 0x1 803 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 804 __u32 handle; 805 }; 806 enum drm_i915_oa_format { 807 I915_OA_FORMAT_A13 = 1, 808 I915_OA_FORMAT_A29, 809 I915_OA_FORMAT_A13_B8_C8, 810 I915_OA_FORMAT_B4_C8, 811 I915_OA_FORMAT_A45_B8_C8, 812 I915_OA_FORMAT_B4_C8_A16, 813 I915_OA_FORMAT_C4_B8, 814 I915_OA_FORMAT_A12, 815 I915_OA_FORMAT_A12_B8_C8, 816 I915_OA_FORMAT_A32u40_A4u32_B8_C8, 817 I915_OA_FORMAT_MAX 818 }; 819 enum drm_i915_perf_property_id { 820 DRM_I915_PERF_PROP_CTX_HANDLE = 1, 821 DRM_I915_PERF_PROP_SAMPLE_OA, 822 DRM_I915_PERF_PROP_OA_METRICS_SET, 823 DRM_I915_PERF_PROP_OA_FORMAT, 824 DRM_I915_PERF_PROP_OA_EXPONENT, 825 DRM_I915_PERF_PROP_HOLD_PREEMPTION, 826 DRM_I915_PERF_PROP_MAX 827 }; 828 struct drm_i915_perf_open_param { 829 __u32 flags; 830 #define I915_PERF_FLAG_FD_CLOEXEC (1 << 0) 831 #define I915_PERF_FLAG_FD_NONBLOCK (1 << 1) 832 #define I915_PERF_FLAG_DISABLED (1 << 2) 833 __u32 num_properties; 834 __u64 properties_ptr; 835 }; 836 #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) 837 #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) 838 #define I915_PERF_IOCTL_CONFIG _IO('i', 0x2) 839 struct drm_i915_perf_record_header { 840 __u32 type; 841 __u16 pad; 842 __u16 size; 843 }; 844 enum drm_i915_perf_record_type { 845 DRM_I915_PERF_RECORD_SAMPLE = 1, 846 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, 847 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, 848 DRM_I915_PERF_RECORD_MAX 849 }; 850 struct drm_i915_perf_oa_config { 851 char uuid[36]; 852 __u32 n_mux_regs; 853 __u32 n_boolean_regs; 854 __u32 n_flex_regs; 855 __u64 mux_regs_ptr; 856 __u64 boolean_regs_ptr; 857 __u64 flex_regs_ptr; 858 }; 859 struct drm_i915_query_item { 860 __u64 query_id; 861 #define DRM_I915_QUERY_TOPOLOGY_INFO 1 862 #define DRM_I915_QUERY_ENGINE_INFO 2 863 #define DRM_I915_QUERY_PERF_CONFIG 3 864 __s32 length; 865 __u32 flags; 866 #define DRM_I915_QUERY_PERF_CONFIG_LIST 1 867 #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2 868 #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3 869 __u64 data_ptr; 870 }; 871 struct drm_i915_query { 872 __u32 num_items; 873 __u32 flags; 874 __u64 items_ptr; 875 }; 876 struct drm_i915_query_topology_info { 877 __u16 flags; 878 __u16 max_slices; 879 __u16 max_subslices; 880 __u16 max_eus_per_subslice; 881 __u16 subslice_offset; 882 __u16 subslice_stride; 883 __u16 eu_offset; 884 __u16 eu_stride; 885 __u8 data[]; 886 }; 887 struct drm_i915_engine_info { 888 struct i915_engine_class_instance engine; 889 __u32 rsvd0; 890 __u64 flags; 891 __u64 capabilities; 892 #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0) 893 #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1) 894 __u64 rsvd1[4]; 895 }; 896 struct drm_i915_query_engine_info { 897 __u32 num_engines; 898 __u32 rsvd[3]; 899 struct drm_i915_engine_info engines[]; 900 }; 901 struct drm_i915_query_perf_config { 902 union { 903 __u64 n_configs; 904 __u64 config; 905 char uuid[36]; 906 }; 907 __u32 flags; 908 __u8 data[]; 909 }; 910 #ifdef __cplusplus 911 } 912 #endif 913 #endif 914