1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __AMDGPU_DRM_H__ 20 #define __AMDGPU_DRM_H__ 21 #include "drm.h" 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 #define DRM_AMDGPU_GEM_CREATE 0x00 26 #define DRM_AMDGPU_GEM_MMAP 0x01 27 #define DRM_AMDGPU_CTX 0x02 28 #define DRM_AMDGPU_BO_LIST 0x03 29 #define DRM_AMDGPU_CS 0x04 30 #define DRM_AMDGPU_INFO 0x05 31 #define DRM_AMDGPU_GEM_METADATA 0x06 32 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 33 #define DRM_AMDGPU_GEM_VA 0x08 34 #define DRM_AMDGPU_WAIT_CS 0x09 35 #define DRM_AMDGPU_GEM_OP 0x10 36 #define DRM_AMDGPU_GEM_USERPTR 0x11 37 #define DRM_AMDGPU_WAIT_FENCES 0x12 38 #define DRM_AMDGPU_VM 0x13 39 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 40 #define DRM_AMDGPU_SCHED 0x15 41 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 42 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 43 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 44 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 45 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 46 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 47 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 48 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 49 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 50 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 51 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 52 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 53 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 54 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 55 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 56 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 57 #define AMDGPU_GEM_DOMAIN_CPU 0x1 58 #define AMDGPU_GEM_DOMAIN_GTT 0x2 59 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 60 #define AMDGPU_GEM_DOMAIN_GDS 0x8 61 #define AMDGPU_GEM_DOMAIN_GWS 0x10 62 #define AMDGPU_GEM_DOMAIN_OA 0x20 63 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA) 64 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 65 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 66 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 67 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 68 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 69 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 70 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 71 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 72 #define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8) 73 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 74 struct drm_amdgpu_gem_create_in { 75 __u64 bo_size; 76 __u64 alignment; 77 __u64 domains; 78 __u64 domain_flags; 79 }; 80 struct drm_amdgpu_gem_create_out { 81 __u32 handle; 82 __u32 _pad; 83 }; 84 union drm_amdgpu_gem_create { 85 struct drm_amdgpu_gem_create_in in; 86 struct drm_amdgpu_gem_create_out out; 87 }; 88 #define AMDGPU_BO_LIST_OP_CREATE 0 89 #define AMDGPU_BO_LIST_OP_DESTROY 1 90 #define AMDGPU_BO_LIST_OP_UPDATE 2 91 struct drm_amdgpu_bo_list_in { 92 __u32 operation; 93 __u32 list_handle; 94 __u32 bo_number; 95 __u32 bo_info_size; 96 __u64 bo_info_ptr; 97 }; 98 struct drm_amdgpu_bo_list_entry { 99 __u32 bo_handle; 100 __u32 bo_priority; 101 }; 102 struct drm_amdgpu_bo_list_out { 103 __u32 list_handle; 104 __u32 _pad; 105 }; 106 union drm_amdgpu_bo_list { 107 struct drm_amdgpu_bo_list_in in; 108 struct drm_amdgpu_bo_list_out out; 109 }; 110 #define AMDGPU_CTX_OP_ALLOC_CTX 1 111 #define AMDGPU_CTX_OP_FREE_CTX 2 112 #define AMDGPU_CTX_OP_QUERY_STATE 3 113 #define AMDGPU_CTX_OP_QUERY_STATE2 4 114 #define AMDGPU_CTX_NO_RESET 0 115 #define AMDGPU_CTX_GUILTY_RESET 1 116 #define AMDGPU_CTX_INNOCENT_RESET 2 117 #define AMDGPU_CTX_UNKNOWN_RESET 3 118 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1 << 0) 119 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1 << 1) 120 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1 << 2) 121 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1 << 3) 122 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1 << 4) 123 #define AMDGPU_CTX_PRIORITY_UNSET - 2048 124 #define AMDGPU_CTX_PRIORITY_VERY_LOW - 1023 125 #define AMDGPU_CTX_PRIORITY_LOW - 512 126 #define AMDGPU_CTX_PRIORITY_NORMAL 0 127 #define AMDGPU_CTX_PRIORITY_HIGH 512 128 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 129 struct drm_amdgpu_ctx_in { 130 __u32 op; 131 __u32 flags; 132 __u32 ctx_id; 133 __s32 priority; 134 }; 135 union drm_amdgpu_ctx_out { 136 struct { 137 __u32 ctx_id; 138 __u32 _pad; 139 } alloc; 140 struct { 141 __u64 flags; 142 __u32 hangs; 143 __u32 reset_status; 144 } state; 145 }; 146 union drm_amdgpu_ctx { 147 struct drm_amdgpu_ctx_in in; 148 union drm_amdgpu_ctx_out out; 149 }; 150 #define AMDGPU_VM_OP_RESERVE_VMID 1 151 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 152 struct drm_amdgpu_vm_in { 153 __u32 op; 154 __u32 flags; 155 }; 156 struct drm_amdgpu_vm_out { 157 __u64 flags; 158 }; 159 union drm_amdgpu_vm { 160 struct drm_amdgpu_vm_in in; 161 struct drm_amdgpu_vm_out out; 162 }; 163 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 164 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 165 struct drm_amdgpu_sched_in { 166 __u32 op; 167 __u32 fd; 168 __s32 priority; 169 __u32 ctx_id; 170 }; 171 union drm_amdgpu_sched { 172 struct drm_amdgpu_sched_in in; 173 }; 174 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 175 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 176 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 177 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 178 struct drm_amdgpu_gem_userptr { 179 __u64 addr; 180 __u64 size; 181 __u32 flags; 182 __u32 handle; 183 }; 184 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 185 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 186 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 187 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 188 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 189 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 190 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 191 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 192 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 193 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 194 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 195 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 196 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 197 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 198 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 199 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 200 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 201 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 202 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 203 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 204 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 205 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 206 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 207 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 208 #define AMDGPU_TILING_SET(field,value) (((__u64) (value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT) 209 #define AMDGPU_TILING_GET(value,field) (((__u64) (value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK) 210 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 211 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 212 struct drm_amdgpu_gem_metadata { 213 __u32 handle; 214 __u32 op; 215 struct { 216 __u64 flags; 217 __u64 tiling_info; 218 __u32 data_size_bytes; 219 __u32 data[64]; 220 } data; 221 }; 222 struct drm_amdgpu_gem_mmap_in { 223 __u32 handle; 224 __u32 _pad; 225 }; 226 struct drm_amdgpu_gem_mmap_out { 227 __u64 addr_ptr; 228 }; 229 union drm_amdgpu_gem_mmap { 230 struct drm_amdgpu_gem_mmap_in in; 231 struct drm_amdgpu_gem_mmap_out out; 232 }; 233 struct drm_amdgpu_gem_wait_idle_in { 234 __u32 handle; 235 __u32 flags; 236 __u64 timeout; 237 }; 238 struct drm_amdgpu_gem_wait_idle_out { 239 __u32 status; 240 __u32 domain; 241 }; 242 union drm_amdgpu_gem_wait_idle { 243 struct drm_amdgpu_gem_wait_idle_in in; 244 struct drm_amdgpu_gem_wait_idle_out out; 245 }; 246 struct drm_amdgpu_wait_cs_in { 247 __u64 handle; 248 __u64 timeout; 249 __u32 ip_type; 250 __u32 ip_instance; 251 __u32 ring; 252 __u32 ctx_id; 253 }; 254 struct drm_amdgpu_wait_cs_out { 255 __u64 status; 256 }; 257 union drm_amdgpu_wait_cs { 258 struct drm_amdgpu_wait_cs_in in; 259 struct drm_amdgpu_wait_cs_out out; 260 }; 261 struct drm_amdgpu_fence { 262 __u32 ctx_id; 263 __u32 ip_type; 264 __u32 ip_instance; 265 __u32 ring; 266 __u64 seq_no; 267 }; 268 struct drm_amdgpu_wait_fences_in { 269 __u64 fences; 270 __u32 fence_count; 271 __u32 wait_all; 272 __u64 timeout_ns; 273 }; 274 struct drm_amdgpu_wait_fences_out { 275 __u32 status; 276 __u32 first_signaled; 277 }; 278 union drm_amdgpu_wait_fences { 279 struct drm_amdgpu_wait_fences_in in; 280 struct drm_amdgpu_wait_fences_out out; 281 }; 282 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 283 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 284 struct drm_amdgpu_gem_op { 285 __u32 handle; 286 __u32 op; 287 __u64 value; 288 }; 289 #define AMDGPU_VA_OP_MAP 1 290 #define AMDGPU_VA_OP_UNMAP 2 291 #define AMDGPU_VA_OP_CLEAR 3 292 #define AMDGPU_VA_OP_REPLACE 4 293 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 294 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 295 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 296 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 297 #define AMDGPU_VM_PAGE_PRT (1 << 4) 298 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 299 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 300 #define AMDGPU_VM_MTYPE_NC (1 << 5) 301 #define AMDGPU_VM_MTYPE_WC (2 << 5) 302 #define AMDGPU_VM_MTYPE_CC (3 << 5) 303 #define AMDGPU_VM_MTYPE_UC (4 << 5) 304 #define AMDGPU_VM_MTYPE_RW (5 << 5) 305 struct drm_amdgpu_gem_va { 306 __u32 handle; 307 __u32 _pad; 308 __u32 operation; 309 __u32 flags; 310 __u64 va_address; 311 __u64 offset_in_bo; 312 __u64 map_size; 313 }; 314 #define AMDGPU_HW_IP_GFX 0 315 #define AMDGPU_HW_IP_COMPUTE 1 316 #define AMDGPU_HW_IP_DMA 2 317 #define AMDGPU_HW_IP_UVD 3 318 #define AMDGPU_HW_IP_VCE 4 319 #define AMDGPU_HW_IP_UVD_ENC 5 320 #define AMDGPU_HW_IP_VCN_DEC 6 321 #define AMDGPU_HW_IP_VCN_ENC 7 322 #define AMDGPU_HW_IP_VCN_JPEG 8 323 #define AMDGPU_HW_IP_NUM 9 324 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 325 #define AMDGPU_CHUNK_ID_IB 0x01 326 #define AMDGPU_CHUNK_ID_FENCE 0x02 327 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 328 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 329 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 330 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 331 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 332 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 333 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 334 struct drm_amdgpu_cs_chunk { 335 __u32 chunk_id; 336 __u32 length_dw; 337 __u64 chunk_data; 338 }; 339 struct drm_amdgpu_cs_in { 340 __u32 ctx_id; 341 __u32 bo_list_handle; 342 __u32 num_chunks; 343 __u32 _pad; 344 __u64 chunks; 345 }; 346 struct drm_amdgpu_cs_out { 347 __u64 handle; 348 }; 349 union drm_amdgpu_cs { 350 struct drm_amdgpu_cs_in in; 351 struct drm_amdgpu_cs_out out; 352 }; 353 #define AMDGPU_IB_FLAG_CE (1 << 0) 354 #define AMDGPU_IB_FLAG_PREAMBLE (1 << 1) 355 #define AMDGPU_IB_FLAG_PREEMPT (1 << 2) 356 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 357 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 358 struct drm_amdgpu_cs_chunk_ib { 359 __u32 _pad; 360 __u32 flags; 361 __u64 va_start; 362 __u32 ib_bytes; 363 __u32 ip_type; 364 __u32 ip_instance; 365 __u32 ring; 366 }; 367 struct drm_amdgpu_cs_chunk_dep { 368 __u32 ip_type; 369 __u32 ip_instance; 370 __u32 ring; 371 __u32 ctx_id; 372 __u64 handle; 373 }; 374 struct drm_amdgpu_cs_chunk_fence { 375 __u32 handle; 376 __u32 offset; 377 }; 378 struct drm_amdgpu_cs_chunk_sem { 379 __u32 handle; 380 }; 381 struct drm_amdgpu_cs_chunk_syncobj { 382 __u32 handle; 383 __u32 flags; 384 __u64 point; 385 }; 386 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 387 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 388 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 389 union drm_amdgpu_fence_to_handle { 390 struct { 391 struct drm_amdgpu_fence fence; 392 __u32 what; 393 __u32 pad; 394 } in; 395 struct { 396 __u32 handle; 397 } out; 398 }; 399 struct drm_amdgpu_cs_chunk_data { 400 union { 401 struct drm_amdgpu_cs_chunk_ib ib_data; 402 struct drm_amdgpu_cs_chunk_fence fence_data; 403 }; 404 }; 405 #define AMDGPU_IDS_FLAGS_FUSION 0x1 406 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 407 #define AMDGPU_INFO_ACCEL_WORKING 0x00 408 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 409 #define AMDGPU_INFO_HW_IP_INFO 0x02 410 #define AMDGPU_INFO_HW_IP_COUNT 0x03 411 #define AMDGPU_INFO_TIMESTAMP 0x05 412 #define AMDGPU_INFO_FW_VERSION 0x0e 413 #define AMDGPU_INFO_FW_VCE 0x1 414 #define AMDGPU_INFO_FW_UVD 0x2 415 #define AMDGPU_INFO_FW_GMC 0x03 416 #define AMDGPU_INFO_FW_GFX_ME 0x04 417 #define AMDGPU_INFO_FW_GFX_PFP 0x05 418 #define AMDGPU_INFO_FW_GFX_CE 0x06 419 #define AMDGPU_INFO_FW_GFX_RLC 0x07 420 #define AMDGPU_INFO_FW_GFX_MEC 0x08 421 #define AMDGPU_INFO_FW_SMC 0x0a 422 #define AMDGPU_INFO_FW_SDMA 0x0b 423 #define AMDGPU_INFO_FW_SOS 0x0c 424 #define AMDGPU_INFO_FW_ASD 0x0d 425 #define AMDGPU_INFO_FW_VCN 0x0e 426 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 427 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 428 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 429 #define AMDGPU_INFO_FW_DMCU 0x12 430 #define AMDGPU_INFO_FW_TA 0x13 431 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 432 #define AMDGPU_INFO_VRAM_USAGE 0x10 433 #define AMDGPU_INFO_GTT_USAGE 0x11 434 #define AMDGPU_INFO_GDS_CONFIG 0x13 435 #define AMDGPU_INFO_VRAM_GTT 0x14 436 #define AMDGPU_INFO_READ_MMR_REG 0x15 437 #define AMDGPU_INFO_DEV_INFO 0x16 438 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 439 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 440 #define AMDGPU_INFO_MEMORY 0x19 441 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 442 #define AMDGPU_INFO_VBIOS 0x1B 443 #define AMDGPU_INFO_VBIOS_SIZE 0x1 444 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 445 #define AMDGPU_INFO_NUM_HANDLES 0x1C 446 #define AMDGPU_INFO_SENSOR 0x1D 447 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 448 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 449 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 450 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 451 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 452 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 453 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 454 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 455 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 456 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 457 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 458 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 459 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 460 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 461 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 462 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 463 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 464 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 465 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 466 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 467 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 468 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 469 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 470 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 471 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 472 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 473 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 474 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 475 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 476 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 477 struct drm_amdgpu_query_fw { 478 __u32 fw_type; 479 __u32 ip_instance; 480 __u32 index; 481 __u32 _pad; 482 }; 483 struct drm_amdgpu_info { 484 __u64 return_pointer; 485 __u32 return_size; 486 __u32 query; 487 union { 488 struct { 489 __u32 id; 490 __u32 _pad; 491 } mode_crtc; 492 struct { 493 __u32 type; 494 __u32 ip_instance; 495 } query_hw_ip; 496 struct { 497 __u32 dword_offset; 498 __u32 count; 499 __u32 instance; 500 __u32 flags; 501 } read_mmr_reg; 502 struct drm_amdgpu_query_fw query_fw; 503 struct { 504 __u32 type; 505 __u32 offset; 506 } vbios_info; 507 struct { 508 __u32 type; 509 } sensor_info; 510 }; 511 }; 512 struct drm_amdgpu_info_gds { 513 __u32 gds_gfx_partition_size; 514 __u32 compute_partition_size; 515 __u32 gds_total_size; 516 __u32 gws_per_gfx_partition; 517 __u32 gws_per_compute_partition; 518 __u32 oa_per_gfx_partition; 519 __u32 oa_per_compute_partition; 520 __u32 _pad; 521 }; 522 struct drm_amdgpu_info_vram_gtt { 523 __u64 vram_size; 524 __u64 vram_cpu_accessible_size; 525 __u64 gtt_size; 526 }; 527 struct drm_amdgpu_heap_info { 528 __u64 total_heap_size; 529 __u64 usable_heap_size; 530 __u64 heap_usage; 531 __u64 max_allocation; 532 }; 533 struct drm_amdgpu_memory_info { 534 struct drm_amdgpu_heap_info vram; 535 struct drm_amdgpu_heap_info cpu_accessible_vram; 536 struct drm_amdgpu_heap_info gtt; 537 }; 538 struct drm_amdgpu_info_firmware { 539 __u32 ver; 540 __u32 feature; 541 }; 542 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 543 #define AMDGPU_VRAM_TYPE_GDDR1 1 544 #define AMDGPU_VRAM_TYPE_DDR2 2 545 #define AMDGPU_VRAM_TYPE_GDDR3 3 546 #define AMDGPU_VRAM_TYPE_GDDR4 4 547 #define AMDGPU_VRAM_TYPE_GDDR5 5 548 #define AMDGPU_VRAM_TYPE_HBM 6 549 #define AMDGPU_VRAM_TYPE_DDR3 7 550 #define AMDGPU_VRAM_TYPE_DDR4 8 551 #define AMDGPU_VRAM_TYPE_GDDR6 9 552 struct drm_amdgpu_info_device { 553 __u32 device_id; 554 __u32 chip_rev; 555 __u32 external_rev; 556 __u32 pci_rev; 557 __u32 family; 558 __u32 num_shader_engines; 559 __u32 num_shader_arrays_per_engine; 560 __u32 gpu_counter_freq; 561 __u64 max_engine_clock; 562 __u64 max_memory_clock; 563 __u32 cu_active_number; 564 __u32 cu_ao_mask; 565 __u32 cu_bitmap[4][4]; 566 __u32 enabled_rb_pipes_mask; 567 __u32 num_rb_pipes; 568 __u32 num_hw_gfx_contexts; 569 __u32 _pad; 570 __u64 ids_flags; 571 __u64 virtual_address_offset; 572 __u64 virtual_address_max; 573 __u32 virtual_address_alignment; 574 __u32 pte_fragment_size; 575 __u32 gart_page_size; 576 __u32 ce_ram_size; 577 __u32 vram_type; 578 __u32 vram_bit_width; 579 __u32 vce_harvest_config; 580 __u32 gc_double_offchip_lds_buf; 581 __u64 prim_buf_gpu_addr; 582 __u64 pos_buf_gpu_addr; 583 __u64 cntl_sb_buf_gpu_addr; 584 __u64 param_buf_gpu_addr; 585 __u32 prim_buf_size; 586 __u32 pos_buf_size; 587 __u32 cntl_sb_buf_size; 588 __u32 param_buf_size; 589 __u32 wave_front_size; 590 __u32 num_shader_visible_vgprs; 591 __u32 num_cu_per_sh; 592 __u32 num_tcc_blocks; 593 __u32 gs_vgt_table_depth; 594 __u32 gs_prim_buffer_depth; 595 __u32 max_gs_waves_per_vgt; 596 __u32 _pad1; 597 __u32 cu_ao_bitmap[4][4]; 598 __u64 high_va_offset; 599 __u64 high_va_max; 600 __u32 pa_sc_tile_steering_override; 601 __u64 tcc_disabled_mask; 602 }; 603 struct drm_amdgpu_info_hw_ip { 604 __u32 hw_ip_version_major; 605 __u32 hw_ip_version_minor; 606 __u64 capabilities_flags; 607 __u32 ib_start_alignment; 608 __u32 ib_size_alignment; 609 __u32 available_rings; 610 __u32 _pad; 611 }; 612 struct drm_amdgpu_info_num_handles { 613 __u32 uvd_max_handles; 614 __u32 uvd_used_handles; 615 }; 616 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 617 struct drm_amdgpu_info_vce_clock_table_entry { 618 __u32 sclk; 619 __u32 mclk; 620 __u32 eclk; 621 __u32 pad; 622 }; 623 struct drm_amdgpu_info_vce_clock_table { 624 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 625 __u32 num_valid_entries; 626 __u32 pad; 627 }; 628 #define AMDGPU_FAMILY_UNKNOWN 0 629 #define AMDGPU_FAMILY_SI 110 630 #define AMDGPU_FAMILY_CI 120 631 #define AMDGPU_FAMILY_KV 125 632 #define AMDGPU_FAMILY_VI 130 633 #define AMDGPU_FAMILY_CZ 135 634 #define AMDGPU_FAMILY_AI 141 635 #define AMDGPU_FAMILY_RV 142 636 #define AMDGPU_FAMILY_NV 143 637 #ifdef __cplusplus 638 } 639 #endif 640 #endif 641