1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPIVFIO_H 20 #define _UAPIVFIO_H 21 #include <linux/types.h> 22 #include <linux/ioctl.h> 23 #define VFIO_API_VERSION 0 24 #define VFIO_TYPE1_IOMMU 1 25 #define VFIO_SPAPR_TCE_IOMMU 2 26 #define VFIO_TYPE1v2_IOMMU 3 27 #define VFIO_DMA_CC_IOMMU 4 28 #define VFIO_EEH 5 29 #define VFIO_TYPE1_NESTING_IOMMU 6 30 #define VFIO_SPAPR_TCE_v2_IOMMU 7 31 #define VFIO_NOIOMMU_IOMMU 8 32 #define VFIO_TYPE (';') 33 #define VFIO_BASE 100 34 struct vfio_info_cap_header { 35 __u16 id; 36 __u16 version; 37 __u32 next; 38 }; 39 #define VFIO_GET_API_VERSION _IO(VFIO_TYPE, VFIO_BASE + 0) 40 #define VFIO_CHECK_EXTENSION _IO(VFIO_TYPE, VFIO_BASE + 1) 41 #define VFIO_SET_IOMMU _IO(VFIO_TYPE, VFIO_BASE + 2) 42 struct vfio_group_status { 43 __u32 argsz; 44 __u32 flags; 45 #define VFIO_GROUP_FLAGS_VIABLE (1 << 0) 46 #define VFIO_GROUP_FLAGS_CONTAINER_SET (1 << 1) 47 }; 48 #define VFIO_GROUP_GET_STATUS _IO(VFIO_TYPE, VFIO_BASE + 3) 49 #define VFIO_GROUP_SET_CONTAINER _IO(VFIO_TYPE, VFIO_BASE + 4) 50 #define VFIO_GROUP_UNSET_CONTAINER _IO(VFIO_TYPE, VFIO_BASE + 5) 51 #define VFIO_GROUP_GET_DEVICE_FD _IO(VFIO_TYPE, VFIO_BASE + 6) 52 struct vfio_device_info { 53 __u32 argsz; 54 __u32 flags; 55 #define VFIO_DEVICE_FLAGS_RESET (1 << 0) 56 #define VFIO_DEVICE_FLAGS_PCI (1 << 1) 57 #define VFIO_DEVICE_FLAGS_PLATFORM (1 << 2) 58 #define VFIO_DEVICE_FLAGS_AMBA (1 << 3) 59 #define VFIO_DEVICE_FLAGS_CCW (1 << 4) 60 #define VFIO_DEVICE_FLAGS_AP (1 << 5) 61 __u32 num_regions; 62 __u32 num_irqs; 63 }; 64 #define VFIO_DEVICE_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 7) 65 #define VFIO_DEVICE_API_PCI_STRING "vfio-pci" 66 #define VFIO_DEVICE_API_PLATFORM_STRING "vfio-platform" 67 #define VFIO_DEVICE_API_AMBA_STRING "vfio-amba" 68 #define VFIO_DEVICE_API_CCW_STRING "vfio-ccw" 69 #define VFIO_DEVICE_API_AP_STRING "vfio-ap" 70 struct vfio_region_info { 71 __u32 argsz; 72 __u32 flags; 73 #define VFIO_REGION_INFO_FLAG_READ (1 << 0) 74 #define VFIO_REGION_INFO_FLAG_WRITE (1 << 1) 75 #define VFIO_REGION_INFO_FLAG_MMAP (1 << 2) 76 #define VFIO_REGION_INFO_FLAG_CAPS (1 << 3) 77 __u32 index; 78 __u32 cap_offset; 79 __u64 size; 80 __u64 offset; 81 }; 82 #define VFIO_DEVICE_GET_REGION_INFO _IO(VFIO_TYPE, VFIO_BASE + 8) 83 #define VFIO_REGION_INFO_CAP_SPARSE_MMAP 1 84 struct vfio_region_sparse_mmap_area { 85 __u64 offset; 86 __u64 size; 87 }; 88 struct vfio_region_info_cap_sparse_mmap { 89 struct vfio_info_cap_header header; 90 __u32 nr_areas; 91 __u32 reserved; 92 struct vfio_region_sparse_mmap_area areas[]; 93 }; 94 #define VFIO_REGION_INFO_CAP_TYPE 2 95 struct vfio_region_info_cap_type { 96 struct vfio_info_cap_header header; 97 __u32 type; 98 __u32 subtype; 99 }; 100 #define VFIO_REGION_TYPE_PCI_VENDOR_TYPE (1 << 31) 101 #define VFIO_REGION_TYPE_PCI_VENDOR_MASK (0xffff) 102 #define VFIO_REGION_TYPE_GFX (1) 103 #define VFIO_REGION_TYPE_CCW (2) 104 #define VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION (1) 105 #define VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG (2) 106 #define VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG (3) 107 #define VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM (1) 108 #define VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD (1) 109 #define VFIO_REGION_SUBTYPE_GFX_EDID (1) 110 struct vfio_region_gfx_edid { 111 __u32 edid_offset; 112 __u32 edid_max_size; 113 __u32 edid_size; 114 __u32 max_xres; 115 __u32 max_yres; 116 __u32 link_state; 117 #define VFIO_DEVICE_GFX_LINK_STATE_UP 1 118 #define VFIO_DEVICE_GFX_LINK_STATE_DOWN 2 119 }; 120 #define VFIO_REGION_SUBTYPE_CCW_ASYNC_CMD (1) 121 #define VFIO_REGION_INFO_CAP_MSIX_MAPPABLE 3 122 #define VFIO_REGION_INFO_CAP_NVLINK2_SSATGT 4 123 struct vfio_region_info_cap_nvlink2_ssatgt { 124 struct vfio_info_cap_header header; 125 __u64 tgt; 126 }; 127 #define VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD 5 128 struct vfio_region_info_cap_nvlink2_lnkspd { 129 struct vfio_info_cap_header header; 130 __u32 link_speed; 131 __u32 __pad; 132 }; 133 struct vfio_irq_info { 134 __u32 argsz; 135 __u32 flags; 136 #define VFIO_IRQ_INFO_EVENTFD (1 << 0) 137 #define VFIO_IRQ_INFO_MASKABLE (1 << 1) 138 #define VFIO_IRQ_INFO_AUTOMASKED (1 << 2) 139 #define VFIO_IRQ_INFO_NORESIZE (1 << 3) 140 __u32 index; 141 __u32 count; 142 }; 143 #define VFIO_DEVICE_GET_IRQ_INFO _IO(VFIO_TYPE, VFIO_BASE + 9) 144 struct vfio_irq_set { 145 __u32 argsz; 146 __u32 flags; 147 #define VFIO_IRQ_SET_DATA_NONE (1 << 0) 148 #define VFIO_IRQ_SET_DATA_BOOL (1 << 1) 149 #define VFIO_IRQ_SET_DATA_EVENTFD (1 << 2) 150 #define VFIO_IRQ_SET_ACTION_MASK (1 << 3) 151 #define VFIO_IRQ_SET_ACTION_UNMASK (1 << 4) 152 #define VFIO_IRQ_SET_ACTION_TRIGGER (1 << 5) 153 __u32 index; 154 __u32 start; 155 __u32 count; 156 __u8 data[]; 157 }; 158 #define VFIO_DEVICE_SET_IRQS _IO(VFIO_TYPE, VFIO_BASE + 10) 159 #define VFIO_IRQ_SET_DATA_TYPE_MASK (VFIO_IRQ_SET_DATA_NONE | VFIO_IRQ_SET_DATA_BOOL | VFIO_IRQ_SET_DATA_EVENTFD) 160 #define VFIO_IRQ_SET_ACTION_TYPE_MASK (VFIO_IRQ_SET_ACTION_MASK | VFIO_IRQ_SET_ACTION_UNMASK | VFIO_IRQ_SET_ACTION_TRIGGER) 161 #define VFIO_DEVICE_RESET _IO(VFIO_TYPE, VFIO_BASE + 11) 162 enum { 163 VFIO_PCI_BAR0_REGION_INDEX, 164 VFIO_PCI_BAR1_REGION_INDEX, 165 VFIO_PCI_BAR2_REGION_INDEX, 166 VFIO_PCI_BAR3_REGION_INDEX, 167 VFIO_PCI_BAR4_REGION_INDEX, 168 VFIO_PCI_BAR5_REGION_INDEX, 169 VFIO_PCI_ROM_REGION_INDEX, 170 VFIO_PCI_CONFIG_REGION_INDEX, 171 VFIO_PCI_VGA_REGION_INDEX, 172 VFIO_PCI_NUM_REGIONS = 9 173 }; 174 enum { 175 VFIO_PCI_INTX_IRQ_INDEX, 176 VFIO_PCI_MSI_IRQ_INDEX, 177 VFIO_PCI_MSIX_IRQ_INDEX, 178 VFIO_PCI_ERR_IRQ_INDEX, 179 VFIO_PCI_REQ_IRQ_INDEX, 180 VFIO_PCI_NUM_IRQS 181 }; 182 enum { 183 VFIO_CCW_CONFIG_REGION_INDEX, 184 VFIO_CCW_NUM_REGIONS 185 }; 186 enum { 187 VFIO_CCW_IO_IRQ_INDEX, 188 VFIO_CCW_NUM_IRQS 189 }; 190 struct vfio_pci_dependent_device { 191 __u32 group_id; 192 __u16 segment; 193 __u8 bus; 194 __u8 devfn; 195 }; 196 struct vfio_pci_hot_reset_info { 197 __u32 argsz; 198 __u32 flags; 199 __u32 count; 200 struct vfio_pci_dependent_device devices[]; 201 }; 202 #define VFIO_DEVICE_GET_PCI_HOT_RESET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12) 203 struct vfio_pci_hot_reset { 204 __u32 argsz; 205 __u32 flags; 206 __u32 count; 207 __s32 group_fds[]; 208 }; 209 #define VFIO_DEVICE_PCI_HOT_RESET _IO(VFIO_TYPE, VFIO_BASE + 13) 210 struct vfio_device_gfx_plane_info { 211 __u32 argsz; 212 __u32 flags; 213 #define VFIO_GFX_PLANE_TYPE_PROBE (1 << 0) 214 #define VFIO_GFX_PLANE_TYPE_DMABUF (1 << 1) 215 #define VFIO_GFX_PLANE_TYPE_REGION (1 << 2) 216 __u32 drm_plane_type; 217 __u32 drm_format; 218 __u64 drm_format_mod; 219 __u32 width; 220 __u32 height; 221 __u32 stride; 222 __u32 size; 223 __u32 x_pos; 224 __u32 y_pos; 225 __u32 x_hot; 226 __u32 y_hot; 227 union { 228 __u32 region_index; 229 __u32 dmabuf_id; 230 }; 231 }; 232 #define VFIO_DEVICE_QUERY_GFX_PLANE _IO(VFIO_TYPE, VFIO_BASE + 14) 233 #define VFIO_DEVICE_GET_GFX_DMABUF _IO(VFIO_TYPE, VFIO_BASE + 15) 234 struct vfio_device_ioeventfd { 235 __u32 argsz; 236 __u32 flags; 237 #define VFIO_DEVICE_IOEVENTFD_8 (1 << 0) 238 #define VFIO_DEVICE_IOEVENTFD_16 (1 << 1) 239 #define VFIO_DEVICE_IOEVENTFD_32 (1 << 2) 240 #define VFIO_DEVICE_IOEVENTFD_64 (1 << 3) 241 #define VFIO_DEVICE_IOEVENTFD_SIZE_MASK (0xf) 242 __u64 offset; 243 __u64 data; 244 __s32 fd; 245 }; 246 #define VFIO_DEVICE_IOEVENTFD _IO(VFIO_TYPE, VFIO_BASE + 16) 247 struct vfio_iommu_type1_info { 248 __u32 argsz; 249 __u32 flags; 250 #define VFIO_IOMMU_INFO_PGSIZES (1 << 0) 251 #define VFIO_IOMMU_INFO_CAPS (1 << 1) 252 __u64 iova_pgsizes; 253 __u32 cap_offset; 254 }; 255 #define VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE 1 256 struct vfio_iova_range { 257 __u64 start; 258 __u64 end; 259 }; 260 struct vfio_iommu_type1_info_cap_iova_range { 261 struct vfio_info_cap_header header; 262 __u32 nr_iovas; 263 __u32 reserved; 264 struct vfio_iova_range iova_ranges[]; 265 }; 266 #define VFIO_IOMMU_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12) 267 struct vfio_iommu_type1_dma_map { 268 __u32 argsz; 269 __u32 flags; 270 #define VFIO_DMA_MAP_FLAG_READ (1 << 0) 271 #define VFIO_DMA_MAP_FLAG_WRITE (1 << 1) 272 __u64 vaddr; 273 __u64 iova; 274 __u64 size; 275 }; 276 #define VFIO_IOMMU_MAP_DMA _IO(VFIO_TYPE, VFIO_BASE + 13) 277 struct vfio_iommu_type1_dma_unmap { 278 __u32 argsz; 279 __u32 flags; 280 __u64 iova; 281 __u64 size; 282 }; 283 #define VFIO_IOMMU_UNMAP_DMA _IO(VFIO_TYPE, VFIO_BASE + 14) 284 #define VFIO_IOMMU_ENABLE _IO(VFIO_TYPE, VFIO_BASE + 15) 285 #define VFIO_IOMMU_DISABLE _IO(VFIO_TYPE, VFIO_BASE + 16) 286 struct vfio_iommu_spapr_tce_ddw_info { 287 __u64 pgsizes; 288 __u32 max_dynamic_windows_supported; 289 __u32 levels; 290 }; 291 struct vfio_iommu_spapr_tce_info { 292 __u32 argsz; 293 __u32 flags; 294 #define VFIO_IOMMU_SPAPR_INFO_DDW (1 << 0) 295 __u32 dma32_window_start; 296 __u32 dma32_window_size; 297 struct vfio_iommu_spapr_tce_ddw_info ddw; 298 }; 299 #define VFIO_IOMMU_SPAPR_TCE_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12) 300 struct vfio_eeh_pe_err { 301 __u32 type; 302 __u32 func; 303 __u64 addr; 304 __u64 mask; 305 }; 306 struct vfio_eeh_pe_op { 307 __u32 argsz; 308 __u32 flags; 309 __u32 op; 310 union { 311 struct vfio_eeh_pe_err err; 312 }; 313 }; 314 #define VFIO_EEH_PE_DISABLE 0 315 #define VFIO_EEH_PE_ENABLE 1 316 #define VFIO_EEH_PE_UNFREEZE_IO 2 317 #define VFIO_EEH_PE_UNFREEZE_DMA 3 318 #define VFIO_EEH_PE_GET_STATE 4 319 #define VFIO_EEH_PE_STATE_NORMAL 0 320 #define VFIO_EEH_PE_STATE_RESET 1 321 #define VFIO_EEH_PE_STATE_STOPPED 2 322 #define VFIO_EEH_PE_STATE_STOPPED_DMA 4 323 #define VFIO_EEH_PE_STATE_UNAVAIL 5 324 #define VFIO_EEH_PE_RESET_DEACTIVATE 5 325 #define VFIO_EEH_PE_RESET_HOT 6 326 #define VFIO_EEH_PE_RESET_FUNDAMENTAL 7 327 #define VFIO_EEH_PE_CONFIGURE 8 328 #define VFIO_EEH_PE_INJECT_ERR 9 329 #define VFIO_EEH_PE_OP _IO(VFIO_TYPE, VFIO_BASE + 21) 330 struct vfio_iommu_spapr_register_memory { 331 __u32 argsz; 332 __u32 flags; 333 __u64 vaddr; 334 __u64 size; 335 }; 336 #define VFIO_IOMMU_SPAPR_REGISTER_MEMORY _IO(VFIO_TYPE, VFIO_BASE + 17) 337 #define VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY _IO(VFIO_TYPE, VFIO_BASE + 18) 338 struct vfio_iommu_spapr_tce_create { 339 __u32 argsz; 340 __u32 flags; 341 __u32 page_shift; 342 __u32 __resv1; 343 __u64 window_size; 344 __u32 levels; 345 __u32 __resv2; 346 __u64 start_addr; 347 }; 348 #define VFIO_IOMMU_SPAPR_TCE_CREATE _IO(VFIO_TYPE, VFIO_BASE + 19) 349 struct vfio_iommu_spapr_tce_remove { 350 __u32 argsz; 351 __u32 flags; 352 __u64 start_addr; 353 }; 354 #define VFIO_IOMMU_SPAPR_TCE_REMOVE _IO(VFIO_TYPE, VFIO_BASE + 20) 355 #endif 356