1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __UAPI_CAM_DEFS_H__ 20 #define __UAPI_CAM_DEFS_H__ 21 #include <linux/videodev2.h> 22 #include <linux/types.h> 23 #include <linux/ioctl.h> 24 #define CAM_COMMON_OPCODE_BASE 0x100 25 #define CAM_QUERY_CAP (CAM_COMMON_OPCODE_BASE + 0x1) 26 #define CAM_ACQUIRE_DEV (CAM_COMMON_OPCODE_BASE + 0x2) 27 #define CAM_START_DEV (CAM_COMMON_OPCODE_BASE + 0x3) 28 #define CAM_STOP_DEV (CAM_COMMON_OPCODE_BASE + 0x4) 29 #define CAM_CONFIG_DEV (CAM_COMMON_OPCODE_BASE + 0x5) 30 #define CAM_RELEASE_DEV (CAM_COMMON_OPCODE_BASE + 0x6) 31 #define CAM_SD_SHUTDOWN (CAM_COMMON_OPCODE_BASE + 0x7) 32 #define CAM_FLUSH_REQ (CAM_COMMON_OPCODE_BASE + 0x8) 33 #define CAM_COMMON_OPCODE_MAX (CAM_COMMON_OPCODE_BASE + 0x9) 34 #define CAM_COMMON_OPCODE_BASE_v2 0x150 35 #define CAM_ACQUIRE_HW (CAM_COMMON_OPCODE_BASE_v2 + 0x1) 36 #define CAM_RELEASE_HW (CAM_COMMON_OPCODE_BASE_v2 + 0x2) 37 #define CAM_DUMP_REQ (CAM_COMMON_OPCODE_BASE_v2 + 0x3) 38 #define CAM_EXT_OPCODE_BASE 0x200 39 #define CAM_CONFIG_DEV_EXTERNAL (CAM_EXT_OPCODE_BASE + 0x1) 40 #define CAM_HANDLE_USER_POINTER 1 41 #define CAM_HANDLE_MEM_HANDLE 2 42 #define CAM_GENERIC_BLOB_CMDBUFFER_SIZE_MASK 0xFFFFFF00 43 #define CAM_GENERIC_BLOB_CMDBUFFER_SIZE_SHIFT 8 44 #define CAM_GENERIC_BLOB_CMDBUFFER_TYPE_MASK 0xFF 45 #define CAM_GENERIC_BLOB_CMDBUFFER_TYPE_SHIFT 0 46 #define CAM_CMD_BUF_DMI 0x1 47 #define CAM_CMD_BUF_DMI16 0x2 48 #define CAM_CMD_BUF_DMI32 0x3 49 #define CAM_CMD_BUF_DMI64 0x4 50 #define CAM_CMD_BUF_DIRECT 0x5 51 #define CAM_CMD_BUF_INDIRECT 0x6 52 #define CAM_CMD_BUF_I2C 0x7 53 #define CAM_CMD_BUF_FW 0x8 54 #define CAM_CMD_BUF_GENERIC 0x9 55 #define CAM_CMD_BUF_LEGACY 0xA 56 #define CAM_UBWC_CFG_VERSION_1 1 57 #define CAM_UBWC_CFG_VERSION_2 2 58 #define CAM_MAX_ACQ_RES 5 59 #define CAM_MAX_HW_SPLIT 3 60 enum flush_type_t { 61 CAM_FLUSH_TYPE_REQ, 62 CAM_FLUSH_TYPE_ALL, 63 CAM_FLUSH_TYPE_MAX 64 }; 65 struct cam_control { 66 uint32_t op_code; 67 uint32_t size; 68 uint32_t handle_type; 69 uint32_t reserved; 70 uint64_t handle; 71 }; 72 #define VIDIOC_CAM_CONTROL _IOWR('V', BASE_VIDIOC_PRIVATE, struct cam_control) 73 struct cam_hw_version { 74 uint32_t major; 75 uint32_t minor; 76 uint32_t incr; 77 uint32_t reserved; 78 }; 79 struct cam_iommu_handle { 80 int32_t non_secure; 81 int32_t secure; 82 }; 83 #define CAM_SECURE_MODE_NON_SECURE 0 84 #define CAM_SECURE_MODE_SECURE 1 85 #define CAM_FORMAT_BASE 0 86 #define CAM_FORMAT_MIPI_RAW_6 1 87 #define CAM_FORMAT_MIPI_RAW_8 2 88 #define CAM_FORMAT_MIPI_RAW_10 3 89 #define CAM_FORMAT_MIPI_RAW_12 4 90 #define CAM_FORMAT_MIPI_RAW_14 5 91 #define CAM_FORMAT_MIPI_RAW_16 6 92 #define CAM_FORMAT_MIPI_RAW_20 7 93 #define CAM_FORMAT_QTI_RAW_8 8 94 #define CAM_FORMAT_QTI_RAW_10 9 95 #define CAM_FORMAT_QTI_RAW_12 10 96 #define CAM_FORMAT_QTI_RAW_14 11 97 #define CAM_FORMAT_PLAIN8 12 98 #define CAM_FORMAT_PLAIN16_8 13 99 #define CAM_FORMAT_PLAIN16_10 14 100 #define CAM_FORMAT_PLAIN16_12 15 101 #define CAM_FORMAT_PLAIN16_14 16 102 #define CAM_FORMAT_PLAIN16_16 17 103 #define CAM_FORMAT_PLAIN32_20 18 104 #define CAM_FORMAT_PLAIN64 19 105 #define CAM_FORMAT_PLAIN128 20 106 #define CAM_FORMAT_ARGB 21 107 #define CAM_FORMAT_ARGB_10 22 108 #define CAM_FORMAT_ARGB_12 23 109 #define CAM_FORMAT_ARGB_14 24 110 #define CAM_FORMAT_DPCM_10_6_10 25 111 #define CAM_FORMAT_DPCM_10_8_10 26 112 #define CAM_FORMAT_DPCM_12_6_12 27 113 #define CAM_FORMAT_DPCM_12_8_12 28 114 #define CAM_FORMAT_DPCM_14_8_14 29 115 #define CAM_FORMAT_DPCM_14_10_14 30 116 #define CAM_FORMAT_NV21 31 117 #define CAM_FORMAT_NV12 32 118 #define CAM_FORMAT_TP10 33 119 #define CAM_FORMAT_YUV422 34 120 #define CAM_FORMAT_PD8 35 121 #define CAM_FORMAT_PD10 36 122 #define CAM_FORMAT_UBWC_NV12 37 123 #define CAM_FORMAT_UBWC_NV12_4R 38 124 #define CAM_FORMAT_UBWC_TP10 39 125 #define CAM_FORMAT_UBWC_P010 40 126 #define CAM_FORMAT_PLAIN8_SWAP 41 127 #define CAM_FORMAT_PLAIN8_10 42 128 #define CAM_FORMAT_PLAIN8_10_SWAP 43 129 #define CAM_FORMAT_YV12 44 130 #define CAM_FORMAT_Y_ONLY 45 131 #define CAM_FORMAT_DPCM_12_10_12 46 132 #define CAM_FORMAT_PLAIN32 47 133 #define CAM_FORMAT_ARGB_16 48 134 #define CAM_FORMAT_MAX 49 135 #define CAM_ROTATE_CW_0_DEGREE 0 136 #define CAM_ROTATE_CW_90_DEGREE 1 137 #define CAM_RORATE_CW_180_DEGREE 2 138 #define CAM_ROTATE_CW_270_DEGREE 3 139 #define CAM_COLOR_SPACE_BASE 0 140 #define CAM_COLOR_SPACE_BT601_FULL 1 141 #define CAM_COLOR_SPACE_BT601625 2 142 #define CAM_COLOR_SPACE_BT601525 3 143 #define CAM_COLOR_SPACE_BT709 4 144 #define CAM_COLOR_SPACE_DEPTH 5 145 #define CAM_COLOR_SPACE_MAX 6 146 #define CAM_BUF_INPUT 1 147 #define CAM_BUF_OUTPUT 2 148 #define CAM_BUF_IN_OUT 3 149 #define CAM_PACKET_DEV_BASE 0 150 #define CAM_PACKET_DEV_IMG_SENSOR 1 151 #define CAM_PACKET_DEV_ACTUATOR 2 152 #define CAM_PACKET_DEV_COMPANION 3 153 #define CAM_PACKET_DEV_EEPOM 4 154 #define CAM_PACKET_DEV_CSIPHY 5 155 #define CAM_PACKET_DEV_OIS 6 156 #define CAM_PACKET_DEV_FLASH 7 157 #define CAM_PACKET_DEV_FD 8 158 #define CAM_PACKET_DEV_JPEG_ENC 9 159 #define CAM_PACKET_DEV_JPEG_DEC 10 160 #define CAM_PACKET_DEV_VFE 11 161 #define CAM_PACKET_DEV_CPP 12 162 #define CAM_PACKET_DEV_CSID 13 163 #define CAM_PACKET_DEV_ISPIF 14 164 #define CAM_PACKET_DEV_IFE 15 165 #define CAM_PACKET_DEV_ICP 16 166 #define CAM_PACKET_DEV_LRME 17 167 #define CAM_PACKET_DEV_MAX 18 168 #define CAM_REG_DUMP_BASE_TYPE_ISP_LEFT 1 169 #define CAM_REG_DUMP_BASE_TYPE_ISP_RIGHT 2 170 #define CAM_REG_DUMP_BASE_TYPE_CAMNOC 3 171 #define CAM_REG_DUMP_READ_TYPE_CONT_RANGE 1 172 #define CAM_REG_DUMP_READ_TYPE_DMI 2 173 #define CAM_REG_DUMP_DMI_CONFIG_MAX 5 174 #define CAM_PACKET_MAX_PLANES 3 175 struct cam_plane_cfg { 176 uint32_t width; 177 uint32_t height; 178 uint32_t plane_stride; 179 uint32_t slice_height; 180 uint32_t meta_stride; 181 uint32_t meta_size; 182 uint32_t meta_offset; 183 uint32_t packer_config; 184 uint32_t mode_config; 185 uint32_t tile_config; 186 uint32_t h_init; 187 uint32_t v_init; 188 }; 189 struct cam_ubwc_plane_cfg_v1 { 190 uint32_t port_type; 191 uint32_t meta_stride; 192 uint32_t meta_size; 193 uint32_t meta_offset; 194 uint32_t packer_config; 195 uint32_t mode_config_0; 196 uint32_t mode_config_1; 197 uint32_t tile_config; 198 uint32_t h_init; 199 uint32_t v_init; 200 }; 201 struct cam_ubwc_plane_cfg_v2 { 202 uint32_t port_type; 203 uint32_t meta_stride; 204 uint32_t meta_size; 205 uint32_t meta_offset; 206 uint32_t packer_config; 207 uint32_t mode_config_0; 208 uint32_t mode_config_1; 209 uint32_t tile_config; 210 uint32_t h_init; 211 uint32_t v_init; 212 uint32_t static_ctrl; 213 uint32_t ctrl_2; 214 uint32_t stats_ctrl_2; 215 uint32_t lossy_threshold_0; 216 uint32_t lossy_threshold_1; 217 uint32_t lossy_var_offset; 218 uint32_t bandwidth_limit; 219 uint32_t reserved[3]; 220 }; 221 struct cam_cmd_buf_desc { 222 int32_t mem_handle; 223 uint32_t offset; 224 uint32_t size; 225 uint32_t length; 226 uint32_t type; 227 uint32_t meta_data; 228 }; 229 struct cam_buf_io_cfg { 230 int32_t mem_handle[CAM_PACKET_MAX_PLANES]; 231 uint32_t offsets[CAM_PACKET_MAX_PLANES]; 232 struct cam_plane_cfg planes[CAM_PACKET_MAX_PLANES]; 233 uint32_t format; 234 uint32_t color_space; 235 uint32_t color_pattern; 236 uint32_t bpp; 237 uint32_t rotation; 238 uint32_t resource_type; 239 int32_t fence; 240 int32_t early_fence; 241 struct cam_cmd_buf_desc aux_cmd_buf; 242 uint32_t direction; 243 uint32_t batch_size; 244 uint32_t subsample_pattern; 245 uint32_t subsample_period; 246 uint32_t framedrop_pattern; 247 uint32_t framedrop_period; 248 uint32_t flag; 249 uint32_t padding; 250 }; 251 struct cam_packet_header { 252 uint32_t op_code; 253 uint32_t size; 254 uint64_t request_id; 255 uint32_t flags; 256 uint32_t padding; 257 }; 258 struct cam_patch_desc { 259 int32_t dst_buf_hdl; 260 uint32_t dst_offset; 261 int32_t src_buf_hdl; 262 uint32_t src_offset; 263 }; 264 struct cam_packet { 265 struct cam_packet_header header; 266 uint32_t cmd_buf_offset; 267 uint32_t num_cmd_buf; 268 uint32_t io_configs_offset; 269 uint32_t num_io_configs; 270 uint32_t patch_offset; 271 uint32_t num_patches; 272 uint32_t kmd_cmd_buf_index; 273 uint32_t kmd_cmd_buf_offset; 274 uint64_t payload[1]; 275 }; 276 struct cam_release_dev_cmd { 277 int32_t session_handle; 278 int32_t dev_handle; 279 }; 280 struct cam_start_stop_dev_cmd { 281 int32_t session_handle; 282 int32_t dev_handle; 283 }; 284 struct cam_config_dev_cmd { 285 int32_t session_handle; 286 int32_t dev_handle; 287 uint64_t offset; 288 uint64_t packet_handle; 289 }; 290 struct cam_query_cap_cmd { 291 uint32_t size; 292 uint32_t handle_type; 293 uint64_t caps_handle; 294 }; 295 struct cam_acquire_dev_cmd { 296 int32_t session_handle; 297 int32_t dev_handle; 298 uint32_t handle_type; 299 uint32_t num_resources; 300 uint64_t resource_hdl; 301 }; 302 #define CAM_API_COMPAT_CONSTANT 0xFEFEFEFE 303 #define CAM_ACQUIRE_HW_STRUCT_VERSION_1 1 304 #define CAM_ACQUIRE_HW_STRUCT_VERSION_2 2 305 struct cam_acquire_hw_cmd_v1 { 306 uint32_t struct_version; 307 uint32_t reserved; 308 int32_t session_handle; 309 int32_t dev_handle; 310 uint32_t handle_type; 311 uint32_t data_size; 312 uint64_t resource_hdl; 313 }; 314 struct cam_acquired_hw_info { 315 uint32_t acquired_hw_id[CAM_MAX_ACQ_RES]; 316 uint32_t acquired_hw_path[CAM_MAX_ACQ_RES][CAM_MAX_HW_SPLIT]; 317 uint32_t valid_acquired_hw; 318 }; 319 struct cam_acquire_hw_cmd_v2 { 320 uint32_t struct_version; 321 uint32_t reserved; 322 int32_t session_handle; 323 int32_t dev_handle; 324 uint32_t handle_type; 325 uint32_t data_size; 326 uint64_t resource_hdl; 327 struct cam_acquired_hw_info hw_info; 328 }; 329 #define CAM_RELEASE_HW_STRUCT_VERSION_1 1 330 struct cam_release_hw_cmd_v1 { 331 uint32_t struct_version; 332 uint32_t reserved; 333 int32_t session_handle; 334 int32_t dev_handle; 335 }; 336 struct cam_flush_dev_cmd { 337 uint64_t version; 338 int32_t session_handle; 339 int32_t dev_handle; 340 uint32_t flush_type; 341 uint32_t reserved; 342 int64_t req_id; 343 }; 344 struct cam_ubwc_config { 345 uint32_t api_version; 346 uint32_t num_ports; 347 struct cam_ubwc_plane_cfg_v1 ubwc_plane_cfg[1][CAM_PACKET_MAX_PLANES - 1]; 348 }; 349 struct cam_ubwc_config_v2 { 350 uint32_t api_version; 351 uint32_t num_ports; 352 struct cam_ubwc_plane_cfg_v2 ubwc_plane_cfg[1][CAM_PACKET_MAX_PLANES - 1]; 353 }; 354 struct cam_cmd_mem_region_info { 355 int32_t mem_handle; 356 uint32_t offset; 357 uint32_t size; 358 uint32_t flags; 359 }; 360 struct cam_cmd_mem_regions { 361 uint32_t version; 362 uint32_t num_regions; 363 struct cam_cmd_mem_region_info map_info_array[1]; 364 }; 365 struct cam_reg_write_desc { 366 uint32_t offset; 367 uint32_t value; 368 }; 369 struct cam_reg_range_read_desc { 370 uint32_t offset; 371 uint32_t num_values; 372 }; 373 struct cam_dmi_read_desc { 374 uint32_t num_pre_writes; 375 uint32_t num_post_writes; 376 struct cam_reg_write_desc pre_read_config[CAM_REG_DUMP_DMI_CONFIG_MAX]; 377 struct cam_reg_range_read_desc dmi_data_read; 378 struct cam_reg_write_desc post_read_config[CAM_REG_DUMP_DMI_CONFIG_MAX]; 379 }; 380 struct cam_reg_read_info { 381 uint32_t type; 382 uint32_t reserved; 383 union { 384 struct cam_reg_range_read_desc reg_read; 385 struct cam_dmi_read_desc dmi_read; 386 }; 387 }; 388 struct cam_reg_dump_out_buffer { 389 uint64_t req_id; 390 uint32_t bytes_written; 391 uint32_t dump_data[1]; 392 }; 393 struct cam_reg_dump_desc { 394 uint32_t reg_base_type; 395 uint32_t dump_buffer_offset; 396 uint32_t dump_buffer_size; 397 uint32_t num_read_range; 398 struct cam_reg_read_info read_range[1]; 399 }; 400 struct cam_reg_dump_input_info { 401 uint32_t num_dump_sets; 402 uint32_t dump_set_offsets[1]; 403 }; 404 struct cam_dump_req_cmd { 405 uint64_t issue_req_id; 406 size_t offset; 407 uint32_t buf_handle; 408 uint32_t error_type; 409 int32_t session_handle; 410 int32_t link_hdl; 411 int32_t dev_handle; 412 }; 413 #endif 414