1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __UAPI_CAM_ISP_H__ 20 #define __UAPI_CAM_ISP_H__ 21 #include <media/cam_defs.h> 22 #include <media/cam_isp_vfe.h> 23 #include <media/cam_isp_ife.h> 24 #include <media/cam_cpas.h> 25 #define CAM_ISP_DEV_NAME "cam-isp" 26 #define CAM_ISP_HW_BASE 0 27 #define CAM_ISP_HW_CSID 1 28 #define CAM_ISP_HW_VFE 2 29 #define CAM_ISP_HW_IFE 3 30 #define CAM_ISP_HW_ISPIF 4 31 #define CAM_ISP_HW_MAX 5 32 #define CAM_ISP_PATTERN_BAYER_RGRGRG 0 33 #define CAM_ISP_PATTERN_BAYER_GRGRGR 1 34 #define CAM_ISP_PATTERN_BAYER_BGBGBG 2 35 #define CAM_ISP_PATTERN_BAYER_GBGBGB 3 36 #define CAM_ISP_PATTERN_YUV_YCBYCR 4 37 #define CAM_ISP_PATTERN_YUV_YCRYCB 5 38 #define CAM_ISP_PATTERN_YUV_CBYCRY 6 39 #define CAM_ISP_PATTERN_YUV_CRYCBY 7 40 #define CAM_ISP_PATTERN_MAX 8 41 #define CAM_ISP_RES_USAGE_SINGLE 0 42 #define CAM_ISP_RES_USAGE_DUAL 1 43 #define CAM_ISP_RES_USAGE_MAX 2 44 #define CAM_ISP_RES_ID_PORT 0 45 #define CAM_ISP_RES_ID_CLK 1 46 #define CAM_ISP_RES_ID_MAX 2 47 #define CAM_ISP_LANE_TYPE_DPHY 0 48 #define CAM_ISP_LANE_TYPE_CPHY 1 49 #define CAM_ISP_LANE_TYPE_MAX 2 50 #define CAM_ISP_RES_COMP_GROUP_NONE 0 51 #define CAM_ISP_RES_COMP_GROUP_ID_0 1 52 #define CAM_ISP_RES_COMP_GROUP_ID_1 2 53 #define CAM_ISP_RES_COMP_GROUP_ID_2 3 54 #define CAM_ISP_RES_COMP_GROUP_ID_3 4 55 #define CAM_ISP_RES_COMP_GROUP_ID_4 5 56 #define CAM_ISP_RES_COMP_GROUP_ID_5 6 57 #define CAM_ISP_RES_COMP_GROUP_ID_MAX 6 58 #define CAM_ISP_PACKET_OP_BASE 0 59 #define CAM_ISP_PACKET_INIT_DEV 1 60 #define CAM_ISP_PACKET_UPDATE_DEV 2 61 #define CAM_ISP_PACKET_OP_MAX 3 62 #define CAM_ISP_PACKET_META_BASE 0 63 #define CAM_ISP_PACKET_META_LEFT 1 64 #define CAM_ISP_PACKET_META_RIGHT 2 65 #define CAM_ISP_PACKET_META_COMMON 3 66 #define CAM_ISP_PACKET_META_DMI_LEFT 4 67 #define CAM_ISP_PACKET_META_DMI_RIGHT 5 68 #define CAM_ISP_PACKET_META_DMI_COMMON 6 69 #define CAM_ISP_PACKET_META_CLOCK 7 70 #define CAM_ISP_PACKET_META_CSID 8 71 #define CAM_ISP_PACKET_META_DUAL_CONFIG 9 72 #define CAM_ISP_PACKET_META_GENERIC_BLOB_LEFT 10 73 #define CAM_ISP_PACKET_META_GENERIC_BLOB_RIGHT 11 74 #define CAM_ISP_PACKET_META_GENERIC_BLOB_COMMON 12 75 #define CAM_ISP_PACKET_META_REG_DUMP_PER_REQUEST 13 76 #define CAM_ISP_PACKET_META_REG_DUMP_ON_FLUSH 14 77 #define CAM_ISP_PACKET_META_REG_DUMP_ON_ERROR 15 78 #define CAM_ISP_DSP_MODE_NONE 0 79 #define CAM_ISP_DSP_MODE_ONE_WAY 1 80 #define CAM_ISP_DSP_MODE_ROUND 2 81 #define CAM_ISP_GENERIC_BLOB_TYPE_HFR_CONFIG 0 82 #define CAM_ISP_GENERIC_BLOB_TYPE_CLOCK_CONFIG 1 83 #define CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG 2 84 #define CAM_ISP_GENERIC_BLOB_TYPE_UBWC_CONFIG 3 85 #define CAM_ISP_GENERIC_BLOB_TYPE_CSID_CLOCK_CONFIG 4 86 #define CAM_ISP_GENERIC_BLOB_TYPE_FE_CONFIG 5 87 #define CAM_ISP_GENERIC_BLOB_TYPE_UBWC_CONFIG_V2 6 88 #define CAM_ISP_GENERIC_BLOB_TYPE_IFE_CORE_CONFIG 7 89 #define CAM_ISP_GENERIC_BLOB_TYPE_VFE_OUT_CONFIG 8 90 #define CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG_V2 9 91 #define CAM_ISP_GENERIC_BLOB_TYPE_CSID_CONFIG 10 92 #define CAM_ISP_GENERIC_BLOB_TYPE_SENSOR_DIMENSION_CONFIG 11 93 #define CAM_ISP_GENERIC_BLOB_TYPE_CSID_QCFA_CONFIG 12 94 #define CAM_ISP_VC_DT_CFG 4 95 #define CAM_ISP_IFE0_HW 0x1 96 #define CAM_ISP_IFE1_HW 0x2 97 #define CAM_ISP_IFE0_LITE_HW 0x4 98 #define CAM_ISP_IFE1_LITE_HW 0x8 99 #define CAM_ISP_IFE2_LITE_HW 0x10 100 #define CAM_ISP_IFE2_HW 0x100 101 #define CAM_ISP_PXL_PATH 0x1 102 #define CAM_ISP_PPP_PATH 0x2 103 #define CAM_ISP_LCR_PATH 0x4 104 #define CAM_ISP_RDI0_PATH 0x8 105 #define CAM_ISP_RDI1_PATH 0x10 106 #define CAM_ISP_RDI2_PATH 0x20 107 #define CAM_ISP_RDI3_PATH 0x40 108 #define CAM_ISP_USAGE_INVALID 0 109 #define CAM_ISP_USAGE_LEFT_PX 1 110 #define CAM_ISP_USAGE_RIGHT_PX 2 111 #define CAM_ISP_USAGE_RDI 3 112 #define CAM_ISP_ACQ_CUSTOM_NONE 0 113 #define CAM_ISP_ACQ_CUSTOM_PRIMARY 1 114 #define CAM_ISP_ACQ_CUSTOM_SECONDARY 2 115 #define CAM_IFE_CSID_RDI_MAX 4 116 struct cam_isp_dev_cap_info { 117 uint32_t hw_type; 118 uint32_t reserved; 119 struct cam_hw_version hw_version; 120 }; 121 struct cam_isp_query_cap_cmd { 122 struct cam_iommu_handle device_iommu; 123 struct cam_iommu_handle cdm_iommu; 124 int32_t num_dev; 125 uint32_t reserved; 126 struct cam_isp_dev_cap_info dev_caps[CAM_ISP_HW_MAX]; 127 }; 128 struct cam_isp_out_port_info { 129 uint32_t res_type; 130 uint32_t format; 131 uint32_t width; 132 uint32_t height; 133 uint32_t comp_grp_id; 134 uint32_t split_point; 135 uint32_t secure_mode; 136 uint32_t reserved; 137 }; 138 struct cam_isp_out_port_info_v2 { 139 uint32_t res_type; 140 uint32_t format; 141 uint32_t width; 142 uint32_t height; 143 uint32_t comp_grp_id; 144 uint32_t split_point; 145 uint32_t secure_mode; 146 uint32_t wm_mode; 147 uint32_t out_port_res1; 148 uint32_t out_port_res2; 149 }; 150 struct cam_isp_in_port_info { 151 uint32_t res_type; 152 uint32_t lane_type; 153 uint32_t lane_num; 154 uint32_t lane_cfg; 155 uint32_t vc; 156 uint32_t dt; 157 uint32_t format; 158 uint32_t test_pattern; 159 uint32_t usage_type; 160 uint32_t left_start; 161 uint32_t left_stop; 162 uint32_t left_width; 163 uint32_t right_start; 164 uint32_t right_stop; 165 uint32_t right_width; 166 uint32_t line_start; 167 uint32_t line_stop; 168 uint32_t height; 169 uint32_t pixel_clk; 170 uint32_t batch_size; 171 uint32_t dsp_mode; 172 uint32_t hbi_cnt; 173 uint32_t reserved; 174 uint32_t num_out_res; 175 struct cam_isp_out_port_info data[1]; 176 }; 177 struct cam_isp_in_port_info_v2 { 178 uint32_t res_type; 179 uint32_t lane_type; 180 uint32_t lane_num; 181 uint32_t lane_cfg; 182 uint32_t vc[CAM_ISP_VC_DT_CFG]; 183 uint32_t dt[CAM_ISP_VC_DT_CFG]; 184 uint32_t num_valid_vc_dt; 185 uint32_t format; 186 uint32_t test_pattern; 187 uint32_t usage_type; 188 uint32_t left_start; 189 uint32_t left_stop; 190 uint32_t left_width; 191 uint32_t right_start; 192 uint32_t right_stop; 193 uint32_t right_width; 194 uint32_t line_start; 195 uint32_t line_stop; 196 uint32_t height; 197 uint32_t pixel_clk; 198 uint32_t batch_size; 199 uint32_t dsp_mode; 200 uint32_t hbi_cnt; 201 uint32_t cust_node; 202 uint32_t num_out_res; 203 uint32_t offline_mode; 204 uint32_t horizontal_bin; 205 uint32_t qcfa_bin; 206 uint32_t csid_res_1; 207 uint32_t csid_res_2; 208 uint32_t ife_res_1; 209 uint32_t ife_res_2; 210 struct cam_isp_out_port_info_v2 data[1]; 211 }; 212 struct cam_isp_resource { 213 uint32_t resource_id; 214 uint32_t length; 215 uint32_t handle_type; 216 uint32_t reserved; 217 uint64_t res_hdl; 218 }; 219 struct cam_isp_port_hfr_config { 220 uint32_t resource_type; 221 uint32_t subsample_pattern; 222 uint32_t subsample_period; 223 uint32_t framedrop_pattern; 224 uint32_t framedrop_period; 225 uint32_t reserved; 226 } __attribute__((packed)); 227 struct cam_isp_resource_hfr_config { 228 uint32_t num_ports; 229 uint32_t reserved; 230 struct cam_isp_port_hfr_config port_hfr_config[1]; 231 } __attribute__((packed)); 232 struct cam_isp_dual_split_params { 233 uint32_t split_point; 234 uint32_t right_padding; 235 uint32_t left_padding; 236 uint32_t reserved; 237 }; 238 struct cam_isp_dual_stripe_config { 239 uint32_t offset; 240 uint32_t width; 241 uint32_t tileconfig; 242 uint32_t port_id; 243 }; 244 struct cam_isp_dual_config { 245 uint32_t num_ports; 246 uint32_t reserved; 247 struct cam_isp_dual_split_params split_params; 248 struct cam_isp_dual_stripe_config stripes[1]; 249 } __attribute__((packed)); 250 struct cam_isp_clock_config { 251 uint32_t usage_type; 252 uint32_t num_rdi; 253 uint64_t left_pix_hz; 254 uint64_t right_pix_hz; 255 uint64_t rdi_hz[1]; 256 } __attribute__((packed)); 257 struct cam_isp_csid_clock_config { 258 uint64_t csid_clock; 259 } __attribute__((packed)); 260 struct cam_isp_csid_qcfa_config { 261 uint32_t csid_binning; 262 } __attribute__((packed)); 263 struct cam_isp_bw_vote { 264 uint32_t resource_id; 265 uint32_t reserved; 266 uint64_t cam_bw_bps; 267 uint64_t ext_bw_bps; 268 } __attribute__((packed)); 269 struct cam_isp_bw_config { 270 uint32_t usage_type; 271 uint32_t num_rdi; 272 struct cam_isp_bw_vote left_pix_vote; 273 struct cam_isp_bw_vote right_pix_vote; 274 struct cam_isp_bw_vote rdi_vote[1]; 275 } __attribute__((packed)); 276 struct cam_isp_bw_config_v2 { 277 uint32_t usage_type; 278 uint32_t num_paths; 279 struct cam_axi_per_path_bw_vote axi_path[1]; 280 } __attribute__((packed)); 281 struct cam_fe_config { 282 uint64_t version; 283 uint32_t min_vbi; 284 uint32_t fs_mode; 285 uint32_t fs_line_sync_en; 286 uint32_t hbi_count; 287 uint32_t fs_sync_enable; 288 uint32_t go_cmd_sel; 289 uint32_t client_enable; 290 uint32_t source_addr; 291 uint32_t width; 292 uint32_t height; 293 uint32_t stride; 294 uint32_t format; 295 uint32_t unpacker_cfg; 296 uint32_t latency_buf_size; 297 } __attribute__((packed)); 298 struct cam_isp_sensor_dimension { 299 uint32_t width; 300 uint32_t height; 301 uint32_t measure_enabled; 302 } __attribute__((packed)); 303 struct cam_isp_sensor_config { 304 struct cam_isp_sensor_dimension ppp_path; 305 struct cam_isp_sensor_dimension ipp_path; 306 struct cam_isp_sensor_dimension rdi_path[CAM_IFE_CSID_RDI_MAX]; 307 uint32_t hbi; 308 uint32_t vbi; 309 } __attribute__((packed)); 310 struct cam_isp_core_config { 311 uint32_t version; 312 uint32_t vid_ds16_r2pd; 313 uint32_t vid_ds4_r2pd; 314 uint32_t disp_ds16_r2pd; 315 uint32_t disp_ds4_r2pd; 316 uint32_t dsp_streaming_tap_point; 317 uint32_t ihist_src_sel; 318 uint32_t hdr_be_src_sel; 319 uint32_t hdr_bhist_src_sel; 320 uint32_t input_mux_sel_pdaf; 321 uint32_t input_mux_sel_pp; 322 uint32_t reserved; 323 } __attribute__((packed)); 324 struct cam_isp_acquire_hw_info { 325 uint16_t common_info_version; 326 uint16_t common_info_size; 327 uint32_t common_info_offset; 328 uint32_t num_inputs; 329 uint32_t input_info_version; 330 uint32_t input_info_size; 331 uint32_t input_info_offset; 332 uint64_t data; 333 }; 334 struct cam_isp_vfe_wm_config { 335 uint32_t port_type; 336 uint32_t wm_mode; 337 uint32_t h_init; 338 uint32_t height; 339 uint32_t width; 340 uint32_t virtual_frame_en; 341 uint32_t stride; 342 uint32_t offset; 343 uint32_t reserved_1; 344 uint32_t reserved_2; 345 uint32_t reserved_3; 346 uint32_t reserved_4; 347 }; 348 struct cam_isp_vfe_out_config { 349 uint32_t num_ports; 350 uint32_t reserved; 351 struct cam_isp_vfe_wm_config wm_config[1]; 352 }; 353 struct cam_isp_csid_epd_config { 354 uint32_t is_epd_supported; 355 }; 356 #define CAM_ISP_ACQUIRE_COMMON_VER0 0x1000 357 #define CAM_ISP_ACQUIRE_COMMON_SIZE_VER0 0x0 358 #define CAM_ISP_ACQUIRE_INPUT_VER0 0x2000 359 #define CAM_ISP_ACQUIRE_INPUT_SIZE_VER0 sizeof(struct cam_isp_in_port_info) 360 #define CAM_ISP_ACQUIRE_OUT_VER0 0x3000 361 #define CAM_ISP_ACQUIRE_OUT_SIZE_VER0 sizeof(struct cam_isp_out_port_info) 362 #endif 363