1 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ 2 /* 3 * Copyright (c) 2017-2018, 2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _SDE_DRM_H_ 7 #define _SDE_DRM_H_ 8 9 #include "drm.h" 10 11 /* Total number of supported color planes */ 12 #define SDE_MAX_PLANES 4 13 14 /* Total number of parameterized detail enhancer mapping curves */ 15 #define SDE_MAX_DE_CURVES 3 16 17 /* Y/RGB and UV filter configuration */ 18 #define FILTER_EDGE_DIRECTED_2D 0x0 19 #define FILTER_CIRCULAR_2D 0x1 20 #define FILTER_SEPARABLE_1D 0x2 21 #define FILTER_BILINEAR 0x3 22 23 /* Alpha filters */ 24 #define FILTER_ALPHA_DROP_REPEAT 0x0 25 #define FILTER_ALPHA_BILINEAR 0x1 26 #define FILTER_ALPHA_2D 0x3 27 28 /* Blend filters */ 29 #define FILTER_BLEND_CIRCULAR_2D 0x0 30 #define FILTER_BLEND_SEPARABLE_1D 0x1 31 32 /* LUT configuration flags */ 33 #define SCALER_LUT_SWAP 0x1 34 #define SCALER_LUT_DIR_WR 0x2 35 #define SCALER_LUT_Y_CIR_WR 0x4 36 #define SCALER_LUT_UV_CIR_WR 0x8 37 #define SCALER_LUT_Y_SEP_WR 0x10 38 #define SCALER_LUT_UV_SEP_WR 0x20 39 40 /** 41 * Blend operations for "blend_op" property 42 * 43 * @SDE_DRM_BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. 44 * @SDE_DRM_BLEND_OP_OPAQUE: Apply a constant blend operation. The layer 45 * would appear opaque in case fg plane alpha 46 * is 0xff. 47 * @SDE_DRM_BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already 48 * has alpha pre-multiplication done. If the fg 49 * plane alpha is less than 0xff, apply 50 * modulation as well. This operation is 51 * intended on layers having alpha channel. 52 * @SDE_DRM_BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not 53 * alpha pre-multiplied. Apply 54 * pre-multiplication. If fg plane alpha is 55 * less than 0xff, apply modulation as well. 56 * @SDE_DRM_BLEND_OP_MAX: Used to track maximum blend operation 57 * possible by mdp. 58 */ 59 #define SDE_DRM_BLEND_OP_NOT_DEFINED 0 60 #define SDE_DRM_BLEND_OP_OPAQUE 1 61 #define SDE_DRM_BLEND_OP_PREMULTIPLIED 2 62 #define SDE_DRM_BLEND_OP_COVERAGE 3 63 #define SDE_DRM_BLEND_OP_MAX 4 64 65 /** 66 * Bit masks for "src_config" property 67 * construct bitmask via (1UL << SDE_DRM_<flag>) 68 */ 69 #define SDE_DRM_DEINTERLACE 0 /* Specifies interlaced input */ 70 71 /* DRM bitmasks are restricted to 0..63 */ 72 #define SDE_DRM_BITMASK_COUNT 64 73 74 /** 75 * Framebuffer modes for "fb_translation_mode" PLANE and CONNECTOR property 76 * 77 * @SDE_DRM_FB_NON_SEC: IOMMU configuration for this framebuffer mode 78 * is non-secure domain and requires 79 * both stage I and stage II translations when 80 * this buffer is accessed by the display HW. 81 * This is the default mode of all frambuffers. 82 * @SDE_DRM_FB_SEC: IOMMU configuration for this framebuffer mode 83 * is secure domain and requires 84 * both stage I and stage II translations when 85 * this buffer is accessed by the display HW. 86 * @SDE_DRM_FB_NON_SEC_DIR_TRANS: IOMMU configuration for this framebuffer mode 87 * is non-secure domain and requires 88 * only stage II translation when 89 * this buffer is accessed by the display HW. 90 * @SDE_DRM_FB_SEC_DIR_TRANS: IOMMU configuration for this framebuffer mode 91 * is secure domain and requires 92 * only stage II translation when 93 * this buffer is accessed by the display HW. 94 */ 95 96 #define SDE_DRM_FB_NON_SEC 0 97 #define SDE_DRM_FB_SEC 1 98 #define SDE_DRM_FB_NON_SEC_DIR_TRANS 2 99 #define SDE_DRM_FB_SEC_DIR_TRANS 3 100 101 /** 102 * Secure levels for "security_level" CRTC property. 103 * CRTC property which specifies what plane types 104 * can be attached to this CRTC. Plane component 105 * derives the plane type based on the FB_MODE. 106 * @ SDE_DRM_SEC_NON_SEC: Both Secure and non-secure plane types can be 107 * attached to this CRTC. This is the default state of 108 * the CRTC. 109 * @ SDE_DRM_SEC_ONLY: Only secure planes can be added to this CRTC. If a 110 * CRTC is instructed to be in this mode it follows the 111 * platform dependent restrictions. 112 */ 113 #define SDE_DRM_SEC_NON_SEC 0 114 #define SDE_DRM_SEC_ONLY 1 115 116 /** 117 * struct sde_drm_pix_ext_v1 - version 1 of pixel ext structure 118 * @num_ext_pxls_lr: Number of total horizontal pixels 119 * @num_ext_pxls_tb: Number of total vertical lines 120 * @left_ftch: Number of extra pixels to overfetch from left 121 * @right_ftch: Number of extra pixels to overfetch from right 122 * @top_ftch: Number of extra lines to overfetch from top 123 * @btm_ftch: Number of extra lines to overfetch from bottom 124 * @left_rpt: Number of extra pixels to repeat from left 125 * @right_rpt: Number of extra pixels to repeat from right 126 * @top_rpt: Number of extra lines to repeat from top 127 * @btm_rpt: Number of extra lines to repeat from bottom 128 */ 129 struct sde_drm_pix_ext_v1 { 130 /* 131 * Number of pixels ext in left, right, top and bottom direction 132 * for all color components. 133 */ 134 int32_t num_ext_pxls_lr[SDE_MAX_PLANES]; 135 int32_t num_ext_pxls_tb[SDE_MAX_PLANES]; 136 137 /* 138 * Number of pixels needs to be overfetched in left, right, top 139 * and bottom directions from source image for scaling. 140 */ 141 int32_t left_ftch[SDE_MAX_PLANES]; 142 int32_t right_ftch[SDE_MAX_PLANES]; 143 int32_t top_ftch[SDE_MAX_PLANES]; 144 int32_t btm_ftch[SDE_MAX_PLANES]; 145 /* 146 * Number of pixels needs to be repeated in left, right, top and 147 * bottom directions for scaling. 148 */ 149 int32_t left_rpt[SDE_MAX_PLANES]; 150 int32_t right_rpt[SDE_MAX_PLANES]; 151 int32_t top_rpt[SDE_MAX_PLANES]; 152 int32_t btm_rpt[SDE_MAX_PLANES]; 153 154 }; 155 156 /** 157 * struct sde_drm_scaler_v1 - version 1 of struct sde_drm_scaler 158 * @lr: Pixel extension settings for left/right 159 * @tb: Pixel extension settings for top/botton 160 * @init_phase_x: Initial scaler phase values for x 161 * @phase_step_x: Phase step values for x 162 * @init_phase_y: Initial scaler phase values for y 163 * @phase_step_y: Phase step values for y 164 * @horz_filter: Horizontal filter array 165 * @vert_filter: Vertical filter array 166 */ 167 struct sde_drm_scaler_v1 { 168 /* 169 * Pix ext settings 170 */ 171 struct sde_drm_pix_ext_v1 pe; 172 /* 173 * Phase settings 174 */ 175 int32_t init_phase_x[SDE_MAX_PLANES]; 176 int32_t phase_step_x[SDE_MAX_PLANES]; 177 int32_t init_phase_y[SDE_MAX_PLANES]; 178 int32_t phase_step_y[SDE_MAX_PLANES]; 179 180 /* 181 * Filter type to be used for scaling in horizontal and vertical 182 * directions 183 */ 184 uint32_t horz_filter[SDE_MAX_PLANES]; 185 uint32_t vert_filter[SDE_MAX_PLANES]; 186 }; 187 188 /** 189 * struct sde_drm_de_v1 - version 1 of detail enhancer structure 190 * @enable: Enables/disables detail enhancer 191 * @sharpen_level1: Sharpening strength for noise 192 * @sharpen_level2: Sharpening strength for context 193 * @clip: Clip coefficient 194 * @limit: Detail enhancer limit factor 195 * @thr_quiet: Quite zone threshold 196 * @thr_dieout: Die-out zone threshold 197 * @thr_low: Linear zone left threshold 198 * @thr_high: Linear zone right threshold 199 * @prec_shift: Detail enhancer precision 200 * @adjust_a: Mapping curves A coefficients 201 * @adjust_b: Mapping curves B coefficients 202 * @adjust_c: Mapping curves C coefficients 203 */ 204 struct sde_drm_de_v1 { 205 uint32_t enable; 206 int16_t sharpen_level1; 207 int16_t sharpen_level2; 208 uint16_t clip; 209 uint16_t limit; 210 uint16_t thr_quiet; 211 uint16_t thr_dieout; 212 uint16_t thr_low; 213 uint16_t thr_high; 214 uint16_t prec_shift; 215 int16_t adjust_a[SDE_MAX_DE_CURVES]; 216 int16_t adjust_b[SDE_MAX_DE_CURVES]; 217 int16_t adjust_c[SDE_MAX_DE_CURVES]; 218 }; 219 220 /* 221 * Scaler configuration flags 222 */ 223 224 /* Disable dynamic expansion */ 225 #define SDE_DYN_EXP_DISABLE 0x1 226 227 #define SDE_DRM_QSEED3LITE 228 #define SDE_DRM_QSEED4 229 #define SDE_DRM_INLINE_PREDOWNSCALE 230 231 /** 232 * struct sde_drm_scaler_v2 - version 2 of struct sde_drm_scaler 233 * @enable: Scaler enable 234 * @dir_en: Detail enhancer enable 235 * @pe: Pixel extension settings 236 * @horz_decimate: Horizontal decimation factor 237 * @vert_decimate: Vertical decimation factor 238 * @init_phase_x: Initial scaler phase values for x 239 * @phase_step_x: Phase step values for x 240 * @init_phase_y: Initial scaler phase values for y 241 * @phase_step_y: Phase step values for y 242 * @preload_x: Horizontal preload value 243 * @preload_y: Vertical preload value 244 * @src_width: Source width 245 * @src_height: Source height 246 * @dst_width: Destination width 247 * @dst_height: Destination height 248 * @y_rgb_filter_cfg: Y/RGB plane filter configuration 249 * @uv_filter_cfg: UV plane filter configuration 250 * @alpha_filter_cfg: Alpha filter configuration 251 * @blend_cfg: Selection of blend coefficients 252 * @lut_flag: LUT configuration flags 253 * @dir_lut_idx: 2d 4x4 LUT index 254 * @y_rgb_cir_lut_idx: Y/RGB circular LUT index 255 * @uv_cir_lut_idx: UV circular LUT index 256 * @y_rgb_sep_lut_idx: Y/RGB separable LUT index 257 * @uv_sep_lut_idx: UV separable LUT index 258 * @de: Detail enhancer settings 259 * @dir_weight: Directional Weight 260 * @unsharp_mask_blend: Unsharp Blend Filter Ratio 261 * @de_blend: Ratio of two unsharp mask filters 262 * @flags: Scaler configuration flags 263 * @pre_downscale_x_0 Pre-downscale ratio, x-direction, plane 0(Y/RGB) 264 * @pre_downscale_x_1 Pre-downscale ratio, x-direction, plane 1(UV) 265 * @pre_downscale_y_0 Pre-downscale ratio, y-direction, plane 0(Y/RGB) 266 * @pre_downscale_y_1 Pre-downscale ratio, y-direction, plane 1(UV) 267 */ 268 struct sde_drm_scaler_v2 { 269 /* 270 * General definitions 271 */ 272 uint32_t enable; 273 uint32_t dir_en; 274 275 /* 276 * Pix ext settings 277 */ 278 struct sde_drm_pix_ext_v1 pe; 279 280 /* 281 * Decimation settings 282 */ 283 uint32_t horz_decimate; 284 uint32_t vert_decimate; 285 286 /* 287 * Phase settings 288 */ 289 int32_t init_phase_x[SDE_MAX_PLANES]; 290 int32_t phase_step_x[SDE_MAX_PLANES]; 291 int32_t init_phase_y[SDE_MAX_PLANES]; 292 int32_t phase_step_y[SDE_MAX_PLANES]; 293 294 uint32_t preload_x[SDE_MAX_PLANES]; 295 uint32_t preload_y[SDE_MAX_PLANES]; 296 uint32_t src_width[SDE_MAX_PLANES]; 297 uint32_t src_height[SDE_MAX_PLANES]; 298 299 uint32_t dst_width; 300 uint32_t dst_height; 301 302 uint32_t y_rgb_filter_cfg; 303 uint32_t uv_filter_cfg; 304 uint32_t alpha_filter_cfg; 305 uint32_t blend_cfg; 306 307 uint32_t lut_flag; 308 uint32_t dir_lut_idx; 309 310 /* for Y(RGB) and UV planes*/ 311 uint32_t y_rgb_cir_lut_idx; 312 uint32_t uv_cir_lut_idx; 313 uint32_t y_rgb_sep_lut_idx; 314 uint32_t uv_sep_lut_idx; 315 316 /* 317 * Detail enhancer settings 318 */ 319 struct sde_drm_de_v1 de; 320 uint32_t dir_weight; 321 uint32_t unsharp_mask_blend; 322 uint32_t de_blend; 323 uint32_t flags; 324 325 /* 326 * Inline pre-downscale settings 327 */ 328 uint32_t pre_downscale_x_0; 329 uint32_t pre_downscale_x_1; 330 uint32_t pre_downscale_y_0; 331 uint32_t pre_downscale_y_1; 332 }; 333 334 /* Number of dest scalers supported */ 335 #define SDE_MAX_DS_COUNT 2 336 337 /* 338 * Destination scaler flag config 339 */ 340 #define SDE_DRM_DESTSCALER_ENABLE 0x1 341 #define SDE_DRM_DESTSCALER_SCALE_UPDATE 0x2 342 #define SDE_DRM_DESTSCALER_ENHANCER_UPDATE 0x4 343 #define SDE_DRM_DESTSCALER_PU_ENABLE 0x8 344 345 /** 346 * struct sde_drm_dest_scaler_cfg - destination scaler config structure 347 * @flags: Flag to switch between mode for destination scaler 348 * refer to destination scaler flag config 349 * @index: Destination scaler selection index 350 * @lm_width: Layer mixer width configuration 351 * @lm_height: Layer mixer height configuration 352 * @scaler_cfg: The scaling parameters for all the mode except disable 353 * Userspace pointer to struct sde_drm_scaler_v2 354 */ 355 struct sde_drm_dest_scaler_cfg { 356 uint32_t flags; 357 uint32_t index; 358 uint32_t lm_width; 359 uint32_t lm_height; 360 uint64_t scaler_cfg; 361 }; 362 363 /** 364 * struct sde_drm_dest_scaler_data - destination scaler data struct 365 * @num_dest_scaler: Number of dest scalers to be configured 366 * @ds_cfg: Destination scaler block configuration 367 */ 368 struct sde_drm_dest_scaler_data { 369 uint32_t num_dest_scaler; 370 struct sde_drm_dest_scaler_cfg ds_cfg[SDE_MAX_DS_COUNT]; 371 }; 372 373 /* 374 * Define constants for struct sde_drm_csc 375 */ 376 #define SDE_CSC_MATRIX_COEFF_SIZE 9 377 #define SDE_CSC_CLAMP_SIZE 6 378 #define SDE_CSC_BIAS_SIZE 3 379 380 /** 381 * struct sde_drm_csc_v1 - version 1 of struct sde_drm_csc 382 * @ctm_coeff: Matrix coefficients, in S31.32 format 383 * @pre_bias: Pre-bias array values 384 * @post_bias: Post-bias array values 385 * @pre_clamp: Pre-clamp array values 386 * @post_clamp: Post-clamp array values 387 */ 388 struct sde_drm_csc_v1 { 389 int64_t ctm_coeff[SDE_CSC_MATRIX_COEFF_SIZE]; 390 uint32_t pre_bias[SDE_CSC_BIAS_SIZE]; 391 uint32_t post_bias[SDE_CSC_BIAS_SIZE]; 392 uint32_t pre_clamp[SDE_CSC_CLAMP_SIZE]; 393 uint32_t post_clamp[SDE_CSC_CLAMP_SIZE]; 394 }; 395 396 /** 397 * struct sde_drm_color - struct to store the color and alpha values 398 * @color_0: Color 0 value 399 * @color_1: Color 1 value 400 * @color_2: Color 2 value 401 * @color_3: Color 3 value 402 */ 403 struct sde_drm_color { 404 uint32_t color_0; 405 uint32_t color_1; 406 uint32_t color_2; 407 uint32_t color_3; 408 }; 409 410 /* Total number of supported dim layers */ 411 #define SDE_MAX_DIM_LAYERS 7 412 413 /* SDE_DRM_DIM_LAYER_CONFIG_FLAG - flags for Dim Layer */ 414 /* Color fill inside of the rect, including border */ 415 #define SDE_DRM_DIM_LAYER_INCLUSIVE 0x1 416 /* Color fill outside of the rect, excluding border */ 417 #define SDE_DRM_DIM_LAYER_EXCLUSIVE 0x2 418 419 /** 420 * struct sde_drm_dim_layer - dim layer cfg struct 421 * @flags: Refer SDE_DRM_DIM_LAYER_CONFIG_FLAG for possible values 422 * @stage: Blending stage of the dim layer 423 * @color_fill: Color fill for dim layer 424 * @rect: Dim layer coordinates 425 */ 426 struct sde_drm_dim_layer_cfg { 427 uint32_t flags; 428 uint32_t stage; 429 struct sde_drm_color color_fill; 430 struct drm_clip_rect rect; 431 }; 432 433 /** 434 * struct sde_drm_dim_layer_v1 - version 1 of dim layer struct 435 * @num_layers: Numer of Dim Layers 436 * @layer: Dim layer user cfgs ptr for the num_layers 437 */ 438 struct sde_drm_dim_layer_v1 { 439 uint32_t num_layers; 440 struct sde_drm_dim_layer_cfg layer_cfg[SDE_MAX_DIM_LAYERS]; 441 }; 442 443 /* Writeback Config version definition */ 444 #define SDE_DRM_WB_CFG 0x1 445 446 /* SDE_DRM_WB_CONFIG_FLAGS - Writeback configuration flags */ 447 #define SDE_DRM_WB_CFG_FLAGS_CONNECTED (1<<0) 448 449 /** 450 * struct sde_drm_wb_cfg - Writeback configuration structure 451 * @flags: see DRM_MSM_WB_CONFIG_FLAGS 452 * @connector_id: writeback connector identifier 453 * @count_modes: Count of modes in modes_ptr 454 * @modes: Pointer to struct drm_mode_modeinfo 455 */ 456 struct sde_drm_wb_cfg { 457 uint32_t flags; 458 uint32_t connector_id; 459 uint32_t count_modes; 460 uint64_t modes; 461 }; 462 463 #define SDE_MAX_ROI_V1 4 464 465 /** 466 * struct sde_drm_roi_v1 - list of regions of interest for a drm object 467 * @num_rects: number of valid rectangles in the roi array 468 * @roi: list of roi rectangles 469 */ 470 struct sde_drm_roi_v1 { 471 uint32_t num_rects; 472 struct drm_clip_rect roi[SDE_MAX_ROI_V1]; 473 }; 474 475 /** 476 * Define extended power modes supported by the SDE connectors. 477 */ 478 #define SDE_MODE_DPMS_ON 0 479 #define SDE_MODE_DPMS_LP1 1 480 #define SDE_MODE_DPMS_LP2 2 481 #define SDE_MODE_DPMS_STANDBY 3 482 #define SDE_MODE_DPMS_SUSPEND 4 483 #define SDE_MODE_DPMS_OFF 5 484 485 /** 486 * sde recovery events for notifying client 487 */ 488 #define SDE_RECOVERY_SUCCESS 0 489 #define SDE_RECOVERY_CAPTURE 1 490 #define SDE_RECOVERY_HARD_RESET 2 491 492 #endif /* _SDE_DRM_H_ */ 493