1 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ 2 /* 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _MSM_NPU_H_ 7 #define _MSM_NPU_H_ 8 9 /* ------------------------------------------------------------------------- 10 * Includes 11 * ------------------------------------------------------------------------- 12 */ 13 #include <linux/types.h> 14 15 /* ------------------------------------------------------------------------- 16 * Defines 17 * ------------------------------------------------------------------------- 18 */ 19 #define MSM_NPU_IOCTL_MAGIC 'n' 20 21 /* get npu info */ 22 #define MSM_NPU_GET_INFO \ 23 _IOWR(MSM_NPU_IOCTL_MAGIC, 1, struct msm_npu_get_info_ioctl) 24 25 /* map buf */ 26 #define MSM_NPU_MAP_BUF \ 27 _IOWR(MSM_NPU_IOCTL_MAGIC, 2, struct msm_npu_map_buf_ioctl) 28 29 /* map buf */ 30 #define MSM_NPU_UNMAP_BUF \ 31 _IOWR(MSM_NPU_IOCTL_MAGIC, 3, struct msm_npu_unmap_buf_ioctl) 32 33 /* load network */ 34 #define MSM_NPU_LOAD_NETWORK \ 35 _IOWR(MSM_NPU_IOCTL_MAGIC, 4, struct msm_npu_load_network_ioctl) 36 37 /* unload network */ 38 #define MSM_NPU_UNLOAD_NETWORK \ 39 _IOWR(MSM_NPU_IOCTL_MAGIC, 5, struct msm_npu_unload_network_ioctl) 40 41 /* exec network */ 42 #define MSM_NPU_EXEC_NETWORK \ 43 _IOWR(MSM_NPU_IOCTL_MAGIC, 6, struct msm_npu_exec_network_ioctl) 44 45 /* load network v2 */ 46 #define MSM_NPU_LOAD_NETWORK_V2 \ 47 _IOWR(MSM_NPU_IOCTL_MAGIC, 7, struct msm_npu_load_network_ioctl_v2) 48 49 /* exec network v2 */ 50 #define MSM_NPU_EXEC_NETWORK_V2 \ 51 _IOWR(MSM_NPU_IOCTL_MAGIC, 8, struct msm_npu_exec_network_ioctl_v2) 52 53 /* receive event */ 54 #define MSM_NPU_RECEIVE_EVENT \ 55 _IOR(MSM_NPU_IOCTL_MAGIC, 9, struct msm_npu_event) 56 57 /* set property */ 58 #define MSM_NPU_SET_PROP \ 59 _IOW(MSM_NPU_IOCTL_MAGIC, 10, struct msm_npu_property) 60 61 /* get property */ 62 #define MSM_NPU_GET_PROP \ 63 _IOW(MSM_NPU_IOCTL_MAGIC, 11, struct msm_npu_property) 64 65 #define MSM_NPU_EVENT_TYPE_START 0x10000000 66 #define MSM_NPU_EVENT_TYPE_EXEC_DONE (MSM_NPU_EVENT_TYPE_START + 1) 67 #define MSM_NPU_EVENT_TYPE_EXEC_V2_DONE (MSM_NPU_EVENT_TYPE_START + 2) 68 #define MSM_NPU_EVENT_TYPE_SSR (MSM_NPU_EVENT_TYPE_START + 3) 69 70 #define MSM_NPU_MAX_INPUT_LAYER_NUM 8 71 #define MSM_NPU_MAX_OUTPUT_LAYER_NUM 4 72 #define MSM_NPU_MAX_PATCH_LAYER_NUM (MSM_NPU_MAX_INPUT_LAYER_NUM +\ 73 MSM_NPU_MAX_OUTPUT_LAYER_NUM) 74 75 #define MSM_NPU_PROP_ID_START 0x100 76 #define MSM_NPU_PROP_ID_FW_STATE (MSM_NPU_PROP_ID_START + 0) 77 #define MSM_NPU_PROP_ID_PERF_MODE (MSM_NPU_PROP_ID_START + 1) 78 #define MSM_NPU_PROP_ID_PERF_MODE_MAX (MSM_NPU_PROP_ID_START + 2) 79 #define MSM_NPU_PROP_ID_DRV_VERSION (MSM_NPU_PROP_ID_START + 3) 80 #define MSM_NPU_PROP_ID_HARDWARE_VERSION (MSM_NPU_PROP_ID_START + 4) 81 #define MSM_NPU_PROP_ID_IPC_QUEUE_INFO (MSM_NPU_PROP_ID_START + 5) 82 #define MSM_NPU_PROP_ID_DRV_FEATURE (MSM_NPU_PROP_ID_START + 6) 83 84 #define MSM_NPU_FW_PROP_ID_START 0x1000 85 #define MSM_NPU_PROP_ID_DCVS_MODE (MSM_NPU_FW_PROP_ID_START + 0) 86 #define MSM_NPU_PROP_ID_DCVS_MODE_MAX (MSM_NPU_FW_PROP_ID_START + 1) 87 #define MSM_NPU_PROP_ID_CLK_GATING_MODE (MSM_NPU_FW_PROP_ID_START + 2) 88 #define MSM_NPU_PROP_ID_HW_VERSION (MSM_NPU_FW_PROP_ID_START + 3) 89 #define MSM_NPU_PROP_ID_FW_VERSION (MSM_NPU_FW_PROP_ID_START + 4) 90 #define MSM_NPU_PROP_ID_FW_GETCAPS (MSM_NPU_FW_PROP_ID_START + 5) 91 92 /* features supported by driver */ 93 #define MSM_NPU_FEATURE_MULTI_EXECUTE 0x1 94 #define MSM_NPU_FEATURE_ASYNC_EXECUTE 0x2 95 96 #define PROP_PARAM_MAX_SIZE 8 97 98 /* ------------------------------------------------------------------------- 99 * Data Structures 100 * ------------------------------------------------------------------------- 101 */ 102 struct msm_npu_patch_info { 103 /* chunk id */ 104 uint32_t chunk_id; 105 /* instruction size in bytes */ 106 uint16_t instruction_size_in_bytes; 107 /* variable size in bits */ 108 uint16_t variable_size_in_bits; 109 /* shift value in bits */ 110 uint16_t shift_value_in_bits; 111 /* location offset */ 112 uint32_t loc_offset; 113 }; 114 115 struct msm_npu_layer { 116 /* layer id */ 117 uint32_t layer_id; 118 /* patch information*/ 119 struct msm_npu_patch_info patch_info; 120 /* buffer handle */ 121 int32_t buf_hdl; 122 /* buffer size */ 123 uint32_t buf_size; 124 /* physical address */ 125 uint64_t buf_phys_addr; 126 }; 127 128 struct msm_npu_patch_info_v2 { 129 /* patch value */ 130 uint32_t value; 131 /* chunk id */ 132 uint32_t chunk_id; 133 /* instruction size in bytes */ 134 uint32_t instruction_size_in_bytes; 135 /* variable size in bits */ 136 uint32_t variable_size_in_bits; 137 /* shift value in bits */ 138 uint32_t shift_value_in_bits; 139 /* location offset */ 140 uint32_t loc_offset; 141 }; 142 143 struct msm_npu_patch_buf_info { 144 /* physical address to be patched */ 145 uint64_t buf_phys_addr; 146 /* buffer id */ 147 uint32_t buf_id; 148 }; 149 150 /* ------------------------------------------------------------------------- 151 * Data Structures - IOCTLs 152 * ------------------------------------------------------------------------- 153 */ 154 struct msm_npu_map_buf_ioctl { 155 /* buffer ion handle */ 156 int32_t buf_ion_hdl; 157 /* buffer size */ 158 uint32_t size; 159 /* iommu mapped physical address */ 160 uint64_t npu_phys_addr; 161 }; 162 163 struct msm_npu_unmap_buf_ioctl { 164 /* buffer ion handle */ 165 int32_t buf_ion_hdl; 166 /* iommu mapped physical address */ 167 uint64_t npu_phys_addr; 168 }; 169 170 struct msm_npu_get_info_ioctl { 171 /* firmware version */ 172 uint32_t firmware_version; 173 /* reserved */ 174 uint32_t flags; 175 }; 176 177 struct msm_npu_load_network_ioctl { 178 /* buffer ion handle */ 179 int32_t buf_ion_hdl; 180 /* physical address */ 181 uint64_t buf_phys_addr; 182 /* buffer size */ 183 uint32_t buf_size; 184 /* first block size */ 185 uint32_t first_block_size; 186 /* reserved */ 187 uint32_t flags; 188 /* network handle */ 189 uint32_t network_hdl; 190 /* priority */ 191 uint32_t priority; 192 /* perf mode */ 193 uint32_t perf_mode; 194 }; 195 196 struct msm_npu_load_network_ioctl_v2 { 197 /* physical address */ 198 uint64_t buf_phys_addr; 199 /* patch info(v2) for all input/output layers */ 200 uint64_t patch_info; 201 /* buffer ion handle */ 202 int32_t buf_ion_hdl; 203 /* buffer size */ 204 uint32_t buf_size; 205 /* first block size */ 206 uint32_t first_block_size; 207 /* load flags */ 208 uint32_t flags; 209 /* network handle */ 210 uint32_t network_hdl; 211 /* priority */ 212 uint32_t priority; 213 /* perf mode */ 214 uint32_t perf_mode; 215 /* number of layers in the network */ 216 uint32_t num_layers; 217 /* number of layers to be patched */ 218 uint32_t patch_info_num; 219 /* reserved */ 220 uint32_t reserved; 221 }; 222 223 struct msm_npu_unload_network_ioctl { 224 /* network handle */ 225 uint32_t network_hdl; 226 }; 227 228 struct msm_npu_exec_network_ioctl { 229 /* network handle */ 230 uint32_t network_hdl; 231 /* input layer number */ 232 uint32_t input_layer_num; 233 /* input layer info */ 234 struct msm_npu_layer input_layers[MSM_NPU_MAX_INPUT_LAYER_NUM]; 235 /* output layer number */ 236 uint32_t output_layer_num; 237 /* output layer info */ 238 struct msm_npu_layer output_layers[MSM_NPU_MAX_OUTPUT_LAYER_NUM]; 239 /* patching is required */ 240 uint32_t patching_required; 241 /* asynchronous execution */ 242 uint32_t async; 243 /* reserved */ 244 uint32_t flags; 245 }; 246 247 struct msm_npu_exec_network_ioctl_v2 { 248 /* stats buffer to be filled with execution stats */ 249 uint64_t stats_buf_addr; 250 /* patch buf info for both input and output layers */ 251 uint64_t patch_buf_info; 252 /* network handle */ 253 uint32_t network_hdl; 254 /* asynchronous execution */ 255 uint32_t async; 256 /* execution flags */ 257 uint32_t flags; 258 /* stats buf size allocated */ 259 uint32_t stats_buf_size; 260 /* number of layers to be patched */ 261 uint32_t patch_buf_info_num; 262 /* reserved */ 263 uint32_t reserved; 264 }; 265 266 struct msm_npu_event_execute_done { 267 uint32_t network_hdl; 268 int32_t exec_result; 269 }; 270 271 struct msm_npu_event_execute_v2_done { 272 uint32_t network_hdl; 273 int32_t exec_result; 274 /* stats buf size filled */ 275 uint32_t stats_buf_size; 276 }; 277 278 struct msm_npu_event_ssr { 279 uint32_t network_hdl; 280 }; 281 282 struct msm_npu_event { 283 uint32_t type; 284 union { 285 struct msm_npu_event_execute_done exec_done; 286 struct msm_npu_event_execute_v2_done exec_v2_done; 287 struct msm_npu_event_ssr ssr; 288 uint8_t data[128]; 289 } u; 290 uint32_t reserved[4]; 291 }; 292 293 struct msm_npu_property { 294 uint32_t prop_id; 295 uint32_t num_of_params; 296 uint32_t network_hdl; 297 uint32_t prop_param[PROP_PARAM_MAX_SIZE]; 298 }; 299 300 #endif /* _MSM_NPU_H_*/ 301