1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __MSM_DRM_H__ 20 #define __MSM_DRM_H__ 21 #include "drm.h" 22 #include "sde_drm.h" 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 #define MSM_PIPE_NONE 0x00 27 #define MSM_PIPE_2D0 0x01 28 #define MSM_PIPE_2D1 0x02 29 #define MSM_PIPE_3D0 0x10 30 #define MSM_PIPE_ID_MASK 0xffff 31 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 32 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 33 struct drm_msm_timespec { 34 __s64 tv_sec; 35 __s64 tv_nsec; 36 }; 37 #define HDR_PRIMARIES_COUNT 3 38 #define HDR_EOTF_SDR_LUM_RANGE 0x0 39 #define HDR_EOTF_HDR_LUM_RANGE 0x1 40 #define HDR_EOTF_SMTPE_ST2084 0x2 41 #define HDR_EOTF_HLG 0x3 42 #define DRM_MSM_EXT_HDR_METADATA 43 struct drm_msm_ext_hdr_metadata { 44 __u32 hdr_state; 45 __u32 eotf; 46 __u32 hdr_supported; 47 __u32 display_primaries_x[HDR_PRIMARIES_COUNT]; 48 __u32 display_primaries_y[HDR_PRIMARIES_COUNT]; 49 __u32 white_point_x; 50 __u32 white_point_y; 51 __u32 max_luminance; 52 __u32 min_luminance; 53 __u32 max_content_light_level; 54 __u32 max_average_light_level; 55 }; 56 #define DRM_MSM_EXT_HDR_PROPERTIES 57 struct drm_msm_ext_hdr_properties { 58 __u8 hdr_metadata_type_one; 59 __u32 hdr_supported; 60 __u32 hdr_eotf; 61 __u32 hdr_max_luminance; 62 __u32 hdr_avg_luminance; 63 __u32 hdr_min_luminance; 64 }; 65 #define MSM_PARAM_GPU_ID 0x01 66 #define MSM_PARAM_GMEM_SIZE 0x02 67 #define MSM_PARAM_CHIP_ID 0x03 68 #define MSM_PARAM_MAX_FREQ 0x04 69 #define MSM_PARAM_TIMESTAMP 0x05 70 #define MSM_PARAM_GMEM_BASE 0x06 71 struct drm_msm_param { 72 __u32 pipe; 73 __u32 param; 74 __u64 value; 75 }; 76 #define MSM_BO_SCANOUT 0x00000001 77 #define MSM_BO_GPU_READONLY 0x00000002 78 #define MSM_BO_CACHE_MASK 0x000f0000 79 #define MSM_BO_CACHED 0x00010000 80 #define MSM_BO_WC 0x00020000 81 #define MSM_BO_UNCACHED 0x00040000 82 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHED | MSM_BO_WC | MSM_BO_UNCACHED) 83 struct drm_msm_gem_new { 84 __u64 size; 85 __u32 flags; 86 __u32 handle; 87 }; 88 #define MSM_INFO_IOVA 0x01 89 #define MSM_INFO_FLAGS (MSM_INFO_IOVA) 90 struct drm_msm_gem_info { 91 __u32 handle; 92 __u32 flags; 93 __u64 offset; 94 }; 95 #define MSM_PREP_READ 0x01 96 #define MSM_PREP_WRITE 0x02 97 #define MSM_PREP_NOSYNC 0x04 98 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) 99 struct drm_msm_gem_cpu_prep { 100 __u32 handle; 101 __u32 op; 102 struct drm_msm_timespec timeout; 103 }; 104 struct drm_msm_gem_cpu_fini { 105 __u32 handle; 106 }; 107 struct drm_msm_gem_submit_reloc { 108 __u32 submit_offset; 109 #ifdef __cplusplus 110 __u32 or_val; 111 #else 112 __u32 or; 113 #endif 114 __s32 shift; 115 __u32 reloc_idx; 116 __u64 reloc_offset; 117 }; 118 #define MSM_SUBMIT_CMD_BUF 0x0001 119 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 120 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 121 struct drm_msm_gem_submit_cmd { 122 __u32 type; 123 __u32 submit_idx; 124 __u32 submit_offset; 125 __u32 size; 126 __u32 pad; 127 __u32 nr_relocs; 128 __u64 relocs; 129 }; 130 #define MSM_SUBMIT_BO_READ 0x0001 131 #define MSM_SUBMIT_BO_WRITE 0x0002 132 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE) 133 struct drm_msm_gem_submit_bo { 134 __u32 flags; 135 __u32 handle; 136 __u64 presumed; 137 }; 138 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 139 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 140 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 141 #define MSM_SUBMIT_FLAGS (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | 0) 142 struct drm_msm_gem_submit { 143 __u32 flags; 144 __u32 fence; 145 __u32 nr_bos; 146 __u32 nr_cmds; 147 __u64 bos; 148 __u64 cmds; 149 __s32 fence_fd; 150 }; 151 struct drm_msm_wait_fence { 152 __u32 fence; 153 __u32 pad; 154 struct drm_msm_timespec timeout; 155 }; 156 #define MSM_MADV_WILLNEED 0 157 #define MSM_MADV_DONTNEED 1 158 #define __MSM_MADV_PURGED 2 159 struct drm_msm_gem_madvise { 160 __u32 handle; 161 __u32 madv; 162 __u32 retained; 163 }; 164 #define DISPLAY_PRIMARIES_WX 0 165 #define DISPLAY_PRIMARIES_WY 1 166 #define DISPLAY_PRIMARIES_RX 2 167 #define DISPLAY_PRIMARIES_RY 3 168 #define DISPLAY_PRIMARIES_GX 4 169 #define DISPLAY_PRIMARIES_GY 5 170 #define DISPLAY_PRIMARIES_BX 6 171 #define DISPLAY_PRIMARIES_BY 7 172 #define DISPLAY_PRIMARIES_MAX 8 173 struct drm_panel_hdr_properties { 174 __u32 hdr_enabled; 175 __u32 display_primaries[DISPLAY_PRIMARIES_MAX]; 176 __u32 peak_brightness; 177 __u32 blackness_level; 178 }; 179 struct drm_msm_event_req { 180 __u32 object_id; 181 __u32 object_type; 182 __u32 event; 183 __u64 client_context; 184 __u32 index; 185 }; 186 struct drm_msm_event_resp { 187 struct drm_event base; 188 struct drm_msm_event_req info; 189 __u8 data[]; 190 }; 191 struct drm_msm_power_ctrl { 192 __u32 enable; 193 __u32 flags; 194 }; 195 #define DRM_MSM_GET_PARAM 0x00 196 #define DRM_MSM_GEM_NEW 0x02 197 #define DRM_MSM_GEM_INFO 0x03 198 #define DRM_MSM_GEM_CPU_PREP 0x04 199 #define DRM_MSM_GEM_CPU_FINI 0x05 200 #define DRM_MSM_GEM_SUBMIT 0x06 201 #define DRM_MSM_WAIT_FENCE 0x07 202 #define DRM_MSM_GEM_MADVISE 0x08 203 #define DRM_SDE_WB_CONFIG 0x40 204 #define DRM_MSM_REGISTER_EVENT 0x41 205 #define DRM_MSM_DEREGISTER_EVENT 0x42 206 #define DRM_MSM_RMFB2 0x43 207 #define DRM_MSM_POWER_CTRL 0x44 208 #define DRM_EVENT_HISTOGRAM 0x80000000 209 #define DRM_EVENT_AD_BACKLIGHT 0x80000001 210 #define DRM_EVENT_CRTC_POWER 0x80000002 211 #define DRM_EVENT_SYS_BACKLIGHT 0x80000003 212 #define DRM_EVENT_SDE_POWER 0x80000004 213 #define DRM_EVENT_IDLE_NOTIFY 0x80000005 214 #define DRM_EVENT_PANEL_DEAD 0x80000006 215 #define DRM_EVENT_SDE_HW_RECOVERY 0X80000007 216 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 217 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 218 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 219 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 220 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 221 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 222 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 223 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 224 #define DRM_IOCTL_SDE_WB_CONFIG DRM_IOW((DRM_COMMAND_BASE + DRM_SDE_WB_CONFIG), struct sde_drm_wb_cfg) 225 #define DRM_IOCTL_MSM_REGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_REGISTER_EVENT), struct drm_msm_event_req) 226 #define DRM_IOCTL_MSM_DEREGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_DEREGISTER_EVENT), struct drm_msm_event_req) 227 #define DRM_IOCTL_MSM_RMFB2 DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_RMFB2), unsigned int) 228 #define DRM_IOCTL_MSM_POWER_CTRL DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_POWER_CTRL), struct drm_msm_power_ctrl) 229 #ifdef __cplusplus 230 } 231 #endif 232 #endif 233