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1 #ifndef _H_MSM_VPU_H_
2 #define _H_MSM_VPU_H_
3 
4 #include <linux/videodev2.h>
5 
6 /*
7  * V 4 L 2   E X T E N S I O N S   B Y   V P U
8  */
9 
10 /*
11  * v4l2_buffer:
12  *
13  * VPU uses standard V4L2 buffer flags, and defines some custom
14  * flags (used in v4l2_buffer.flags field):
15  *	V4L2_QCOM_BUF_FLAG_EOS: buffer flag indicating end of stream
16  *	V4L2_BUF_FLAG_CDS_ENABLE: buffer flag to enable chroma down-sampling
17  */
18 #define V4L2_BUF_FLAG_CDS_ENABLE	0x10000000
19 
20 /*
21  * VPU uses multi-plane v4l2_buffer in the following manner:
22  * each plane can be a separate ION buffer, or all planes are from the
23  * same ION buffer (under this case all planes have the same fd, but different
24  * offset).
25  *
26  * For struct v4l2_plane
27  *   fd: ION fd representing the ION buffer this plane is from
28  *   reserved[0]: offset of this plane from the start of the ION buffer in
29  *		bytes. Needed when all planes are from the same ION buffer.
30  */
31 #define V4L2_PLANE_MEM_OFFSET		0
32 
33 /*
34  * struct v4l2_format:
35  * always use v4l2_pix_format_mplane, even when there is only one plane
36  *
37  * v4l2_pix_format_mplane:
38  *
39  * VPU uses v4l2_pix_format_mplane for pixel format configuration
40  * The following members of this structure is either extended or changed:
41  *    pixelformat: extended, a few more private formats added
42  *    colorspace:  possible values are enum vpu_colorspace
43  *    field: when it is V4L2_FIELD_ALTERNATE, flags from vpu format extension
44  *           specifies which field first.
45  *    reserved[]:  VPU format extension. struct v4l2_format_vpu_extension
46  */
47 enum vpu_colorspace {
48 	VPU_CS_MIN = 0,
49 	/* RGB with full range*/
50 	VPU_CS_RGB_FULL = 1,
51 	/* RGB with limited range*/
52 	VPU_CS_RGB_LIMITED = 2,
53 	/* REC 601 with full range */
54 	VPU_CS_REC601_FULL = 3,
55 	/* REC 601 with limited range */
56 	VPU_CS_REC601_LIMITED = 4,
57 	/* REC 709 with full range */
58 	VPU_CS_REC709_FULL = 5,
59 	/* REC 709 with limited range */
60 	VPU_CS_REC709_LIMITED = 6,
61 	/* SMPTE 240 with full range */
62 	VPU_CS_SMPTE240_FULL = 7,
63 	/* SMPTE 240 with limited range */
64 	VPU_CS_SMPTE240_LIMITED = 8,
65 	VPU_CS_MAX = 9,
66 };
67 
68 
69 #define VPU_FMT_EXT_FLAG_BT	1	/* bottom field first */
70 #define VPU_FMT_EXT_FLAG_TB	2	/* top field first */
71 #define VPU_FMT_EXT_FLAG_3D	4	/* 3D format */
72 struct v4l2_format_vpu_extension {
73 	__u8		flag;
74 	__u8		gap_in_lines;
75 };
76 
77 /*
78  * Supported pixel formats:
79  *
80  * VPU supported pixel format fourcc codes (use in s_fmt pixelformat field).
81  *	Can be enumerated using VIDIOC_ENUM_FMT
82  *
83  * Standard V4L2 formats, defined in videodev2.h :
84  *
85  * V4L2_PIX_FMT_RGB24		24 bit RGB-8-8-8
86  * V4L2_PIX_FMT_RGB32		32 bit XRGB-8-8-8-8
87  * V4L2_PIX_FMT_BGR24		24 bit BGR-8-8-8
88  * V4L2_PIX_FMT_BGR32		32 bit BGRX-8-8-8-8
89  *
90  * V4L2_PIX_FMT_NV12		12 bit YUV 4:2:0  semi-planar NV12
91  * V4L2_PIX_FMT_NV21		12 bit YUV 4:2:0  semi-planar NV21
92  * V4L2_PIX_FMT_YUYV		16 bit YUYV 4:2:2 interleaved
93  * V4L2_PIX_FMT_YVYU		16 bit YVYU 4:2:2 interleaved
94  * V4L2_PIX_FMT_UYVY		16 bit UYVY 4:2:2 interleaved
95  * V4L2_PIX_FMT_VYUY		16 bit VYUY 4:2:2 interleaved
96  *
97  *
98  * Private VPU formats, defined here :
99  *
100  * V4L2_PIX_FMT_XRGB2		32 bit XRGB-2-10-10-10
101  * V4L2_PIX_FMT_XBGR2		32 bit XBGR-2-10-10-10
102  *
103  * V4L2_PIX_FMT_YUYV10		24 bit YUYV 4:2:2  10 bit per component loose
104  * V4L2_PIX_FMT_YUV8		24 bit YUV 4:4:4   8 bit per component
105  * V4L2_PIX_FMT_YUV10		32 bit YUV 4:4:4   10 bit per component loose
106  * V4L2_PIX_FMT_YUYV10BWC	10 bit YUYV 4:2:2  compressed, for output only
107  */
108 #define V4L2_PIX_FMT_XRGB2		v4l2_fourcc('X', 'R', 'G', '2')
109 #define V4L2_PIX_FMT_XBGR2		v4l2_fourcc('X', 'B', 'G', '2')
110 #define V4L2_PIX_FMT_YUYV10		v4l2_fourcc('Y', 'U', 'Y', 'L')
111 #define V4L2_PIX_FMT_YUV8		v4l2_fourcc('Y', 'U', 'V', '8')
112 #define V4L2_PIX_FMT_YUV10		v4l2_fourcc('Y', 'U', 'V', 'L')
113 #define V4L2_PIX_FMT_YUYV10BWC		v4l2_fourcc('Y', 'B', 'W', 'C')
114 
115 /*
116  * VIDIOC_S_INPUT/VIDIOC_S_OUTPUT
117  *
118  * The single integer passed by these commands specifies port type in the
119  * lower 16 bits, and pipe bit mask in the higher 16 bits.
120  */
121 /* input / output types */
122 #define VPU_INPUT_TYPE_HOST			0
123 #define VPU_INPUT_TYPE_VCAP			1
124 #define VPU_OUTPUT_TYPE_HOST			0
125 #define VPU_OUTPUT_TYPE_DISPLAY			1
126 
127 /* input / output pipe bit fields */
128 #define VPU_PIPE_VCAP0			(1 << 16)
129 #define VPU_PIPE_VCAP1			(1 << 17)
130 #define VPU_PIPE_DISPLAY0		(1 << 18)
131 #define VPU_PIPE_DISPLAY1		(1 << 19)
132 #define VPU_PIPE_DISPLAY2		(1 << 20)
133 #define VPU_PIPE_DISPLAY3		(1 << 21)
134 
135 /*
136  * V P U   E V E N T S :   I D s   A N D   D A T A   P A Y L O A D S
137  */
138 
139 /*
140  * Event ID: set in type field of struct v4l2_event
141  * payload: returned in u.data array of struct v4l2_event
142  *
143  *
144  * VPU_EVENT_FLUSH_DONE: Done flushing buffers after VPU_FLUSH_BUFS ioctl
145  * payload data: enum v4l2_buf_type (buffer type of flushed port)
146  *
147  * VPU_EVENT_ACTIVE_REGION_CHANGED: New Active Region Detected
148  * payload data: struct v4l2_rect (new active region rectangle)
149  *
150  * VPU_EVENT_SESSION_TIMESTAMP: New Session timestamp
151  * payload data: vpu_frame_timestamp_info
152  *
153  * VPU_EVENT_SESSION_CREATED: New session has been created
154  * payload data: int (number of the attached session)
155  *
156  * VPU_EVENT_SESSION_FREED: Session is detached and free
157  * payload data: int (number of the detached session)
158  *
159  * VPU_EVENT_SESSION_CLIENT_EXITED: Indicates that clients of current
160  *	session have exited.
161  * payload data: int (number of all remaining clients for this session)
162  *
163  * VPU_EVENT_HW_ERROR: a hardware error occurred in VPU
164  * payload data: NULL
165  *
166  * VPU_EVENT_INVALID_CONFIG: invalid VPU session configuration
167  * payload data: NULL
168  *
169  * VPU_EVENT_FAILED_SESSION_STREAMING: Failed to stream session
170  * payload data: NULL
171  */
172 #define VPU_PRIVATE_EVENT_BASE (V4L2_EVENT_PRIVATE_START + 6 * 1000)
173 enum VPU_PRIVATE_EVENT {
174 	VPU_EVENT_START = VPU_PRIVATE_EVENT_BASE,
175 
176 	VPU_EVENT_FLUSH_DONE = VPU_EVENT_START + 1,
177 	VPU_EVENT_ACTIVE_REGION_CHANGED = VPU_EVENT_START + 2,
178 	VPU_EVENT_SESSION_TIMESTAMP = VPU_EVENT_START + 3,
179 	VPU_EVENT_SESSION_CREATED = VPU_EVENT_START + 4,
180 	VPU_EVENT_SESSION_FREED = VPU_EVENT_START + 5,
181 	VPU_EVENT_SESSION_CLIENT_EXITED = VPU_EVENT_START + 6,
182 
183 	VPU_EVENT_HW_ERROR = VPU_EVENT_START + 11,
184 	VPU_EVENT_INVALID_CONFIG = VPU_EVENT_START + 12,
185 	VPU_EVENT_FAILED_SESSION_STREAMING = VPU_EVENT_START + 13,
186 
187 	VPU_EVENT_END
188 };
189 
190 
191 /*
192  * V P U   CO N T R O L S :   S T R U C T S   A N D   I D s
193  *
194  * Controls are video processing parameters
195  */
196 
197 /*
198  * Standard VPU Controls
199  */
200 struct vpu_ctrl_standard {
201 	__u32 enable;		/* boolean: 0=disable, else=enable */
202 	__s32 value;
203 };
204 
205 struct vpu_ctrl_auto_manual {
206 	__u32 enable;		/* boolean: 0=disable, else=enable */
207 	__u32 auto_mode;	/* boolean: 0=manual, else=automatic */
208 	__s32 value;
209 };
210 
211 struct vpu_ctrl_range_mapping {
212 	__u32 enable;		/* boolean: 0=disable, else=enable */
213 	__u32 y_range;		/* the range mapping set for Y [0, 7] */
214 	__u32 uv_range;		/* the range mapping set for UV [0, 7] */
215 };
216 
217 #define VPU_ACTIVE_REGION_N_EXCLUSIONS 1
218 struct vpu_ctrl_active_region_param {
219 	__u32               enable; /* boolean: 0=disable, else=enable */
220 	/* number of exclusion regions */
221 	__u32               num_exclusions;
222 	/* roi where active region detection is applied */
223 	struct v4l2_rect    detection_region;
224 	/* roi(s) excluded from active region detection*/
225 	struct v4l2_rect    excluded_regions[VPU_ACTIVE_REGION_N_EXCLUSIONS];
226 };
227 
228 struct vpu_ctrl_deinterlacing_mode {
229 	__u32 field_polarity;
230 	__u32 mvp_mode;
231 };
232 
233 struct vpu_ctrl_hqv {
234 	__u32 enable;
235 	/* strength control of all sharpening features [0, 100] */
236 	__u32 sharpen_strength;
237 	/* strength control of Auto NR feature [0, 100] */
238 	__u32 auto_nr_strength;
239 };
240 
241 struct vpu_info_frame_timestamp {
242 	/* presentation timestamp of the frame */
243 	__u32 pts_low;
244 	__u32 pts_high;
245 	/* qtimer snapshot */
246 	__u32 qtime_low;
247 	__u32 qtime_high;
248 };
249 
250 struct vpu_control {
251 	__u32 control_id;
252 	union control_data {
253 		__s32 value;
254 		struct vpu_ctrl_standard standard;
255 		struct vpu_ctrl_auto_manual auto_manual;
256 		struct vpu_ctrl_range_mapping range_mapping;
257 		struct vpu_ctrl_active_region_param active_region_param;
258 		struct v4l2_rect active_region_result;
259 		struct vpu_ctrl_deinterlacing_mode deinterlacing_mode;
260 		struct vpu_ctrl_hqv hqv;
261 		struct vpu_info_frame_timestamp timestamp;
262 		__u8 reserved[124];
263 	} data;
264 };
265 
266 /*
267  * IDs for standard controls (use in control_id field of struct vpu_control)
268  *
269  * VPU_CTRL_NOISE_REDUCTION: noise reduction level, data: auto_manual,
270  * value: [0, 100] (step in increments of 25).
271  *
272  * VPU_CTRL_IMAGE_ENHANCEMENT: image enhancement level, data: auto_manual,
273  * value: [-100, 100] (step in increments of 1).
274  *
275  * VPU_CTRL_ANAMORPHIC_SCALING: anamorphic scaling config, data: standard,
276  * value: [0, 100] (step in increments of 1).
277  *
278  * VPU_CTRL_DIRECTIONAL_INTERPOLATION: directional interpolation config
279  * data: standard, value: [0, 100] (step in increments of 1).
280  *
281  * VPU_CTRL_BACKGROUND_COLOR: , data: value,
282  * value: red[0:7] green[8:15] blue[16:23] alpha[24:31]
283  *
284  * VPU_CTRL_RANGE_MAPPING: Y/UV range mapping, data: range_mapping,
285  * y_range: [0, 7], uv_range: [0, 7] (step in increments of 1).
286  *
287  * VPU_CTRL_DEINTERLACING_MODE: deinterlacing mode, data: deinterlacing_mode,
288  * field_polarity: [0, 2], mvp_mode: [0, 2] (step in increments of 1).
289  *
290  * VPU_CTRL_ACTIVE_REGION_PARAM: active region detection parameters (set only)
291  * data: active_region_param,
292  *
293  * VPU_CTRL_ACTIVE_REGION_RESULT: detected active region roi (get only)
294  * data: active_region_result
295  *
296  * VPU_CTRL_PRIORITY: Session priority, data: value,
297  * value: high 100, normal 50
298  *
299  * VPU_CTRL_CONTENT_PROTECTION: input content protection status, data: value,
300  * value: secure 1, non-secure 0
301  *
302  * VPU_CTRL_DISPLAY_REFRESH_RATE: display refresh rate (set only)
303  * data: value (set to __u32 16.16 format)
304  *
305  * VPU_CTRL_HQV: hqv block config, data: hqv,
306  * sharpen_strength: [0, 100] (step in increments of 25),
307  * auto_nr_strength: [0, 100] (step in increments of 1).
308  *
309  * VPU_CTRL_HQV_SHARPEN: , data: value,
310  * sharpen_strength: [0, 100] (step in increments of 1).
311  *
312  * VPU_CTRL_HQV_AUTONR: , data: value,
313  * auto_nr_strength: [0, 100] (step in increments of 1).
314  *
315  * VPU_CTRL_ACE: , data: value
316  *
317  * VPU_CTRL_ACE_BRIGHTNESS: , data: value,
318  * value: [-100, 100] (step in increments of 1).
319  *
320  * VPU_CTRL_ACE_CONTRAST: , data: value,
321  * value: [-100, 100] (step in increments of 1).
322  *
323  * VPU_CTRL_2D3D: , data: value,
324  * value: 1 enabled, 0 disabled
325  *
326  * VPU_CTRL_2D3D_DEPTH: , data: value,
327  * value: [0, 100] (step in increments of 1).
328  *
329  * VPU_CTRL_TIMESTAMP_INFO_MODE: timestamp reporting mode,
330  *  data: value specifying how frequent a timestamp reporting info, value
331  *  is in frames
332  *
333  * VPU_INFO_TIMESTAMP: timestamp information (get only)
334  *  data: struct vpu_frame_timestamp_info
335  *
336  * VPU_CTRL_FRC: enable/disable FRC, data: value,
337  * value: 1 enable, 0 disable
338  *
339  * VPU_CTRL_FRC_MOTION_SMOOTHNESS: , data: value,
340  * value: [0, 100] (step in increments of 1).
341  *
342  * VPU_CTRL_FRC_MOTION_CLEAR: , data: value,
343  * value: [0, 100] (step in increments of 1).
344  *
345  * VPU_CTRL_LATENCY: session latency, data: value in us
346  *
347  * VPU_CTRL_LATENCY_MODE: data: value (ultra low, low, etc.)
348  *
349  * VPU_INFO_STATISTICS: frames dropped, etc (get only),
350  *  data: reserved
351  */
352 #define VPU_CTRL_ID_MIN						0
353 
354 #define VPU_CTRL_NOISE_REDUCTION				1
355 #define VPU_CTRL_IMAGE_ENHANCEMENT				2
356 #define VPU_CTRL_ANAMORPHIC_SCALING				3
357 #define VPU_CTRL_DIRECTIONAL_INTERPOLATION			4
358 #define VPU_CTRL_BACKGROUND_COLOR				5
359 #define VPU_CTRL_RANGE_MAPPING					6
360 #define VPU_CTRL_DEINTERLACING_MODE				7
361 #define VPU_CTRL_ACTIVE_REGION_PARAM				8
362 #define VPU_CTRL_ACTIVE_REGION_RESULT				9
363 #define VPU_CTRL_PRIORITY					10
364 #define VPU_CTRL_CONTENT_PROTECTION				11
365 #define VPU_CTRL_DISPLAY_REFRESH_RATE				12
366 
367 #define VPU_CTRL_HQV						20
368 #define VPU_CTRL_HQV_SHARPEN					21
369 #define VPU_CTRL_HQV_AUTONR					22
370 #define VPU_CTRL_ACE						23
371 #define VPU_CTRL_ACE_BRIGHTNESS					24
372 #define VPU_CTRL_ACE_CONTRAST					25
373 #define VPU_CTRL_2D3D						26
374 #define VPU_CTRL_2D3D_DEPTH					27
375 #define VPU_CTRL_FRC						28
376 #define VPU_CTRL_FRC_MOTION_SMOOTHNESS				29
377 #define VPU_CTRL_FRC_MOTION_CLEAR				30
378 
379 #define VPU_INFO_TIMESTAMP					35
380 #define VPU_CTRL_TIMESTAMP_INFO_MODE				36
381 #define VPU_INFO_STATISTICS					37
382 #define VPU_CTRL_LATENCY					38
383 #define VPU_CTRL_LATENCY_MODE					39
384 
385 #define VPU_CTRL_ID_MAX						40
386 
387 
388 /*
389  * Extended VPU Controls (large data payloads)
390  */
391 #define VPU_MAX_EXT_DATA_SIZE	720
392 struct vpu_control_extended {
393 	/*
394 	 * extended control type
395 	 * 0: system
396 	 * 1: session
397 	 */
398 	__u32 type;
399 
400 	/*
401 	 * size and ptr of the data to send
402 	 * maximum VPU_MAX_EXT_DATA_SIZE bytes
403 	 */
404 	__u32 data_len;
405 	void *data_ptr;
406 
407 	/*
408 	 * size and ptr of the buffer to recv data
409 	 * maximum VPU_MAX_EXT_DATA_SIZE bytes
410 	 */
411 	__u32 buf_size;
412 	void *buf_ptr;
413 };
414 
415 /*
416  * Port specific controls
417  */
418 struct vpu_control_port {
419 	__u32 control_id;
420 	__u32 port;	/* 0: INPUT, 1: OUTPUT */
421 	union control_port_data {
422 		__u32 framerate;
423 	} data;
424 };
425 
426 /*
427  * IDs for port controls (use in control_id field of struct vpu_control_port)
428  *
429  * VPU_CTRL_FPS: set frame rate, data: __u32, 16.16 format
430  */
431 #define	VPU_CTRL_FPS				1000
432 
433 
434 /*
435  * V P U   D E V I C E   P R I V A T E   I O C T L   C O D E S
436  */
437 
438 /* VPU Session ioctls (deprecated) */
439 #define VPU_ATTACH_TO_SESSION	_IOW('V', (BASE_VIDIOC_PRIVATE + 1), int)
440 
441 /* VPU Session ioctls */
442 #define VPU_QUERY_SESSIONS	_IOR('V', (BASE_VIDIOC_PRIVATE + 0), int)
443 #define VPU_CREATE_SESSION	_IOR('V', (BASE_VIDIOC_PRIVATE + 2), int)
444 #define VPU_JOIN_SESSION	_IOW('V', (BASE_VIDIOC_PRIVATE + 3), int)
445 
446 /* Enable second VPU output port and use with current client */
447 #define VPU_CREATE_OUTPUT2	_IO('V', (BASE_VIDIOC_PRIVATE + 5))
448 
449 /* Explicit commit of session configuration */
450 #define VPU_COMMIT_CONFIGURATION    _IO('V', (BASE_VIDIOC_PRIVATE + 10))
451 
452 /* Flush all buffers of given type (port) */
453 #define VPU_FLUSH_BUFS		_IOW('V', (BASE_VIDIOC_PRIVATE + 15), \
454 		enum v4l2_buf_type)
455 
456 /* VPU controls get/set ioctls (for most controls with small data) */
457 #define VPU_G_CONTROL		_IOWR('V', (BASE_VIDIOC_PRIVATE + 20), \
458 						struct vpu_control)
459 #define VPU_S_CONTROL		_IOW('V', (BASE_VIDIOC_PRIVATE + 21), \
460 						struct vpu_control)
461 
462 /* extended control set/get ioctls (large data payloads) */
463 #define VPU_G_CONTROL_EXTENDED	_IOWR('V', (BASE_VIDIOC_PRIVATE + 22), \
464 		struct vpu_control_extended)
465 #define VPU_S_CONTROL_EXTENDED	_IOW('V', (BASE_VIDIOC_PRIVATE + 23), \
466 		struct vpu_control_extended)
467 
468 /* VPU port (input/output) specific controls get/set ioctls */
469 #define VPU_G_CONTROL_PORT	_IOWR('V', (BASE_VIDIOC_PRIVATE + 24), \
470 						struct vpu_control_port)
471 #define VPU_S_CONTROL_PORT	_IOW('V', (BASE_VIDIOC_PRIVATE + 25), \
472 						struct vpu_control_port)
473 
474 #endif /* _H_MSM_VPU_H_ */
475 
476