1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _MSM_MDP_H_ 20 #define _MSM_MDP_H_ 21 #include <stdint.h> 22 #include <linux/fb.h> 23 #define MSMFB_IOCTL_MAGIC 'm' 24 #define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 25 #define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 26 #define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 27 #define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 28 #define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 29 #define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 30 #define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 31 #define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 32 #define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 33 #define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, struct mdp_overlay) 34 #define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 35 #define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, struct msmfb_overlay_data) 36 #define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 37 #define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, struct mdp_page_protection) 38 #define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, struct mdp_page_protection) 39 #define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, struct mdp_overlay) 40 #define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 41 #define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, struct msmfb_overlay_blt) 42 #define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 43 #define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, struct mdp_histogram_start_req) 44 #define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 45 #define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 46 #define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, struct msmfb_overlay_3d) 47 #define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, struct msmfb_mixer_info_req) 48 #define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, struct msmfb_overlay_data) 49 #define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 50 #define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 51 #define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 52 #define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, struct msmfb_data) 53 #define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, struct msmfb_data) 54 #define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 55 #define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 56 #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 57 #define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 58 #define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 59 #define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 60 #define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, struct mdp_display_commit) 61 #define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 62 #define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 63 #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, unsigned int) 64 #define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 65 #define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, struct mdp_overlay_list) 66 #define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) 67 #define MSMFB_MDP_PP_GET_FEATURE_VERSION _IOWR(MSMFB_IOCTL_MAGIC, 171, struct mdp_pp_feature_version) 68 #define FB_TYPE_3D_PANEL 0x10101010 69 #define MDP_IMGTYPE2_START 0x10000 70 #define MSMFB_DRIVER_VERSION 0xF9E8D701 71 #define MDP_IMGTYPE_END 0x100 72 #define MDSS_GET_MAJOR(rev) ((rev) >> 28) 73 #define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) 74 #define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) 75 #define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) 76 #define IS_MDSS_MAJOR_MINOR_SAME(rev1,rev2) (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) 77 #define MDSS_MDP_REV(major,minor,step) ((((major) & 0x000F) << 28) | (((minor) & 0x0FFF) << 16) | ((step) & 0xFFFF)) 78 #define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) 79 #define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) 80 #define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) 81 #define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) 82 #define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) 83 #define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) 84 #define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) 85 #define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) 86 #define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) 87 #define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) 88 #define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) 89 #define MDSS_MDP_HW_REV_107_1 MDSS_MDP_REV(1, 7, 1) 90 #define MDSS_MDP_HW_REV_107_2 MDSS_MDP_REV(1, 7, 2) 91 #define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) 92 #define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) 93 #define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) 94 #define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) 95 #define MDSS_MDP_HW_REV_112 MDSS_MDP_REV(1, 12, 0) 96 #define MDSS_MDP_HW_REV_114 MDSS_MDP_REV(1, 14, 0) 97 #define MDSS_MDP_HW_REV_115 MDSS_MDP_REV(1, 15, 0) 98 #define MDSS_MDP_HW_REV_116 MDSS_MDP_REV(1, 16, 0) 99 #define MDSS_MDP_HW_REV_117 MDSS_MDP_REV(1, 17, 0) 100 #define MDSS_MDP_HW_REV_300 MDSS_MDP_REV(3, 0, 0) 101 #define MDSS_MDP_HW_REV_301 MDSS_MDP_REV(3, 0, 1) 102 enum { 103 NOTIFY_UPDATE_INIT, 104 NOTIFY_UPDATE_DEINIT, 105 NOTIFY_UPDATE_START, 106 NOTIFY_UPDATE_STOP, 107 NOTIFY_UPDATE_POWER_OFF, 108 }; 109 enum { 110 NOTIFY_TYPE_NO_UPDATE, 111 NOTIFY_TYPE_SUSPEND, 112 NOTIFY_TYPE_UPDATE, 113 NOTIFY_TYPE_BL_UPDATE, 114 NOTIFY_TYPE_BL_AD_ATTEN_UPDATE, 115 }; 116 enum { 117 MDP_RGB_565, 118 MDP_XRGB_8888, 119 MDP_Y_CBCR_H2V2, 120 MDP_Y_CBCR_H2V2_ADRENO, 121 MDP_ARGB_8888, 122 MDP_RGB_888, 123 MDP_Y_CRCB_H2V2, 124 MDP_YCRYCB_H2V1, 125 MDP_CBYCRY_H2V1, 126 MDP_Y_CRCB_H2V1, 127 MDP_Y_CBCR_H2V1, 128 MDP_Y_CRCB_H1V2, 129 MDP_Y_CBCR_H1V2, 130 MDP_RGBA_8888, 131 MDP_BGRA_8888, 132 MDP_RGBX_8888, 133 MDP_Y_CRCB_H2V2_TILE, 134 MDP_Y_CBCR_H2V2_TILE, 135 MDP_Y_CR_CB_H2V2, 136 MDP_Y_CR_CB_GH2V2, 137 MDP_Y_CB_CR_H2V2, 138 MDP_Y_CRCB_H1V1, 139 MDP_Y_CBCR_H1V1, 140 MDP_YCRCB_H1V1, 141 MDP_YCBCR_H1V1, 142 MDP_BGR_565, 143 MDP_BGR_888, 144 MDP_Y_CBCR_H2V2_VENUS, 145 MDP_BGRX_8888, 146 MDP_RGBA_8888_TILE, 147 MDP_ARGB_8888_TILE, 148 MDP_ABGR_8888_TILE, 149 MDP_BGRA_8888_TILE, 150 MDP_RGBX_8888_TILE, 151 MDP_XRGB_8888_TILE, 152 MDP_XBGR_8888_TILE, 153 MDP_BGRX_8888_TILE, 154 MDP_YCBYCR_H2V1, 155 MDP_RGB_565_TILE, 156 MDP_BGR_565_TILE, 157 MDP_ARGB_1555, 158 MDP_RGBA_5551, 159 MDP_ARGB_4444, 160 MDP_RGBA_4444, 161 MDP_RGB_565_UBWC, 162 MDP_RGBA_8888_UBWC, 163 MDP_Y_CBCR_H2V2_UBWC, 164 MDP_RGBX_8888_UBWC, 165 MDP_Y_CRCB_H2V2_VENUS, 166 MDP_IMGTYPE_LIMIT, 167 MDP_RGB_BORDERFILL, 168 MDP_XRGB_1555, 169 MDP_RGBX_5551, 170 MDP_XRGB_4444, 171 MDP_RGBX_4444, 172 MDP_ABGR_1555, 173 MDP_BGRA_5551, 174 MDP_XBGR_1555, 175 MDP_BGRX_5551, 176 MDP_ABGR_4444, 177 MDP_BGRA_4444, 178 MDP_XBGR_4444, 179 MDP_BGRX_4444, 180 MDP_ABGR_8888, 181 MDP_XBGR_8888, 182 MDP_RGBA_1010102, 183 MDP_ARGB_2101010, 184 MDP_RGBX_1010102, 185 MDP_XRGB_2101010, 186 MDP_BGRA_1010102, 187 MDP_ABGR_2101010, 188 MDP_BGRX_1010102, 189 MDP_XBGR_2101010, 190 MDP_RGBA_1010102_UBWC, 191 MDP_RGBX_1010102_UBWC, 192 MDP_Y_CBCR_H2V2_P010, 193 MDP_Y_CBCR_H2V2_TP10_UBWC, 194 MDP_CRYCBY_H2V1, 195 MDP_IMGTYPE_LIMIT1 = MDP_IMGTYPE_END, 196 MDP_FB_FORMAT = MDP_IMGTYPE2_START, 197 MDP_IMGTYPE_LIMIT2 198 }; 199 #define MDP_CRYCBY_H2V1 MDP_CRYCBY_H2V1 200 enum { 201 PMEM_IMG, 202 FB_IMG, 203 }; 204 enum { 205 HSIC_HUE = 0, 206 HSIC_SAT, 207 HSIC_INT, 208 HSIC_CON, 209 NUM_HSIC_PARAM, 210 }; 211 enum mdss_mdp_max_bw_mode { 212 MDSS_MAX_BW_LIMIT_DEFAULT = 0x1, 213 MDSS_MAX_BW_LIMIT_CAMERA = 0x2, 214 MDSS_MAX_BW_LIMIT_HFLIP = 0x4, 215 MDSS_MAX_BW_LIMIT_VFLIP = 0x8, 216 }; 217 #define MDSS_MDP_ROT_ONLY 0x80 218 #define MDSS_MDP_RIGHT_MIXER 0x100 219 #define MDSS_MDP_DUAL_PIPE 0x200 220 #define MDP_ROT_NOP 0 221 #define MDP_FLIP_LR 0x1 222 #define MDP_FLIP_UD 0x2 223 #define MDP_ROT_90 0x4 224 #define MDP_ROT_180 (MDP_FLIP_UD | MDP_FLIP_LR) 225 #define MDP_ROT_270 (MDP_ROT_90 | MDP_FLIP_UD | MDP_FLIP_LR) 226 #define MDP_DITHER 0x8 227 #define MDP_BLUR 0x10 228 #define MDP_BLEND_FG_PREMULT 0x20000 229 #define MDP_IS_FG 0x40000 230 #define MDP_SOLID_FILL 0x00000020 231 #define MDP_VPU_PIPE 0x00000040 232 #define MDP_DEINTERLACE 0x80000000 233 #define MDP_SHARPENING 0x40000000 234 #define MDP_NO_DMA_BARRIER_START 0x20000000 235 #define MDP_NO_DMA_BARRIER_END 0x10000000 236 #define MDP_NO_BLIT 0x08000000 237 #define MDP_BLIT_WITH_DMA_BARRIERS 0x000 238 #define MDP_BLIT_WITH_NO_DMA_BARRIERS (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 239 #define MDP_BLIT_SRC_GEM 0x04000000 240 #define MDP_BLIT_DST_GEM 0x02000000 241 #define MDP_BLIT_NON_CACHED 0x01000000 242 #define MDP_OV_PIPE_SHARE 0x00800000 243 #define MDP_DEINTERLACE_ODD 0x00400000 244 #define MDP_OV_PLAY_NOWAIT 0x00200000 245 #define MDP_SOURCE_ROTATED_90 0x00100000 246 #define MDP_OVERLAY_PP_CFG_EN 0x00080000 247 #define MDP_BACKEND_COMPOSITION 0x00040000 248 #define MDP_BORDERFILL_SUPPORTED 0x00010000 249 #define MDP_SECURE_OVERLAY_SESSION 0x00008000 250 #define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 251 #define MDP_OV_PIPE_FORCE_DMA 0x00004000 252 #define MDP_MEMORY_ID_TYPE_FB 0x00001000 253 #define MDP_BWC_EN 0x00000400 254 #define MDP_DECIMATION_EN 0x00000800 255 #define MDP_SMP_FORCE_ALLOC 0x00200000 256 #define MDP_TRANSP_NOP 0xffffffff 257 #define MDP_ALPHA_NOP 0xff 258 #define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 259 #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 260 #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 261 #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 262 #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 263 #define MDP_FB_PAGE_PROTECTION_INVALID (5) 264 #define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 265 #define MDP_DEEP_COLOR_YUV444 0x1 266 #define MDP_DEEP_COLOR_RGB30B 0x2 267 #define MDP_DEEP_COLOR_RGB36B 0x4 268 #define MDP_DEEP_COLOR_RGB48B 0x8 269 struct mdp_rect { 270 uint32_t x; 271 uint32_t y; 272 uint32_t w; 273 uint32_t h; 274 }; 275 struct mdp_img { 276 uint32_t width; 277 uint32_t height; 278 uint32_t format; 279 uint32_t offset; 280 int memory_id; 281 uint32_t priv; 282 }; 283 struct mult_factor { 284 uint32_t numer; 285 uint32_t denom; 286 }; 287 #define MDP_CCS_RGB2YUV 0 288 #define MDP_CCS_YUV2RGB 1 289 #define MDP_CCS_SIZE 9 290 #define MDP_BV_SIZE 3 291 struct mdp_ccs { 292 int direction; 293 uint16_t ccs[MDP_CCS_SIZE]; 294 uint16_t bv[MDP_BV_SIZE]; 295 }; 296 struct mdp_csc { 297 int id; 298 uint32_t csc_mv[9]; 299 uint32_t csc_pre_bv[3]; 300 uint32_t csc_post_bv[3]; 301 uint32_t csc_pre_lv[6]; 302 uint32_t csc_post_lv[6]; 303 }; 304 #define MDP_BLIT_REQ_VERSION 3 305 struct color { 306 uint32_t r; 307 uint32_t g; 308 uint32_t b; 309 uint32_t alpha; 310 }; 311 struct mdp_blit_req { 312 struct mdp_img src; 313 struct mdp_img dst; 314 struct mdp_rect src_rect; 315 struct mdp_rect dst_rect; 316 struct color const_color; 317 uint32_t alpha; 318 uint32_t transp_mask; 319 uint32_t flags; 320 int sharpening_strength; 321 uint8_t color_space; 322 uint32_t fps; 323 }; 324 struct mdp_blit_req_list { 325 uint32_t count; 326 struct mdp_blit_req req[]; 327 }; 328 #define MSMFB_DATA_VERSION 2 329 struct msmfb_data { 330 uint32_t offset; 331 int memory_id; 332 int id; 333 uint32_t flags; 334 uint32_t priv; 335 uint32_t iova; 336 }; 337 #define MSMFB_NEW_REQUEST - 1 338 struct msmfb_overlay_data { 339 uint32_t id; 340 struct msmfb_data data; 341 uint32_t version_key; 342 struct msmfb_data plane1_data; 343 struct msmfb_data plane2_data; 344 struct msmfb_data dst_data; 345 }; 346 struct msmfb_img { 347 uint32_t width; 348 uint32_t height; 349 uint32_t format; 350 }; 351 #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 352 struct msmfb_writeback_data { 353 struct msmfb_data buf_info; 354 struct msmfb_img img; 355 }; 356 #define MDP_PP_OPS_ENABLE 0x1 357 #define MDP_PP_OPS_READ 0x2 358 #define MDP_PP_OPS_WRITE 0x4 359 #define MDP_PP_OPS_DISABLE 0x8 360 #define MDP_PP_IGC_FLAG_ROM0 0x10 361 #define MDP_PP_IGC_FLAG_ROM1 0x20 362 #define MDSS_PP_DSPP_CFG 0x000 363 #define MDSS_PP_SSPP_CFG 0x100 364 #define MDSS_PP_LM_CFG 0x200 365 #define MDSS_PP_WB_CFG 0x300 366 #define MDSS_PP_ARG_MASK 0x3C00 367 #define MDSS_PP_ARG_NUM 4 368 #define MDSS_PP_ARG_SHIFT 10 369 #define MDSS_PP_LOCATION_MASK 0x0300 370 #define MDSS_PP_LOGICAL_MASK 0x00FF 371 #define MDSS_PP_ADD_ARG(var,arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 372 #define PP_ARG(x,var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 373 #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 374 #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 375 struct mdp_qseed_cfg { 376 uint32_t table_num; 377 uint32_t ops; 378 uint32_t len; 379 uint32_t * data; 380 }; 381 struct mdp_sharp_cfg { 382 uint32_t flags; 383 uint32_t strength; 384 uint32_t edge_thr; 385 uint32_t smooth_thr; 386 uint32_t noise_thr; 387 }; 388 struct mdp_qseed_cfg_data { 389 uint32_t block; 390 struct mdp_qseed_cfg qseed_data; 391 }; 392 #define MDP_OVERLAY_PP_CSC_CFG 0x1 393 #define MDP_OVERLAY_PP_QSEED_CFG 0x2 394 #define MDP_OVERLAY_PP_PA_CFG 0x4 395 #define MDP_OVERLAY_PP_IGC_CFG 0x8 396 #define MDP_OVERLAY_PP_SHARP_CFG 0x10 397 #define MDP_OVERLAY_PP_HIST_CFG 0x20 398 #define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 399 #define MDP_OVERLAY_PP_PA_V2_CFG 0x80 400 #define MDP_OVERLAY_PP_PCC_CFG 0x100 401 #define MDP_CSC_FLAG_ENABLE 0x1 402 #define MDP_CSC_FLAG_YUV_IN 0x2 403 #define MDP_CSC_FLAG_YUV_OUT 0x4 404 #define MDP_CSC_MATRIX_COEFF_SIZE 9 405 #define MDP_CSC_CLAMP_SIZE 6 406 #define MDP_CSC_BIAS_SIZE 3 407 struct mdp_csc_cfg { 408 uint32_t flags; 409 uint32_t csc_mv[MDP_CSC_MATRIX_COEFF_SIZE]; 410 uint32_t csc_pre_bv[MDP_CSC_BIAS_SIZE]; 411 uint32_t csc_post_bv[MDP_CSC_BIAS_SIZE]; 412 uint32_t csc_pre_lv[MDP_CSC_CLAMP_SIZE]; 413 uint32_t csc_post_lv[MDP_CSC_CLAMP_SIZE]; 414 }; 415 struct mdp_csc_cfg_data { 416 uint32_t block; 417 struct mdp_csc_cfg csc_data; 418 }; 419 struct mdp_pa_cfg { 420 uint32_t flags; 421 uint32_t hue_adj; 422 uint32_t sat_adj; 423 uint32_t val_adj; 424 uint32_t cont_adj; 425 }; 426 struct mdp_pa_mem_col_cfg { 427 uint32_t color_adjust_p0; 428 uint32_t color_adjust_p1; 429 uint32_t hue_region; 430 uint32_t sat_region; 431 uint32_t val_region; 432 }; 433 #define MDP_SIX_ZONE_LUT_SIZE 384 434 #define MDP_PP_PA_HUE_ENABLE 0x10 435 #define MDP_PP_PA_SAT_ENABLE 0x20 436 #define MDP_PP_PA_VAL_ENABLE 0x40 437 #define MDP_PP_PA_CONT_ENABLE 0x80 438 #define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 439 #define MDP_PP_PA_SKIN_ENABLE 0x200 440 #define MDP_PP_PA_SKY_ENABLE 0x400 441 #define MDP_PP_PA_FOL_ENABLE 0x800 442 #define MDP_PP_PA_MEM_PROT_HUE_EN 0x1 443 #define MDP_PP_PA_MEM_PROT_SAT_EN 0x2 444 #define MDP_PP_PA_MEM_PROT_VAL_EN 0x4 445 #define MDP_PP_PA_MEM_PROT_CONT_EN 0x8 446 #define MDP_PP_PA_MEM_PROT_SIX_EN 0x10 447 #define MDP_PP_PA_MEM_PROT_BLEND_EN 0x20 448 #define MDP_PP_PA_HUE_MASK 0x1000 449 #define MDP_PP_PA_SAT_MASK 0x2000 450 #define MDP_PP_PA_VAL_MASK 0x4000 451 #define MDP_PP_PA_CONT_MASK 0x8000 452 #define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 453 #define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 454 #define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 455 #define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 456 #define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 457 #define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 458 #define MDP_PP_PA_MEM_PROTECT_EN 0x400000 459 #define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 460 #define MDP_PP_PA_LEFT_HOLD 0x1 461 #define MDP_PP_PA_RIGHT_HOLD 0x2 462 struct mdp_pa_v2_data { 463 uint32_t flags; 464 uint32_t global_hue_adj; 465 uint32_t global_sat_adj; 466 uint32_t global_val_adj; 467 uint32_t global_cont_adj; 468 struct mdp_pa_mem_col_cfg skin_cfg; 469 struct mdp_pa_mem_col_cfg sky_cfg; 470 struct mdp_pa_mem_col_cfg fol_cfg; 471 uint32_t six_zone_len; 472 uint32_t six_zone_thresh; 473 uint32_t * six_zone_curve_p0; 474 uint32_t * six_zone_curve_p1; 475 }; 476 struct mdp_pa_mem_col_data_v1_7 { 477 uint32_t color_adjust_p0; 478 uint32_t color_adjust_p1; 479 uint32_t color_adjust_p2; 480 uint32_t blend_gain; 481 uint8_t sat_hold; 482 uint8_t val_hold; 483 uint32_t hue_region; 484 uint32_t sat_region; 485 uint32_t val_region; 486 }; 487 struct mdp_pa_data_v1_7 { 488 uint32_t mode; 489 uint32_t global_hue_adj; 490 uint32_t global_sat_adj; 491 uint32_t global_val_adj; 492 uint32_t global_cont_adj; 493 struct mdp_pa_mem_col_data_v1_7 skin_cfg; 494 struct mdp_pa_mem_col_data_v1_7 sky_cfg; 495 struct mdp_pa_mem_col_data_v1_7 fol_cfg; 496 uint32_t six_zone_thresh; 497 uint32_t six_zone_adj_p0; 498 uint32_t six_zone_adj_p1; 499 uint8_t six_zone_sat_hold; 500 uint8_t six_zone_val_hold; 501 uint32_t six_zone_len; 502 uint32_t * six_zone_curve_p0; 503 uint32_t * six_zone_curve_p1; 504 }; 505 struct mdp_pa_v2_cfg_data { 506 uint32_t version; 507 uint32_t block; 508 uint32_t flags; 509 struct mdp_pa_v2_data pa_v2_data; 510 void * cfg_payload; 511 }; 512 enum { 513 mdp_igc_rec601 = 1, 514 mdp_igc_rec709, 515 mdp_igc_srgb, 516 mdp_igc_custom, 517 mdp_igc_rec_max, 518 }; 519 struct mdp_igc_lut_data { 520 uint32_t block; 521 uint32_t version; 522 uint32_t len, ops; 523 uint32_t * c0_c1_data; 524 uint32_t * c2_data; 525 void * cfg_payload; 526 }; 527 struct mdp_igc_lut_data_v1_7 { 528 uint32_t table_fmt; 529 uint32_t len; 530 uint32_t * c0_c1_data; 531 uint32_t * c2_data; 532 }; 533 struct mdp_igc_lut_data_payload { 534 uint32_t table_fmt; 535 uint32_t len; 536 uint64_t c0_c1_data; 537 uint64_t c2_data; 538 uint32_t strength; 539 }; 540 struct mdp_histogram_cfg { 541 uint32_t ops; 542 uint32_t block; 543 uint8_t frame_cnt; 544 uint8_t bit_mask; 545 uint16_t num_bins; 546 }; 547 struct mdp_hist_lut_data_v1_7 { 548 uint32_t len; 549 uint32_t * data; 550 }; 551 struct mdp_hist_lut_data { 552 uint32_t block; 553 uint32_t version; 554 uint32_t hist_lut_first; 555 uint32_t ops; 556 uint32_t len; 557 uint32_t * data; 558 void * cfg_payload; 559 }; 560 struct mdp_pcc_coeff { 561 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 562 }; 563 struct mdp_pcc_coeff_v1_7 { 564 uint32_t c, r, g, b, rg, gb, rb, rgb; 565 }; 566 struct mdp_pcc_data_v1_7 { 567 struct mdp_pcc_coeff_v1_7 r, g, b; 568 }; 569 struct mdp_pcc_cfg_data { 570 uint32_t version; 571 uint32_t block; 572 uint32_t ops; 573 struct mdp_pcc_coeff r, g, b; 574 void * cfg_payload; 575 }; 576 enum { 577 mdp_lut_igc, 578 mdp_lut_pgc, 579 mdp_lut_hist, 580 mdp_lut_rgb, 581 mdp_lut_max, 582 }; 583 struct mdp_overlay_pp_params { 584 uint32_t config_ops; 585 struct mdp_csc_cfg csc_cfg; 586 struct mdp_qseed_cfg qseed_cfg[2]; 587 struct mdp_pa_cfg pa_cfg; 588 struct mdp_pa_v2_data pa_v2_cfg; 589 struct mdp_igc_lut_data igc_cfg; 590 struct mdp_sharp_cfg sharp_cfg; 591 struct mdp_histogram_cfg hist_cfg; 592 struct mdp_hist_lut_data hist_lut_cfg; 593 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 594 struct mdp_pcc_cfg_data pcc_cfg_data; 595 }; 596 enum mdss_mdp_blend_op { 597 BLEND_OP_NOT_DEFINED = 0, 598 BLEND_OP_OPAQUE, 599 BLEND_OP_PREMULTIPLIED, 600 BLEND_OP_COVERAGE, 601 BLEND_OP_MAX, 602 }; 603 #define DECIMATED_DIMENSION(dim,deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 604 #define MAX_PLANES 4 605 struct mdp_scale_data { 606 uint8_t enable_pxl_ext; 607 int init_phase_x[MAX_PLANES]; 608 int phase_step_x[MAX_PLANES]; 609 int init_phase_y[MAX_PLANES]; 610 int phase_step_y[MAX_PLANES]; 611 int num_ext_pxls_left[MAX_PLANES]; 612 int num_ext_pxls_right[MAX_PLANES]; 613 int num_ext_pxls_top[MAX_PLANES]; 614 int num_ext_pxls_btm[MAX_PLANES]; 615 int left_ftch[MAX_PLANES]; 616 int left_rpt[MAX_PLANES]; 617 int right_ftch[MAX_PLANES]; 618 int right_rpt[MAX_PLANES]; 619 int top_rpt[MAX_PLANES]; 620 int btm_rpt[MAX_PLANES]; 621 int top_ftch[MAX_PLANES]; 622 int btm_ftch[MAX_PLANES]; 623 uint32_t roi_w[MAX_PLANES]; 624 }; 625 enum mdp_overlay_pipe_type { 626 PIPE_TYPE_AUTO = 0, 627 PIPE_TYPE_VIG, 628 PIPE_TYPE_RGB, 629 PIPE_TYPE_DMA, 630 PIPE_TYPE_CURSOR, 631 PIPE_TYPE_MAX, 632 }; 633 struct mdp_overlay { 634 struct msmfb_img src; 635 struct mdp_rect src_rect; 636 struct mdp_rect dst_rect; 637 uint32_t z_order; 638 uint32_t is_fg; 639 uint32_t alpha; 640 uint32_t blend_op; 641 uint32_t transp_mask; 642 uint32_t flags; 643 uint32_t pipe_type; 644 uint32_t id; 645 uint8_t priority; 646 uint32_t user_data[6]; 647 uint32_t bg_color; 648 uint8_t horz_deci; 649 uint8_t vert_deci; 650 struct mdp_overlay_pp_params overlay_pp_cfg; 651 struct mdp_scale_data scale; 652 uint8_t color_space; 653 uint32_t frame_rate; 654 }; 655 struct msmfb_overlay_3d { 656 uint32_t is_3d; 657 uint32_t width; 658 uint32_t height; 659 }; 660 struct msmfb_overlay_blt { 661 uint32_t enable; 662 uint32_t offset; 663 uint32_t width; 664 uint32_t height; 665 uint32_t bpp; 666 }; 667 struct mdp_histogram { 668 uint32_t frame_cnt; 669 uint32_t bin_cnt; 670 uint32_t * r; 671 uint32_t * g; 672 uint32_t * b; 673 }; 674 #define MISR_CRC_BATCH_SIZE 32 675 enum { 676 DISPLAY_MISR_EDP, 677 DISPLAY_MISR_DSI0, 678 DISPLAY_MISR_DSI1, 679 DISPLAY_MISR_HDMI, 680 DISPLAY_MISR_LCDC, 681 DISPLAY_MISR_MDP, 682 DISPLAY_MISR_ATV, 683 DISPLAY_MISR_DSI_CMD, 684 DISPLAY_MISR_MAX 685 }; 686 enum { 687 MISR_OP_NONE, 688 MISR_OP_SFM, 689 MISR_OP_MFM, 690 MISR_OP_BM, 691 MISR_OP_MAX 692 }; 693 struct mdp_misr { 694 uint32_t block_id; 695 uint32_t frame_count; 696 uint32_t crc_op_mode; 697 uint32_t crc_value[MISR_CRC_BATCH_SIZE]; 698 }; 699 enum { 700 MDP_BLOCK_RESERVED = 0, 701 MDP_BLOCK_OVERLAY_0, 702 MDP_BLOCK_OVERLAY_1, 703 MDP_BLOCK_VG_1, 704 MDP_BLOCK_VG_2, 705 MDP_BLOCK_RGB_1, 706 MDP_BLOCK_RGB_2, 707 MDP_BLOCK_DMA_P, 708 MDP_BLOCK_DMA_S, 709 MDP_BLOCK_DMA_E, 710 MDP_BLOCK_OVERLAY_2, 711 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 712 MDP_LOGICAL_BLOCK_DISP_1, 713 MDP_LOGICAL_BLOCK_DISP_2, 714 MDP_BLOCK_MAX, 715 }; 716 struct mdp_histogram_start_req { 717 uint32_t block; 718 uint8_t frame_cnt; 719 uint8_t bit_mask; 720 uint16_t num_bins; 721 }; 722 struct mdp_histogram_data { 723 uint32_t block; 724 uint32_t bin_cnt; 725 uint32_t * c0; 726 uint32_t * c1; 727 uint32_t * c2; 728 uint32_t * extra_info; 729 }; 730 #define GC_LUT_ENTRIES_V1_7 512 731 struct mdp_ar_gc_lut_data { 732 uint32_t x_start; 733 uint32_t slope; 734 uint32_t offset; 735 }; 736 #define MDP_PP_PGC_ROUNDING_ENABLE 0x10 737 struct mdp_pgc_lut_data { 738 uint32_t version; 739 uint32_t block; 740 uint32_t flags; 741 uint8_t num_r_stages; 742 uint8_t num_g_stages; 743 uint8_t num_b_stages; 744 struct mdp_ar_gc_lut_data * r_data; 745 struct mdp_ar_gc_lut_data * g_data; 746 struct mdp_ar_gc_lut_data * b_data; 747 void * cfg_payload; 748 }; 749 #define PGC_LUT_ENTRIES 1024 750 struct mdp_pgc_lut_data_v1_7 { 751 uint32_t len; 752 uint32_t * c0_data; 753 uint32_t * c1_data; 754 uint32_t * c2_data; 755 }; 756 struct mdp_rgb_lut_data { 757 uint32_t flags; 758 uint32_t lut_type; 759 struct fb_cmap cmap; 760 }; 761 enum { 762 mdp_rgb_lut_gc, 763 mdp_rgb_lut_hist, 764 }; 765 struct mdp_lut_cfg_data { 766 uint32_t lut_type; 767 union { 768 struct mdp_igc_lut_data igc_lut_data; 769 struct mdp_pgc_lut_data pgc_lut_data; 770 struct mdp_hist_lut_data hist_lut_data; 771 struct mdp_rgb_lut_data rgb_lut_data; 772 } data; 773 }; 774 struct mdp_bl_scale_data { 775 uint32_t min_lvl; 776 uint32_t scale; 777 }; 778 struct mdp_pa_cfg_data { 779 uint32_t block; 780 struct mdp_pa_cfg pa_data; 781 }; 782 #define MDP_DITHER_DATA_V1_7_SZ 16 783 struct mdp_dither_data_v1_7 { 784 uint32_t g_y_depth; 785 uint32_t r_cr_depth; 786 uint32_t b_cb_depth; 787 uint32_t len; 788 uint32_t data[MDP_DITHER_DATA_V1_7_SZ]; 789 uint32_t temporal_en; 790 }; 791 struct mdp_pa_dither_data { 792 uint64_t data_flags; 793 uint32_t matrix_sz; 794 uint64_t matrix_data; 795 uint32_t strength; 796 uint32_t offset_en; 797 }; 798 struct mdp_dither_cfg_data { 799 uint32_t version; 800 uint32_t block; 801 uint32_t flags; 802 uint32_t mode; 803 uint32_t g_y_depth; 804 uint32_t r_cr_depth; 805 uint32_t b_cb_depth; 806 void * cfg_payload; 807 }; 808 #define MDP_GAMUT_TABLE_NUM 8 809 #define MDP_GAMUT_TABLE_NUM_V1_7 4 810 #define MDP_GAMUT_SCALE_OFF_TABLE_NUM 3 811 #define MDP_GAMUT_TABLE_V1_7_SZ 1229 812 #define MDP_GAMUT_SCALE_OFF_SZ 16 813 #define MDP_GAMUT_TABLE_V1_7_COARSE_SZ 32 814 struct mdp_gamut_cfg_data { 815 uint32_t block; 816 uint32_t flags; 817 uint32_t version; 818 uint32_t gamut_first; 819 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 820 uint16_t * r_tbl[MDP_GAMUT_TABLE_NUM]; 821 uint16_t * g_tbl[MDP_GAMUT_TABLE_NUM]; 822 uint16_t * b_tbl[MDP_GAMUT_TABLE_NUM]; 823 void * cfg_payload; 824 }; 825 enum { 826 mdp_gamut_fine_mode = 0x1, 827 mdp_gamut_coarse_mode, 828 }; 829 struct mdp_gamut_data_v1_7 { 830 uint32_t mode; 831 uint32_t map_en; 832 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM_V1_7]; 833 uint32_t * c0_data[MDP_GAMUT_TABLE_NUM_V1_7]; 834 uint32_t * c1_c2_data[MDP_GAMUT_TABLE_NUM_V1_7]; 835 uint32_t tbl_scale_off_sz[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 836 uint32_t * scale_off_data[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 837 }; 838 struct mdp_calib_config_data { 839 uint32_t ops; 840 uint32_t addr; 841 uint32_t data; 842 }; 843 struct mdp_calib_config_buffer { 844 uint32_t ops; 845 uint32_t size; 846 uint32_t * buffer; 847 }; 848 struct mdp_calib_dcm_state { 849 uint32_t ops; 850 uint32_t dcm_state; 851 }; 852 enum { 853 DCM_UNINIT, 854 DCM_UNBLANK, 855 DCM_ENTER, 856 DCM_EXIT, 857 DCM_BLANK, 858 DTM_ENTER, 859 DTM_EXIT, 860 }; 861 #define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 862 #define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 863 #define MDSS_PP_SPLIT_MASK 0x30000000 864 #define MDSS_MAX_BL_BRIGHTNESS 255 865 #define AD_BL_LIN_LEN 256 866 #define AD_BL_ATT_LUT_LEN 33 867 #define MDSS_AD_MODE_AUTO_BL 0x0 868 #define MDSS_AD_MODE_AUTO_STR 0x1 869 #define MDSS_AD_MODE_TARG_STR 0x3 870 #define MDSS_AD_MODE_MAN_STR 0x7 871 #define MDSS_AD_MODE_CALIB 0xF 872 #define MDP_PP_AD_INIT 0x10 873 #define MDP_PP_AD_CFG 0x20 874 struct mdss_ad_init { 875 uint32_t asym_lut[33]; 876 uint32_t color_corr_lut[33]; 877 uint8_t i_control[2]; 878 uint16_t black_lvl; 879 uint16_t white_lvl; 880 uint8_t var; 881 uint8_t limit_ampl; 882 uint8_t i_dither; 883 uint8_t slope_max; 884 uint8_t slope_min; 885 uint8_t dither_ctl; 886 uint8_t format; 887 uint8_t auto_size; 888 uint16_t frame_w; 889 uint16_t frame_h; 890 uint8_t logo_v; 891 uint8_t logo_h; 892 uint32_t alpha; 893 uint32_t alpha_base; 894 uint32_t al_thresh; 895 uint32_t bl_lin_len; 896 uint32_t bl_att_len; 897 uint32_t * bl_lin; 898 uint32_t * bl_lin_inv; 899 uint32_t * bl_att_lut; 900 }; 901 #define MDSS_AD_BL_CTRL_MODE_EN 1 902 #define MDSS_AD_BL_CTRL_MODE_DIS 0 903 struct mdss_ad_cfg { 904 uint32_t mode; 905 uint32_t al_calib_lut[33]; 906 uint16_t backlight_min; 907 uint16_t backlight_max; 908 uint16_t backlight_scale; 909 uint16_t amb_light_min; 910 uint16_t filter[2]; 911 uint16_t calib[4]; 912 uint8_t strength_limit; 913 uint8_t t_filter_recursion; 914 uint16_t stab_itr; 915 uint32_t bl_ctrl_mode; 916 }; 917 struct mdss_ad_bl_cfg { 918 uint32_t bl_min_delta; 919 uint32_t bl_low_limit; 920 }; 921 struct mdss_ad_init_cfg { 922 uint32_t ops; 923 union { 924 struct mdss_ad_init init; 925 struct mdss_ad_cfg cfg; 926 } params; 927 }; 928 struct mdss_ad_input { 929 uint32_t mode; 930 union { 931 uint32_t amb_light; 932 uint32_t strength; 933 uint32_t calib_bl; 934 } in; 935 uint32_t output; 936 }; 937 #define MDSS_CALIB_MODE_BL 0x1 938 struct mdss_calib_cfg { 939 uint32_t ops; 940 uint32_t calib_mask; 941 }; 942 enum { 943 mdp_op_pcc_cfg, 944 mdp_op_csc_cfg, 945 mdp_op_lut_cfg, 946 mdp_op_qseed_cfg, 947 mdp_bl_scale_cfg, 948 mdp_op_pa_cfg, 949 mdp_op_pa_v2_cfg, 950 mdp_op_dither_cfg, 951 mdp_op_gamut_cfg, 952 mdp_op_calib_cfg, 953 mdp_op_ad_cfg, 954 mdp_op_ad_input, 955 mdp_op_calib_mode, 956 mdp_op_calib_buffer, 957 mdp_op_calib_dcm_state, 958 mdp_op_max, 959 mdp_op_pa_dither_cfg, 960 mdp_op_ad_bl_cfg, 961 mdp_op_pp_max = 255, 962 }; 963 #define mdp_op_pa_dither_cfg mdp_op_pa_dither_cfg 964 #define mdp_op_pp_max mdp_op_pp_max 965 #define mdp_op_ad_bl_cfg mdp_op_ad_bl_cfg 966 enum { 967 WB_FORMAT_NV12, 968 WB_FORMAT_RGB_565, 969 WB_FORMAT_RGB_888, 970 WB_FORMAT_xRGB_8888, 971 WB_FORMAT_ARGB_8888, 972 WB_FORMAT_BGRA_8888, 973 WB_FORMAT_BGRX_8888, 974 WB_FORMAT_ARGB_8888_INPUT_ALPHA 975 }; 976 struct msmfb_mdp_pp { 977 uint32_t op; 978 union { 979 struct mdp_pcc_cfg_data pcc_cfg_data; 980 struct mdp_csc_cfg_data csc_cfg_data; 981 struct mdp_lut_cfg_data lut_cfg_data; 982 struct mdp_qseed_cfg_data qseed_cfg_data; 983 struct mdp_bl_scale_data bl_scale_data; 984 struct mdp_pa_cfg_data pa_cfg_data; 985 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 986 struct mdp_dither_cfg_data dither_cfg_data; 987 struct mdp_gamut_cfg_data gamut_cfg_data; 988 struct mdp_calib_config_data calib_cfg; 989 struct mdss_ad_init_cfg ad_init_cfg; 990 struct mdss_calib_cfg mdss_calib_cfg; 991 struct mdss_ad_input ad_input; 992 struct mdp_calib_config_buffer calib_buffer; 993 struct mdp_calib_dcm_state calib_dcm; 994 struct mdss_ad_bl_cfg ad_bl_cfg; 995 } data; 996 }; 997 #define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 998 enum { 999 metadata_op_none, 1000 metadata_op_base_blend, 1001 metadata_op_frame_rate, 1002 metadata_op_vic, 1003 metadata_op_wb_format, 1004 metadata_op_wb_secure, 1005 metadata_op_get_caps, 1006 metadata_op_crc, 1007 metadata_op_get_ion_fd, 1008 metadata_op_max 1009 }; 1010 struct mdp_blend_cfg { 1011 uint32_t is_premultiplied; 1012 }; 1013 struct mdp_mixer_cfg { 1014 uint32_t writeback_format; 1015 uint32_t alpha; 1016 }; 1017 struct mdss_hw_caps { 1018 uint32_t mdp_rev; 1019 uint8_t rgb_pipes; 1020 uint8_t vig_pipes; 1021 uint8_t dma_pipes; 1022 uint8_t max_smp_cnt; 1023 uint8_t smp_per_pipe; 1024 uint32_t features; 1025 }; 1026 struct msmfb_metadata { 1027 uint32_t op; 1028 uint32_t flags; 1029 union { 1030 struct mdp_misr misr_request; 1031 struct mdp_blend_cfg blend_cfg; 1032 struct mdp_mixer_cfg mixer_cfg; 1033 uint32_t panel_frame_rate; 1034 uint32_t video_info_code; 1035 struct mdss_hw_caps caps; 1036 uint8_t secure_en; 1037 int fbmem_ionfd; 1038 } data; 1039 }; 1040 #define MDP_MAX_FENCE_FD 32 1041 #define MDP_BUF_SYNC_FLAG_WAIT 1 1042 #define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 1043 struct mdp_buf_sync { 1044 uint32_t flags; 1045 uint32_t acq_fen_fd_cnt; 1046 uint32_t session_id; 1047 int * acq_fen_fd; 1048 int * rel_fen_fd; 1049 int * retire_fen_fd; 1050 }; 1051 struct mdp_async_blit_req_list { 1052 struct mdp_buf_sync sync; 1053 uint32_t count; 1054 struct mdp_blit_req req[]; 1055 }; 1056 #define MDP_DISPLAY_COMMIT_OVERLAY 1 1057 struct mdp_display_commit { 1058 uint32_t flags; 1059 uint32_t wait_for_finish; 1060 struct fb_var_screeninfo var; 1061 struct mdp_rect l_roi; 1062 struct mdp_rect r_roi; 1063 }; 1064 struct mdp_overlay_list { 1065 uint32_t num_overlays; 1066 struct mdp_overlay * * overlay_list; 1067 uint32_t flags; 1068 uint32_t processed_overlays; 1069 }; 1070 struct mdp_page_protection { 1071 uint32_t page_protection; 1072 }; 1073 struct mdp_mixer_info { 1074 int pndx; 1075 int pnum; 1076 int ptype; 1077 int mixer_num; 1078 int z_order; 1079 }; 1080 #define MAX_PIPE_PER_MIXER 7 1081 struct msmfb_mixer_info_req { 1082 int mixer_num; 1083 int cnt; 1084 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 1085 }; 1086 enum { 1087 DISPLAY_SUBSYSTEM_ID, 1088 ROTATOR_SUBSYSTEM_ID, 1089 }; 1090 enum { 1091 MDP_IOMMU_DOMAIN_CP, 1092 MDP_IOMMU_DOMAIN_NS, 1093 }; 1094 enum { 1095 MDP_WRITEBACK_MIRROR_OFF, 1096 MDP_WRITEBACK_MIRROR_ON, 1097 MDP_WRITEBACK_MIRROR_PAUSE, 1098 MDP_WRITEBACK_MIRROR_RESUME, 1099 }; 1100 enum mdp_color_space { 1101 MDP_CSC_ITU_R_601, 1102 MDP_CSC_ITU_R_601_FR, 1103 MDP_CSC_ITU_R_709, 1104 }; 1105 #define MDP_CSC_ITU_R_2020 (MDP_CSC_ITU_R_709 + 1) 1106 #define MDP_CSC_ITU_R_2020_FR (MDP_CSC_ITU_R_2020 + 1) 1107 enum { 1108 mdp_igc_v1_7 = 1, 1109 mdp_igc_vmax, 1110 mdp_hist_lut_v1_7, 1111 mdp_hist_lut_vmax, 1112 mdp_pgc_v1_7, 1113 mdp_pgc_vmax, 1114 mdp_dither_v1_7, 1115 mdp_dither_vmax, 1116 mdp_gamut_v1_7, 1117 mdp_gamut_vmax, 1118 mdp_pa_v1_7, 1119 mdp_pa_vmax, 1120 mdp_pcc_v1_7, 1121 mdp_pcc_vmax, 1122 mdp_pp_legacy, 1123 mdp_dither_pa_v1_7, 1124 mdp_igc_v3, 1125 mdp_pp_unknown = 255 1126 }; 1127 #define mdp_dither_pa_v1_7 mdp_dither_pa_v1_7 1128 #define mdp_pp_unknown mdp_pp_unknown 1129 #define mdp_igc_v3 mdp_igc_v3 1130 enum { 1131 IGC = 1, 1132 PCC, 1133 GC, 1134 PA, 1135 GAMUT, 1136 DITHER, 1137 QSEED, 1138 HIST_LUT, 1139 HIST, 1140 PP_FEATURE_MAX, 1141 PA_DITHER, 1142 PP_MAX_FEATURES = 25, 1143 }; 1144 #define PA_DITHER PA_DITHER 1145 #define PP_MAX_FEATURES PP_MAX_FEATURES 1146 struct mdp_pp_feature_version { 1147 uint32_t pp_feature; 1148 uint32_t version_info; 1149 }; 1150 #endif 1151