1 /** @file
2 *
3 * Copyright (c) 2016, Hisilicon Limited. All rights reserved.
4 * Copyright (c) 2016, Linaro Limited. All rights reserved.
5 *
6 * This program and the accompanying materials
7 * are licensed and made available under the terms and conditions of the BSD License
8 * which accompanies this distribution. The full text of the license may be found at
9 * http://opensource.org/licenses/bsd-license.php
10 *
11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 *
14 **/
15
16 #include "PcieInitLib.h"
17 #include <Library/DebugLib.h>
18 #include <Library/ArmLib.h>
19 #include <Library/BaseLib.h>
20 #include <Library/BaseMemoryLib.h>
21 #include <Library/IoLib.h>
22 #include <Library/PlatformPciLib.h>
23 #include <Library/TimerLib.h>
24
25 #define PCIE_SYS_REG_OFFSET 0x1000
26
27 static PCIE_INIT_CFG mPcieIntCfg;
28 UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000};
29 UINT64 io_sub0_base = 0xa0000000;
30 UINT64 PCIE_APB_SLVAE_BASE[2] = {0xb0070000, BASE_4TB + 0xb0070000};
31 #define PCIE_REG_BASE(HostBridgeNum,port) (PCIE_APB_SLVAE_BASE[HostBridgeNum] + (UINT32)(port * 0x10000))
32 UINT32 loop_test_flag[4] = {0,0,0,0};
33 UINT64 pcie_dma_des_base = PCIE_ADDR_BASE_HOST_ADDR;
34 #define PcieMaxLanNum 8
35 #define PCIE_PORT_NUM_IN_SICL 4 //SICL: Super IO Cluster
36
37
38 extern PCIE_DRIVER_CFG gastr_pcie_driver_cfg;
39 extern PCIE_IATU gastr_pcie_iatu_cfg;
40 extern PCIE_IATU_VA mPcieIatuTable;
41
PcieRegWrite(UINT32 Port,UINTN Offset,UINT32 Value)42 VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value)
43 {
44 RegWrite((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value);
45
46 }
47
PcieRegRead(UINT32 Port,UINTN Offset)48 UINT32 PcieRegRead(UINT32 Port, UINTN Offset)
49 {
50 UINT32 Value = 0;
51
52 RegRead((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value);
53 return Value;
54 }
55
PcieMmioWrite(UINT32 Port,UINTN Offset0,UINTN Offset1,UINT32 Value)56 VOID PcieMmioWrite(UINT32 Port, UINTN Offset0, UINTN Offset1, UINT32 Value)
57 {
58 RegWrite((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
59 }
60
PcieMmioRead(UINT32 Port,UINTN Offset0,UINTN Offset1)61 UINT32 PcieMmioRead(UINT32 Port, UINTN Offset0, UINTN Offset1)
62 {
63 UINT32 Value = 0;
64 RegRead((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
65 return Value;
66 }
67
PcieChangeRwMode(UINT32 HostBridgeNum,UINT32 Port,PCIE_RW_MODE Mode)68 VOID PcieChangeRwMode(UINT32 HostBridgeNum, UINT32 Port, PCIE_RW_MODE Mode)
69 {
70 u_sc_pcie0_clkreq pcie0;
71 u_sc_pcie1_clkreq pcie1;
72 u_sc_pcie2_clkreq pcie2;
73 u_sc_pcie3_clkreq pcie3;
74
75 switch(Port)
76 {
77 case 0:
78 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32);
79 pcie0.Bits.pcie0_apb_cfg_sel = Mode;
80 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_CLKREQ_REG, pcie0.UInt32);
81 break;
82 case 1:
83 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32);
84 pcie1.Bits.pcie1_apb_cfg_sel = Mode;
85 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE1_CLKREQ_REG, pcie1.UInt32);
86 break;
87 case 2:
88 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32);
89 pcie2.Bits.pcie2_apb_cfg_sel = Mode;
90 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE2_CLKREQ_REG, pcie2.UInt32);
91 break;
92 case 3:
93 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32);
94 pcie3.Bits.pcie3_apb_cfg_sel = Mode;
95 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_CLKREQ_REG, pcie3.UInt32);
96 break;
97 default:
98 break;
99 }
100 }
101
PcieRxValidCtrl(UINT32 soctype,UINT32 HostBridgeNum,UINT32 Port,BOOLEAN On)102 VOID PcieRxValidCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, BOOLEAN On)
103 {
104 UINT32 i;
105 UINT32 Lanenum;
106 UINT32 Value;
107 UINT32 Laneid;
108 UINT32 Loopcnt;
109 UINT32 Lockedcnt[PcieMaxLanNum] = {0};
110
111 Lanenum = 8;
112 if (0x1610 == soctype)
113 {
114 if (On) {
115 /*
116 * to valid the RX, firstly, we should check and make
117 * sure the RX lanes have been steadily locked.
118 */
119 for (Loopcnt = 500 * Lanenum; Loopcnt > 0; Loopcnt--) {
120 Laneid = Loopcnt % Lanenum;
121 RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0xf4 + Laneid * 0x4, Value);
122 if (((Value >> 21) & 0x7) >= 4)
123 Lockedcnt[Laneid]++;
124 else
125 Lockedcnt[Laneid] = 0;
126 /*
127 * If we get a locked status above 8 times incessantly
128 * on anyone of the lanes, we get a stable lock.
129 */
130 if (Lockedcnt[Laneid] >= 8)
131 break;
132 if (Laneid == (Lanenum - 1))
133 MicroSecondDelay(500);
134 }
135 if (Loopcnt == 0)
136 DEBUG((EFI_D_ERROR, "pcs locked timeout!\n"));
137 for (i = 0; i < Lanenum; i++) {
138 RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i * 0x4, Value);
139 Value &= (~BIT14);
140 RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
141 }
142 } else {
143 for (i = 0; i < Lanenum; i++) {
144 RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i * 0x4, Value);
145 Value |= BIT14;
146 Value &= (~BIT15);
147 RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
148 }
149 }
150 }
151 }
152
PcieEnableItssm(UINT32 soctype,UINT32 HostBridgeNum,UINT32 Port)153 EFI_STATUS PcieEnableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
154 {
155 PCIE_CTRL_7_U pcie_ctrl7;
156 UINT32 Value = 0;
157
158 if (Port >= PCIE_MAX_ROOTBRIDGE) {
159 return EFI_INVALID_PARAMETER;
160 }
161
162 if (0x1610 == soctype)
163 {
164 RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value);
165 Value |= BIT11|BIT30|BIT31;
166 RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value);
167 (VOID)PcieRxValidCtrl(soctype, HostBridgeNum, Port, 1);
168 return EFI_SUCCESS;
169 }
170 else
171 {
172 PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
173
174 pcie_ctrl7.UInt32 = PcieRegRead(Port, PCIE_CTRL_7_REG);
175 pcie_ctrl7.Bits.pcie_linkdown_auto_rstn_enable = 0x1;
176 pcie_ctrl7.Bits.pcie2_app_ltssm_enable = 0x1;
177 PcieRegWrite(Port, PCIE_CTRL_7_REG, pcie_ctrl7.UInt32);
178
179 PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
180
181 return EFI_SUCCESS;
182 }
183
184 }
185
PciPerfTuning(UINT32 soctype,UINT32 HostBridgeNum,UINT32 Port)186 STATIC EFI_STATUS PciPerfTuning(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
187 {
188 UINT32 Value;
189 UINTN RegSegmentOffset;
190
191 if (Port >= PCIE_MAX_ROOTBRIDGE) {
192 DEBUG((DEBUG_ERROR, "Invalid port number: %d\n", Port));
193 return EFI_INVALID_PARAMETER;
194 }
195
196 RegSegmentOffset = PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET;
197
198 //Enable SMMU bypass for translation
199 RegRead(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value);
200 //BIT13: controller master read SMMU bypass
201 //BIT12: controller master write SMMU bypass
202 //BIT10: SMMU bypass enable
203 Value |= (BIT13 | BIT12 | BIT10);
204 RegWrite(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value);
205
206 //Switch strongly order (SO) to relaxed order (RO) for write transaction
207 RegRead(RegSegmentOffset + PCIE_CTRL_6_REG, Value);
208 //BIT13 | BIT12: Enable write merge and SMMU streaming ordered write acknowledge
209 Value |= (BIT13 | BIT12);
210 //BIT29 | BIT27 | BIT25 | BIT23 | BIT21 | BIT19 | BIT17: Enable RO for all types of write transaction
211 Value |= (BIT29 | BIT27 | BIT25 | BIT23 | BIT21 | BIT19 | BIT17);
212 RegWrite(RegSegmentOffset + PCIE_CTRL_6_REG, Value);
213
214 //Force streamID for controller read operation
215 RegRead(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value);
216 //Force using streamID in PCIE_SYS_CTRL54_REG
217 Value &= ~(BIT30);
218 //Set streamID to 0, bit[0:15] is for request ID and should be kept
219 Value &= ~(0xff << 16);
220 RegWrite(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value);
221
222 //Enable read and write snoopy
223 RegRead(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value);
224 Value |= (BIT30 | BIT28);
225 RegWrite(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value);
226
227 return EFI_SUCCESS;
228 }
229
PcieDisableItssm(UINT32 soctype,UINT32 HostBridgeNum,UINT32 Port)230 EFI_STATUS PcieDisableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
231 {
232 PCIE_CTRL_7_U pcie_ctrl7;
233 UINT32 Value = 0;
234
235 if(Port >= PCIE_MAX_ROOTBRIDGE) {
236 return PCIE_ERR_PARAM_INVALID;
237 }
238
239 if (0x1610 == soctype)
240 {
241 RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value);
242 Value &= ~(BIT11);
243 RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value);
244 PcieRxValidCtrl(soctype, HostBridgeNum, Port, 1);
245 return EFI_SUCCESS;
246 }
247 else
248 {
249 PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
250
251 pcie_ctrl7.UInt32 = PcieRegRead(Port, PCIE_CTRL_7_REG);
252 pcie_ctrl7.Bits.pcie2_app_ltssm_enable = 0x0;
253 PcieRegWrite(Port,PCIE_CTRL_7_REG, pcie_ctrl7.UInt32);
254
255 PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
256
257 return EFI_SUCCESS;
258 }
259
260 }
261
262
PcieLinkSpeedSet(UINT32 Port,PCIE_PORT_GEN Speed)263 EFI_STATUS PcieLinkSpeedSet(UINT32 Port,PCIE_PORT_GEN Speed)
264 {
265 PCIE_EP_PCIE_CAP12_U pcie_cap12;
266
267 if(Port >= PCIE_MAX_ROOTBRIDGE) {
268 return EFI_INVALID_PARAMETER;
269 }
270
271 pcie_cap12.UInt32 = PcieRegRead(Port, PCIE_EP_PCIE_CAP12_REG);
272 pcie_cap12.Bits.targetlinkspeed = Speed;
273 PcieRegWrite(Port, PCIE_EP_PCIE_CAP12_REG, pcie_cap12.UInt32);
274
275 if(mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_NTB ||
276 mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_RP)
277 {
278 pcie_cap12.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PCIE_CAP12_REG);
279 pcie_cap12.Bits.targetlinkspeed = Speed;
280 PcieMmioWrite(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PCIE_CAP12_REG, pcie_cap12.UInt32);
281 }
282 return EFI_SUCCESS;
283 }
284
PcieLinkWidthSet(UINT32 Port,PCIE_PORT_WIDTH Width)285 EFI_STATUS PcieLinkWidthSet(UINT32 Port, PCIE_PORT_WIDTH Width)
286 {
287 PCIE_EP_PORT_LOGIC4_U pcie_logic4;
288 PCIE_EP_PORT_LOGIC22_U logic22;
289
290 if(Port >= PCIE_MAX_ROOTBRIDGE) {
291 return PCIE_ERR_PARAM_INVALID;
292 }
293
294 pcie_logic4.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC4_REG);
295 pcie_logic4.Bits.linkmodeenable = Width;
296 pcie_logic4.Bits.crosslinkenable = 0;
297 pcie_logic4.Bits.fastlinkmode = 1;
298 PcieRegWrite(Port, PCIE_EP_PORT_LOGIC4_REG, pcie_logic4.UInt32);
299
300 logic22.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC22_REG);
301 logic22.Bits.n_fts = 0xff;
302 if(Width == PCIE_WITDH_X1)
303 {
304 logic22.Bits.pre_determ_num_of_lane = 1;
305 }
306 else if(Width == PCIE_WITDH_X2)
307 {
308 logic22.Bits.pre_determ_num_of_lane = 2;
309 }
310 else
311 {
312 logic22.Bits.pre_determ_num_of_lane = 3;
313 }
314 PcieRegWrite(Port, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
315
316 if(mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_NTB ||
317 mPcieIntCfg.Dev[Port].PcieDevice.PortInfo.PortType == PCIE_NTB_TO_RP)
318 {
319 pcie_logic4.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC4_REG);
320 pcie_logic4.Bits.linkmodeenable = Width;
321 pcie_logic4.Bits.crosslinkenable = 0;
322 pcie_logic4.Bits.fastlinkmode = 1;
323 PcieMmioWrite(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC4_REG, pcie_logic4.UInt32);
324
325 logic22.UInt32 = PcieMmioRead(Port, PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC22_REG);
326 logic22.Bits.n_fts = 0xff;
327 if(Width == PCIE_WITDH_X1)
328 {
329 logic22.Bits.pre_determ_num_of_lane = 1;
330 }
331 else if(Width == PCIE_WITDH_X2)
332 {
333 logic22.Bits.pre_determ_num_of_lane = 2;
334 }
335 else
336 {
337 logic22.Bits.pre_determ_num_of_lane = 3;
338 }
339 PcieMmioWrite(Port,PCIE_MMIO_EEP_CFG, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
340 }
341 return EFI_SUCCESS;
342 }
343
PcieSetupRC(UINT32 Port,PCIE_PORT_WIDTH Width)344 EFI_STATUS PcieSetupRC(UINT32 Port, PCIE_PORT_WIDTH Width)
345 {
346 PCIE_EP_PORT_LOGIC22_U logic22;
347 PCIE_EEP_PCI_CFG_HDR15_U hdr15;
348 UINT32 Value = 0;
349 if(Port >= PCIE_MAX_ROOTBRIDGE) {
350 return EFI_INVALID_PARAMETER;
351 }
352
353 Value = PcieRegRead(Port, PCIE_EP_PORT_LOGIC4_REG);
354 Value &= ~(0x3f<<16);
355
356 if(Width == PCIE_WITDH_X1)
357 {
358 Value |= (0x1 << 16);
359 }
360 else if(Width == PCIE_WITDH_X2)
361 {
362 Value |= (0x3 << 16);
363 }
364 else if(Width == PCIE_WITDH_X4)
365 {
366 Value |= (0x7 << 16);
367 }
368 else if(Width == PCIE_WITDH_X8)
369 {
370 Value |= (0xf << 16);
371 }
372 else
373 {
374 DEBUG((EFI_D_ERROR,"Width is not valid\n"));
375 }
376
377 PcieRegWrite(Port, PCIE_EP_PORT_LOGIC4_REG, Value);
378
379 logic22.UInt32 = PcieRegRead(Port, PCIE_EP_PORT_LOGIC22_REG);
380 if(Width == PCIE_WITDH_X1)
381 {
382 logic22.Bits.pre_determ_num_of_lane = 1;
383 }
384 else if(Width == PCIE_WITDH_X2)
385 {
386 logic22.Bits.pre_determ_num_of_lane = 2;
387 }
388 else if(Width == PCIE_WITDH_X4)
389 {
390 logic22.Bits.pre_determ_num_of_lane = 4;
391 }
392 else if(Width == PCIE_WITDH_X8)
393 {
394 logic22.Bits.pre_determ_num_of_lane = 8;
395 }
396 else
397 {
398 DEBUG((EFI_D_ERROR,"Width is not valid\n"));
399 }
400
401 logic22.UInt32 |= (0x100<<8);
402 logic22.UInt32 |= (0x1<<17);
403 PcieRegWrite(Port, PCIE_EP_PORT_LOGIC22_REG, logic22.UInt32);
404
405 /* setup RC BARs */
406 PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR4_REG, 0x00000004);
407 PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR5_REG, 0x00000000);
408
409 /* setup interrupt pins */
410 hdr15.UInt32 = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR15_REG);
411 hdr15.UInt32 &= 0xffff00ff;
412 hdr15.UInt32 |= 0x00000100;
413 PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR15_REG, hdr15.UInt32);
414
415 /* setup bus numbers */
416 Value = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR6_REG);
417 Value &= 0xff000000;
418 Value |= 0x00010100;
419 PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR6_REG, Value);
420
421 /* setup command register */
422 Value = PcieRegRead(Port, PCIE_EP_PCI_CFG_HDR1_REG);
423 Value &= 0xffff0000;
424 Value |= 0x1|0x2|0x4|0x100;
425 PcieRegWrite(Port, PCIE_EP_PCI_CFG_HDR1_REG, Value);
426
427 return EFI_SUCCESS;
428 }
429
430
PcieModeSet(UINT32 soctype,UINT32 HostBridgeNum,UINT32 Port,PCIE_PORT_TYPE PcieType)431 EFI_STATUS PcieModeSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, PCIE_PORT_TYPE PcieType)
432 {
433 PCIE_CTRL_0_U str_pcie_ctrl_0;
434
435 if(Port >= PCIE_MAX_ROOTBRIDGE) {
436 return EFI_INVALID_PARAMETER;
437 }
438
439 if (0x1610 == soctype)
440 {
441 RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0xf8, 0x4 << 28);
442 }
443 else
444 {
445 PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
446
447 str_pcie_ctrl_0.UInt32 = PcieRegRead(Port, PCIE_CTRL_0_REG);
448 if(PcieType == PCIE_END_POINT)
449 {
450 str_pcie_ctrl_0.Bits.pcie2_slv_device_type = PCIE_EP_DEVICE;
451 }
452 else
453 {
454 str_pcie_ctrl_0.Bits.pcie2_slv_device_type = RP_OF_PCIE_RC;
455 }
456 PcieRegWrite(Port, PCIE_CTRL_0_REG, str_pcie_ctrl_0.UInt32);
457
458 PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
459 }
460 return EFI_SUCCESS;
461 }
462
PciePcsInit(UINT32 soctype,UINT32 HostBridgeNum,UINT32 Port)463 VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
464 {
465 UINT8 i = 0;
466 UINT32 Value = 0;
467 if (0x1610 == soctype)
468 {
469 for (i = 0; i < PcieMaxLanNum; i++) {
470 RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
471 Value |= (1 << 20); //bit 20: rxvalid enable
472 RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
473 }
474 PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0);
475 RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090);
476 }
477 else
478 {
479 if(Port<=2)
480 {
481 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8020, 0x2026044);
482 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8060, 0x2126044);
483 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80c4, 0x2126044);
484 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80e4, 0x2026044);
485
486 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80a0, 0x4018);
487 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80a4, 0x804018);
488 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80c0, 0x11201100);
489 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x15c, 0x3);
490 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x158, 0);
491 }
492 else
493
494 {
495 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x74, 0x46e000);
496 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x78, 0x46e000);
497 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x7c, 0x46e000);
498 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x80, 0x46e000);
499 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x84, 0x46e000);
500 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x88, 0x46e000);
501 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x8c, 0x46e000);
502 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x90, 0x46e000);
503
504 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x34, 0x1001);
505 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x38, 0x1001);
506 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x3c, 0x1001);
507 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x40, 0x1001);
508 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x44, 0x1001);
509 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x48, 0x1001);
510 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x4c, 0x1001);
511 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0x50, 0x1001);
512
513 RegWrite(pcie_subctrl_base[HostBridgeNum] + 0xc0000 + (UINT32)(Port * 0x10000) + 0xe4, 0xffff);
514 }
515 }
516 return;
517 }
518
PcieEqualization(UINT32 soctype,UINT32 HostBridgeNum,UINT32 Port)519 VOID PcieEqualization(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
520 {
521 UINT32 Value;
522
523 if (0x1610 == soctype)
524 {
525 PcieRegWrite(Port, 0x890, 0x1c00);
526 }
527 else
528 PcieRegWrite(Port, 0x890, 0x1400);
529 PcieRegWrite(Port, 0x894, 0xfd7);
530
531 PcieRegWrite(Port, 0x89c, 0x0);
532 PcieRegWrite(Port, 0x898, 0xfc00);
533 PcieRegWrite(Port, 0x89c, 0x1);
534 PcieRegWrite(Port, 0x898, 0xbd00);
535 PcieRegWrite(Port, 0x89c, 0x2);
536 PcieRegWrite(Port, 0x898, 0xccc0);
537 PcieRegWrite(Port, 0x89c, 0x3);
538 PcieRegWrite(Port, 0x898, 0x8dc0);
539 PcieRegWrite(Port, 0x89c, 0x4);
540 PcieRegWrite(Port, 0x898, 0xfc0);
541 PcieRegWrite(Port, 0x89c, 0x5);
542 PcieRegWrite(Port, 0x898, 0xe46);
543 PcieRegWrite(Port, 0x89c, 0x6);
544 PcieRegWrite(Port, 0x898, 0xdc8);
545 PcieRegWrite(Port, 0x89c, 0x7);
546 PcieRegWrite(Port, 0x898, 0xcb46);
547 PcieRegWrite(Port, 0x89c, 0x8);
548 PcieRegWrite(Port, 0x898, 0x8c07);
549 PcieRegWrite(Port, 0x89c, 0x9);
550 PcieRegWrite(Port, 0x898, 0xd0b);
551 PcieRegWrite(Port, 0x8a8, 0x103ff21);
552 if (0x1610 == soctype)
553 {
554 PcieRegWrite(Port, 0x164, 0x44444444);
555 PcieRegWrite(Port, 0x168, 0x44444444);
556 PcieRegWrite(Port, 0x16c, 0x44444444);
557 PcieRegWrite(Port, 0x170, 0x44444444);
558 RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x2d0, Value);
559 Value &= (~0x3f);
560 Value |= 0x5;
561 RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x2d0, Value);
562
563 }
564 else
565 {
566 Value = PcieRegRead(Port, 0x80);
567 Value |= 0x80;
568 PcieRegWrite(Port, 0x80, Value);
569
570 PcieRegWrite(Port, 0x184, 0x44444444);
571 PcieRegWrite(Port, 0x188, 0x44444444);
572 PcieRegWrite(Port, 0x18c, 0x44444444);
573 PcieRegWrite(Port, 0x190, 0x44444444);
574 }
575 }
576
577
AssertPcieCoreReset(UINT32 soctype,UINT32 HostBridgeNum,UINT32 Port)578 EFI_STATUS AssertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
579 {
580 UINT32 PortIndexInSicl;
581 if(Port >= PCIE_MAX_ROOTBRIDGE) {
582 return EFI_INVALID_PARAMETER;
583 }
584
585 if(PcieIsLinkUp(soctype, HostBridgeNum, Port))
586 {
587 (VOID)PcieDisableItssm(soctype, HostBridgeNum, Port);
588 }
589
590 if (0x1610 == soctype)
591 {
592 PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
593 if (PortIndexInSicl <= 2) {
594 RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * PortIndexInSicl), 0x3);
595 MicroSecondDelay(0x1000);
596 }
597 else
598 {
599 RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG, 0x3);
600 MicroSecondDelay(0x1000);
601 }
602 }
603 else
604 {
605 if(Port <= 2)
606 {
607 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1);
608 MicroSecondDelay(0x1000);
609 }
610 else
611 {
612 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1);
613 MicroSecondDelay(0x1000);
614 }
615 }
616
617 return EFI_SUCCESS;
618 }
619
DeassertPcieCoreReset(UINT32 soctype,UINT32 HostBridgeNum,UINT32 Port)620 EFI_STATUS DeassertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
621 {
622 UINT32 PortIndexInSicl;
623 if(Port >= PCIE_MAX_ROOTBRIDGE) {
624 return EFI_INVALID_PARAMETER;
625 }
626
627 if(PcieIsLinkUp(soctype, HostBridgeNum, Port))
628 {
629 (VOID)PcieDisableItssm(soctype, HostBridgeNum, Port);
630 }
631
632 if (0x1610 == soctype)
633 {
634 PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
635 if (PortIndexInSicl <= 2) {
636 RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * PortIndexInSicl), 0x3);
637 MicroSecondDelay(0x1000);
638 }
639 else
640 {
641 RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG, 0x3);
642 MicroSecondDelay(0x1000);
643 }
644 }
645 else
646 {
647 if(Port <= 2)
648 {
649 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1);
650 MicroSecondDelay(0x1000);
651 }
652 else
653 {
654 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1);
655 MicroSecondDelay(0x1000);
656 }
657 }
658
659 return EFI_SUCCESS;
660 }
661
AssertPciePcsReset(UINT32 soctype,UINT32 HostBridgeNum,UINT32 Port)662 EFI_STATUS AssertPciePcsReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
663 {
664 u_sc_pcie_hilink_pcs_reset_req reset_req;
665 UINT32 PortIndexInSicl;
666 if (0x1610 == soctype)
667 {
668 PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
669 reset_req.UInt32 = 0;
670 reset_req.UInt32 = reset_req.UInt32 | (0x1 << PortIndexInSicl);
671 RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
672 RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_APB_RESET_REQ_REG, reset_req.UInt32);
673
674 reset_req.UInt32 = 0;
675 reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * PortIndexInSicl));
676 RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
677 //0x1000 microseconds delay comes from experiment and
678 //should be fairly enough for this operation.
679 MicroSecondDelay(0x1000);
680 }
681 else
682 {
683 if(Port <= 3)
684 {
685 reset_req.UInt32 = 0;
686 reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
687 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
688
689 reset_req.UInt32 = 0;
690 reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
691 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
692 MicroSecondDelay(0x1000);
693 }
694 }
695 return EFI_SUCCESS;
696 }
697
DeassertPciePcsReset(UINT32 soctype,UINT32 HostBridgeNum,UINT32 Port)698 EFI_STATUS DeassertPciePcsReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
699 {
700 u_sc_pcie_hilink_pcs_reset_req reset_req;
701 UINT32 PortIndexInSicl;
702 if (0x1610 == soctype)
703 {
704 PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
705 reset_req.UInt32 = 0;
706 reset_req.UInt32 = reset_req.UInt32 | (0x1 << PortIndexInSicl);
707 RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + 0xacc, reset_req.UInt32);
708 RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32);
709
710 reset_req.UInt32 = 0;
711 reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * PortIndexInSicl));
712 RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32);
713 //0x1000 microseconds delay comes from experimenti
714 // and should be fairly enough for this operation.
715 MicroSecondDelay(0x1000);
716 }
717 else
718 {
719 if(Port <= 3)
720 {
721 reset_req.UInt32 = 0;
722 reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
723 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32);
724
725 reset_req.UInt32 = 0;
726 reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
727 RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32);
728 MicroSecondDelay(0x1000);
729 }
730 }
731
732 return EFI_SUCCESS;
733 }
734
HisiPcieClockCtrl(UINT32 soctype,UINT32 HostBridgeNum,UINT32 Port,BOOLEAN Clock)735 EFI_STATUS HisiPcieClockCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, BOOLEAN Clock)
736 {
737 UINT32 reg_clock_disable;
738 UINT32 reg_clock_enable;
739 UINT32 PortIndexInSicl;
740 PortIndexInSicl = Port % PCIE_PORT_NUM_IN_SICL;
741 if (PortIndexInSicl == 3) {
742 reg_clock_disable = PCIE_SUBCTRL_SC_PCIE3_CLK_DIS_REG;
743 reg_clock_enable = PCIE_SUBCTRL_SC_PCIE3_CLK_EN_REG;
744 } else {
745 reg_clock_disable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_DIS_REG(PortIndexInSicl);
746 reg_clock_enable = PCIE_SUBCTRL_SC_PCIE0_2_CLK_EN_REG(PortIndexInSicl);
747 }
748
749 if (0x1610 == soctype)
750 {
751 if (Clock)
752 RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + reg_clock_enable, 0x7);
753 else
754 RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + reg_clock_disable, 0x7);
755 }
756 else
757 {
758 if (Clock)
759 RegWrite(pcie_subctrl_base[HostBridgeNum] + reg_clock_enable, 0x3);
760 else
761 RegWrite(pcie_subctrl_base[HostBridgeNum] + reg_clock_disable, 0x3);
762 }
763 return EFI_SUCCESS;
764 }
765
PciePortNumSet(UINT32 soctype,UINT32 HostBridgeNum,UINT32 Port,UINT8 Num)766 VOID PciePortNumSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Num)
767 {
768 if (0x1610 == soctype)
769 {
770 UINT32 Value = 0;
771 RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x1c, Value);
772 Value &= ~(0xff);
773 Value |= Num;
774 RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1000 + 0x1c, Value);
775 }
776 return;
777 }
778
PcieLaneReversalSet(UINT32 soctype,UINT32 HostBridgeNum,UINT32 Port)779 VOID PcieLaneReversalSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
780 {
781 UINT32 Value = 0;
782 if (0x1610 == soctype)
783 {
784 RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PORT_LOGIC22_REG, Value);
785 Value |= BIT16;
786 RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PORT_LOGIC22_REG, Value);
787 }
788 return;
789 }
PcieMaskLinkUpInit(UINT32 soctype,UINT32 HostBridgeNum,UINT32 Port)790 EFI_STATUS PcieMaskLinkUpInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
791 {
792 UINT32 Value = 0;
793 if (0x1610 == soctype)
794 {
795 Value = PcieRegRead(Port, 0x120);
796 Value |= 1 << 25;
797 PcieRegWrite(Port,0x120, Value);
798 }
799 else
800 {
801 PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
802 Value = PcieRegRead(Port, 0x1d0);
803 Value |= 1 << 12;
804 PcieRegWrite(Port,0x1d0, Value);
805 PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
806 }
807 return EFI_SUCCESS;
808 }
809
PcieIsLinkUp(UINT32 soctype,UINT32 HostBridgeNum,UINT32 Port)810 BOOLEAN PcieIsLinkUp(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
811 {
812 UINT32 Value = 0;
813 U_SC_PCIE0_SYS_STATE4 PcieStat;
814 if (0x1610 == soctype)
815 {
816 RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x131c, PcieStat.UInt32);
817 Value = PcieStat.UInt32;
818 if ((Value & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE)
819 return TRUE;
820 return FALSE;
821 }
822 else
823 {
824 RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG + (UINT32)(0x100 * Port), PcieStat.UInt32);
825 Value = PcieStat.UInt32;
826 if ((Value & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE)
827 return TRUE;
828 return FALSE;
829 }
830 }
831
PcieClockIsLock(UINT32 soctype,UINT32 HostBridgeNum,UINT32 Port)832 BOOLEAN PcieClockIsLock(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
833 {
834 UINT32 Value = 0;
835 if (0x1610 == soctype)
836 {
837 RegRead( PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x504, Value);
838 return ((Value & 0x3) == 0x3);
839 }
840 else return TRUE;
841
842 }
843
PcieSpdSet(UINT32 soctype,UINT32 HostBridgeNum,UINT32 Port,UINT8 Spd)844 VOID PcieSpdSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Spd)
845 {
846 UINT32 Value = 0;
847 if (0x1610 == soctype)
848 {
849 RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0xa0, Value);
850 Value &= ~(0xf);
851 Value |= Spd;
852 RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0xa0, Value);
853 return;
854 }
855 return;
856 }
857
PcieWriteOwnConfig(UINT32 HostBridgeNum,UINT32 Port,UINT32 Offset,UINT32 Data)858 VOID PcieWriteOwnConfig(UINT32 HostBridgeNum, UINT32 Port, UINT32 Offset, UINT32 Data)
859 {
860 UINT32 Value = 0;
861 {
862 RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + (Offset & (~0x3)), Value);
863 Value &= 0x0000ffff;
864 Value |= 0x06040000;
865 RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + (Offset & (~0x3)), Value);
866 return;
867 }
868 }
869
SysRegWrite(UINT32 SocType,UINT32 HostBridgeNum,UINT32 Port,UINTN Reg,UINTN Value)870 VOID SysRegWrite(UINT32 SocType, UINT32 HostBridgeNum, UINT32 Port, UINTN Reg, UINTN Value)
871 {
872 if (SocType == 0x1610) {
873 RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + Reg, Value);
874 } else {
875 //PCIE_APB_SLVAE_BASE is for 660,and each PCIe Ccontroller has the same APB_SLVAE_BASE
876 //in the same hostbridge.
877 RegWrite(PCIE_APB_SLVAE_BASE[HostBridgeNum] + Reg, Value);
878 }
879 }
880
PcieConfigContextHi1610(UINT32 soctype,UINT32 HostBridgeNum,UINT32 Port)881 void PcieConfigContextHi1610(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
882 {
883 UINT32 Value = 0;
884 UINT64 GicdSetSpiReg = PcdGet64 (PcdGicDistributorBase) + 0x40;
885
886 if (FeaturePcdGet (PcdIsItsSupported)) {
887 //PCIE_SYS_CTRL24_REG is MSI Low address register
888 //PCIE_SYS_CTRL28_REG is MSI High addres register
889 SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL24_REG, PCIE_ITS_1610[HostBridgeNum][Port]);
890 SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL28_REG, PCIE_ITS_1610[HostBridgeNum][Port] >> 32);
891 } else {
892 SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL24_REG, GicdSetSpiReg);
893 SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL28_REG, GicdSetSpiReg >> 32);
894 }
895 RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value);
896 Value |= (1 << 12);
897 RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x11c8, Value);
898
899 return;
900 }
901
902 EFI_STATUS
903 EFIAPI
PciePortInit(IN UINT32 soctype,IN UINT32 HostBridgeNum,IN PCIE_DRIVER_CFG * PcieCfg)904 PciePortInit (
905 IN UINT32 soctype,
906 IN UINT32 HostBridgeNum,
907 IN PCIE_DRIVER_CFG *PcieCfg
908 )
909 {
910 UINT16 Count = 0;
911 UINT32 PortIndex = PcieCfg->PortIndex;
912
913 if (PortIndex >= PCIE_MAX_ROOTBRIDGE) {
914 return EFI_INVALID_PARAMETER;
915 }
916
917 if (0x1610 == soctype)
918 {
919 mPcieIntCfg.RegResource[PortIndex] = (VOID *)PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][PortIndex];
920 DEBUG((DEBUG_INFO, "Soc type is 161x\n"));
921 }
922 else
923 {
924 mPcieIntCfg.RegResource[PortIndex] = (VOID *)(UINTN)PCIE_REG_BASE(HostBridgeNum, PortIndex);
925 DEBUG((EFI_D_INFO, "Soc type is 660\n"));
926 }
927
928 /* assert reset signals */
929 (VOID)AssertPcieCoreReset(soctype, HostBridgeNum, PortIndex);
930 (VOID)AssertPciePcsReset(soctype, HostBridgeNum, PortIndex);
931 (VOID)HisiPcieClockCtrl(soctype, HostBridgeNum, PortIndex, 0);
932 (VOID)DeassertPcieCoreReset(soctype, HostBridgeNum, PortIndex);
933 /* de-assert phy reset */
934 (VOID)DeassertPciePcsReset(soctype, HostBridgeNum, PortIndex);
935
936 /* de-assert core reset */
937 (VOID)HisiPcieClockCtrl(soctype, HostBridgeNum, PortIndex, 1);
938
939 while (!PcieClockIsLock(soctype, HostBridgeNum, PortIndex)) {
940 MicroSecondDelay(1000);
941 Count++;
942 if (Count >= 50) {
943 DEBUG((EFI_D_ERROR, "HostBridge %d, Port %d PLL Lock failed\n", HostBridgeNum, PortIndex));
944 return PCIE_ERR_LINK_OVER_TIME;
945 }
946 }
947 /* initialize phy */
948 (VOID)PciePcsInit(soctype, HostBridgeNum, PortIndex);
949
950 (VOID)PcieModeSet(soctype, HostBridgeNum, PortIndex,PcieCfg->PortInfo.PortType);
951 (VOID)PcieSpdSet(soctype, HostBridgeNum, PortIndex, 3);
952 (VOID)PciePortNumSet(soctype, HostBridgeNum, PortIndex, 0);
953 /* setup root complex */
954 (VOID)PcieSetupRC(PortIndex,PcieCfg->PortInfo.PortWidth);
955
956 /* disable link up interrupt */
957 (VOID)PcieMaskLinkUpInit(soctype, HostBridgeNum, PortIndex);
958
959 /* Pcie Equalization*/
960 (VOID)PcieEqualization(soctype ,HostBridgeNum, PortIndex);
961
962 /* assert LTSSM enable */
963 (VOID)PcieEnableItssm(soctype, HostBridgeNum, PortIndex);
964 if (FeaturePcdGet(PcdIsPciPerfTuningEnable)) {
965 //PCIe will still work even if performance tuning fails,
966 //and there is warning message inside the function to print
967 //detailed error if there is.
968 (VOID)PciPerfTuning(soctype, HostBridgeNum, PortIndex);
969 }
970
971 PcieConfigContextHi1610(soctype, HostBridgeNum, PortIndex);
972 /*
973 * The default size of BAR0 in Hi1610 host bridge is 0x10000000,
974 * which will bring problem when most resource has been allocated
975 * to BAR0 in host bridge.However, we need not use BAR0 in host bridge
976 * in RC mode. Here we just disable it
977 */
978 PcieRegWrite(PortIndex, 0x10, 0);
979 (VOID)PcieWriteOwnConfig(HostBridgeNum, PortIndex, 0xa, 0x0604);
980 /* check if the link is up or not */
981 while (!PcieIsLinkUp(soctype, HostBridgeNum, PortIndex)) {
982 MicroSecondDelay(1000);
983 Count++;
984 if (Count >= 1000) {
985 DEBUG((EFI_D_ERROR, "HostBridge %d, Port %d link up failed\n", HostBridgeNum, PortIndex));
986 return PCIE_ERR_LINK_OVER_TIME;
987 }
988 }
989 DEBUG((EFI_D_INFO, "HostBridge %d, Port %d Link up ok\n", HostBridgeNum, PortIndex));
990
991 PcieRegWrite(PortIndex, 0x8BC, 0);
992
993 return EFI_SUCCESS;
994 }
995
996
997
998
PcieSetDBICS2Enable(UINT32 HostBridgeNum,UINT32 Port,UINT32 Enable)999 EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable)
1000 {
1001 PCIE_SYS_CTRL20_U dbi_ro_enable;
1002
1003 if (Port >= PCIE_MAX_ROOTBRIDGE) {
1004 return EFI_INVALID_PARAMETER;
1005 }
1006
1007 PcieChangeRwMode(HostBridgeNum, Port, PCIE_SYS_CONTROL);
1008 dbi_ro_enable.UInt32 = PcieRegRead(Port, PCIE_SYS_CTRL20_REG);
1009 dbi_ro_enable.Bits.ro_sel = Enable;
1010 PcieRegWrite(Port, PCIE_SYS_CTRL20_REG, dbi_ro_enable.UInt32);
1011 PcieChangeRwMode(HostBridgeNum, Port, PCIE_CONFIG_REG);
1012
1013 return EFI_SUCCESS;
1014
1015 }
1016
PcieDelay(UINT32 dCount)1017 VOID PcieDelay(UINT32 dCount)
1018 {
1019 volatile UINT32 *uwCnt = &dCount;
1020
1021 while(*uwCnt > 0)
1022 {
1023 *uwCnt = *uwCnt - 1;
1024 }
1025
1026 }
1027
1028