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1 /*
2  * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <arch.h>
8 #include <arch_helpers.h>
9 #include <arm_gic.h>
10 #include <assert.h>
11 #include <bl_common.h>
12 #include <debug.h>
13 #include <gic_v2.h>
14 #include <gic_v3.h>
15 #include <interrupt_mgmt.h>
16 #include <platform.h>
17 #include <stdint.h>
18 
19 /* Value used to initialize Non-Secure IRQ priorities four at a time */
20 #define GICD_IPRIORITYR_DEF_VAL \
21 	(GIC_HIGHEST_NS_PRIORITY | \
22 	(GIC_HIGHEST_NS_PRIORITY << 8) | \
23 	(GIC_HIGHEST_NS_PRIORITY << 16) | \
24 	(GIC_HIGHEST_NS_PRIORITY << 24))
25 
26 static uintptr_t g_gicc_base;
27 static uintptr_t g_gicd_base;
28 static uintptr_t g_gicr_base;
29 static const unsigned int *g_irq_sec_ptr;
30 static unsigned int g_num_irqs;
31 
32 
33 /*******************************************************************************
34  * This function does some minimal GICv3 configuration. The Firmware itself does
35  * not fully support GICv3 at this time and relies on GICv2 emulation as
36  * provided by GICv3. This function allows software (like Linux) in later stages
37  * to use full GICv3 features.
38  ******************************************************************************/
gicv3_cpuif_setup(void)39 static void gicv3_cpuif_setup(void)
40 {
41 	unsigned int val;
42 	uintptr_t base;
43 
44 	/*
45 	 * When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep
46 	 * bit set. In order to allow interrupts to get routed to the CPU we
47 	 * need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep
48 	 * to clear (GICv3 Architecture specification 5.4.23).
49 	 * GICR_WAKER is NOT banked per CPU, compute the correct base address
50 	 * per CPU.
51 	 */
52 	assert(g_gicr_base);
53 	base = gicv3_get_rdist(g_gicr_base, read_mpidr());
54 	if (base == (uintptr_t)NULL) {
55 		/* No re-distributor base address. This interface cannot be
56 		 * configured.
57 		 */
58 		panic();
59 	}
60 
61 	val = gicr_read_waker(base);
62 
63 	val &= ~WAKER_PS;
64 	gicr_write_waker(base, val);
65 	dsb();
66 
67 	/* We need to wait for ChildrenAsleep to clear. */
68 	val = gicr_read_waker(base);
69 	while (val & WAKER_CA)
70 		val = gicr_read_waker(base);
71 
72 	val = read_icc_sre_el3();
73 	write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE);
74 	isb();
75 }
76 
77 /*******************************************************************************
78  * This function does some minimal GICv3 configuration when cores go
79  * down.
80  ******************************************************************************/
gicv3_cpuif_deactivate(void)81 static void gicv3_cpuif_deactivate(void)
82 {
83 	unsigned int val;
84 	uintptr_t base;
85 
86 	/*
87 	 * When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and
88 	 * wait for GICR_WAKER.ChildrenAsleep to get set.
89 	 * (GICv3 Architecture specification 5.4.23).
90 	 * GICR_WAKER is NOT banked per CPU, compute the correct base address
91 	 * per CPU.
92 	 */
93 	assert(g_gicr_base);
94 	base = gicv3_get_rdist(g_gicr_base, read_mpidr());
95 	if (base == (uintptr_t)NULL) {
96 		/* No re-distributor base address. This interface cannot be
97 		 * configured.
98 		 */
99 		panic();
100 	}
101 
102 	val = gicr_read_waker(base);
103 	val |= WAKER_PS;
104 	gicr_write_waker(base, val);
105 	dsb();
106 
107 	/* We need to wait for ChildrenAsleep to set. */
108 	val = gicr_read_waker(base);
109 	while ((val & WAKER_CA) == 0)
110 		val = gicr_read_waker(base);
111 }
112 
113 
114 /*******************************************************************************
115  * Enable secure interrupts and use FIQs to route them. Disable legacy bypass
116  * and set the priority mask register to allow all interrupts to trickle in.
117  ******************************************************************************/
arm_gic_cpuif_setup(void)118 void arm_gic_cpuif_setup(void)
119 {
120 	unsigned int val;
121 
122 	assert(g_gicc_base);
123 	val = gicc_read_iidr(g_gicc_base);
124 
125 	/*
126 	 * If GICv3 we need to do a bit of additional setup. We want to
127 	 * allow default GICv2 behaviour but allow the next stage to
128 	 * enable full gicv3 features.
129 	 */
130 	if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3)
131 		gicv3_cpuif_setup();
132 
133 	val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0;
134 	val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
135 
136 	gicc_write_pmr(g_gicc_base, GIC_PRI_MASK);
137 	gicc_write_ctlr(g_gicc_base, val);
138 }
139 
140 /*******************************************************************************
141  * Place the cpu interface in a state where it can never make a cpu exit wfi as
142  * as result of an asserted interrupt. This is critical for powering down a cpu
143  ******************************************************************************/
arm_gic_cpuif_deactivate(void)144 void arm_gic_cpuif_deactivate(void)
145 {
146 	unsigned int val;
147 
148 	/* Disable secure, non-secure interrupts and disable their bypass */
149 	assert(g_gicc_base);
150 	val = gicc_read_ctlr(g_gicc_base);
151 	val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
152 	val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
153 	val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
154 	gicc_write_ctlr(g_gicc_base, val);
155 
156 	val = gicc_read_iidr(g_gicc_base);
157 
158 	/*
159 	 * If GICv3 we need to do a bit of additional setup. Make sure the
160 	 * RDIST is put to sleep.
161 	 */
162 	if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3)
163 		gicv3_cpuif_deactivate();
164 }
165 
166 /*******************************************************************************
167  * Per cpu gic distributor setup which will be done by all cpus after a cold
168  * boot/hotplug. This marks out the secure interrupts & enables them.
169  ******************************************************************************/
arm_gic_pcpu_distif_setup(void)170 void arm_gic_pcpu_distif_setup(void)
171 {
172 	unsigned int index, irq_num, sec_ppi_sgi_mask;
173 
174 	assert(g_gicd_base);
175 
176 	/* Setup PPI priorities doing four at a time */
177 	for (index = 0; index < 32; index += 4) {
178 		gicd_write_ipriorityr(g_gicd_base, index,
179 				GICD_IPRIORITYR_DEF_VAL);
180 	}
181 
182 	assert(g_irq_sec_ptr);
183 	sec_ppi_sgi_mask = 0;
184 
185 	/* Ensure all SGIs and PPIs are Group0 to begin with */
186 	gicd_write_igroupr(g_gicd_base, 0, 0);
187 
188 	for (index = 0; index < g_num_irqs; index++) {
189 		irq_num = g_irq_sec_ptr[index];
190 		if (irq_num < MIN_SPI_ID) {
191 			/* We have an SGI or a PPI */
192 			sec_ppi_sgi_mask |= 1U << irq_num;
193 			gicd_set_ipriorityr(g_gicd_base, irq_num,
194 				GIC_HIGHEST_SEC_PRIORITY);
195 			gicd_set_isenabler(g_gicd_base, irq_num);
196 		}
197 	}
198 
199 	/*
200 	 * Invert the bitmask to create a mask for non-secure PPIs and
201 	 * SGIs. Program the GICD_IGROUPR0 with this bit mask. This write will
202 	 * update the GICR_IGROUPR0 as well in case we are running on a GICv3
203 	 * system. This is critical if GICD_CTLR.ARE_NS=1.
204 	 */
205 	gicd_write_igroupr(g_gicd_base, 0, ~sec_ppi_sgi_mask);
206 }
207 
208 /*******************************************************************************
209  * Get the current CPU bit mask from GICD_ITARGETSR0
210  ******************************************************************************/
arm_gic_get_cpuif_id(void)211 static unsigned int arm_gic_get_cpuif_id(void)
212 {
213 	unsigned int val;
214 
215 	val = gicd_read_itargetsr(g_gicd_base, 0);
216 	return val & GIC_TARGET_CPU_MASK;
217 }
218 
219 /*******************************************************************************
220  * Global gic distributor setup which will be done by the primary cpu after a
221  * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
222  * then enables the secure GIC distributor interface.
223  ******************************************************************************/
arm_gic_distif_setup(void)224 static void arm_gic_distif_setup(void)
225 {
226 	unsigned int num_ints, ctlr, index, irq_num;
227 	uint8_t target_cpu;
228 
229 	/* Disable the distributor before going further */
230 	assert(g_gicd_base);
231 	ctlr = gicd_read_ctlr(g_gicd_base);
232 	ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1);
233 	gicd_write_ctlr(g_gicd_base, ctlr);
234 
235 	/*
236 	 * Mark out non-secure SPI interrupts. The number of interrupts is
237 	 * calculated as 32 * (IT_LINES + 1). We do 32 at a time.
238 	 */
239 	num_ints = gicd_read_typer(g_gicd_base) & IT_LINES_NO_MASK;
240 	num_ints = (num_ints + 1) << 5;
241 	for (index = MIN_SPI_ID; index < num_ints; index += 32)
242 		gicd_write_igroupr(g_gicd_base, index, ~0);
243 
244 	/* Setup SPI priorities doing four at a time */
245 	for (index = MIN_SPI_ID; index < num_ints; index += 4) {
246 		gicd_write_ipriorityr(g_gicd_base, index,
247 				GICD_IPRIORITYR_DEF_VAL);
248 	}
249 
250 	/* Read the target CPU mask */
251 	target_cpu = arm_gic_get_cpuif_id();
252 
253 	/* Configure SPI secure interrupts now */
254 	assert(g_irq_sec_ptr);
255 	for (index = 0; index < g_num_irqs; index++) {
256 		irq_num = g_irq_sec_ptr[index];
257 		if (irq_num >= MIN_SPI_ID) {
258 			/* We have an SPI */
259 			gicd_clr_igroupr(g_gicd_base, irq_num);
260 			gicd_set_ipriorityr(g_gicd_base, irq_num,
261 				GIC_HIGHEST_SEC_PRIORITY);
262 			gicd_set_itargetsr(g_gicd_base, irq_num, target_cpu);
263 			gicd_set_isenabler(g_gicd_base, irq_num);
264 		}
265 	}
266 
267 	/*
268 	 * Configure the SGI and PPI. This is done in a separated function
269 	 * because each CPU is responsible for initializing its own private
270 	 * interrupts.
271 	 */
272 	arm_gic_pcpu_distif_setup();
273 
274 	gicd_write_ctlr(g_gicd_base, ctlr | ENABLE_GRP0);
275 }
276 
277 /*******************************************************************************
278  * Initialize the ARM GIC driver with the provided platform inputs
279 ******************************************************************************/
arm_gic_init(uintptr_t gicc_base,uintptr_t gicd_base,uintptr_t gicr_base,const unsigned int * irq_sec_ptr,unsigned int num_irqs)280 void arm_gic_init(uintptr_t gicc_base,
281 		  uintptr_t gicd_base,
282 		  uintptr_t gicr_base,
283 		  const unsigned int *irq_sec_ptr,
284 		  unsigned int num_irqs)
285 {
286 	unsigned int val;
287 
288 	assert(gicc_base);
289 	assert(gicd_base);
290 	assert(irq_sec_ptr);
291 
292 	g_gicc_base = gicc_base;
293 	g_gicd_base = gicd_base;
294 
295 	val = gicc_read_iidr(g_gicc_base);
296 
297 	if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) {
298 		assert(gicr_base);
299 		g_gicr_base = gicr_base;
300 	}
301 
302 	g_irq_sec_ptr = irq_sec_ptr;
303 	g_num_irqs = num_irqs;
304 }
305 
306 /*******************************************************************************
307  * Setup the ARM GIC CPU and distributor interfaces.
308 ******************************************************************************/
arm_gic_setup(void)309 void arm_gic_setup(void)
310 {
311 	arm_gic_cpuif_setup();
312 	arm_gic_distif_setup();
313 }
314 
315 /*******************************************************************************
316  * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
317  * The interrupt controller knows which pin/line it uses to signal a type of
318  * interrupt. This function provides a common implementation of
319  * plat_interrupt_type_to_line() in an ARM GIC environment for optional re-use
320  * across platforms. It lets the interrupt management framework determine
321  * for a type of interrupt and security state, which line should be used in the
322  * SCR_EL3 to control its routing to EL3. The interrupt line is represented as
323  * the bit position of the IRQ or FIQ bit in the SCR_EL3.
324  ******************************************************************************/
arm_gic_interrupt_type_to_line(uint32_t type,uint32_t security_state)325 uint32_t arm_gic_interrupt_type_to_line(uint32_t type,
326 				uint32_t security_state)
327 {
328 	assert(type == INTR_TYPE_S_EL1 ||
329 	       type == INTR_TYPE_EL3 ||
330 	       type == INTR_TYPE_NS);
331 
332 	assert(sec_state_is_valid(security_state));
333 
334 	/*
335 	 * We ignore the security state parameter under the assumption that
336 	 * both normal and secure worlds are using ARM GICv2. This parameter
337 	 * will be used when the secure world starts using GICv3.
338 	 */
339 #if ARM_GIC_ARCH == 2
340 	return gicv2_interrupt_type_to_line(g_gicc_base, type);
341 #else
342 #error "Invalid ARM GIC architecture version specified for platform port"
343 #endif /* ARM_GIC_ARCH */
344 }
345 
346 #if ARM_GIC_ARCH == 2
347 /*******************************************************************************
348  * This function returns the type of the highest priority pending interrupt at
349  * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
350  * interrupt pending.
351  ******************************************************************************/
arm_gic_get_pending_interrupt_type(void)352 uint32_t arm_gic_get_pending_interrupt_type(void)
353 {
354 	uint32_t id;
355 
356 	assert(g_gicc_base);
357 	id = gicc_read_hppir(g_gicc_base) & INT_ID_MASK;
358 
359 	/* Assume that all secure interrupts are S-EL1 interrupts */
360 	if (id < 1022)
361 		return INTR_TYPE_S_EL1;
362 
363 	if (id == GIC_SPURIOUS_INTERRUPT)
364 		return INTR_TYPE_INVAL;
365 
366 	return INTR_TYPE_NS;
367 }
368 
369 /*******************************************************************************
370  * This function returns the id of the highest priority pending interrupt at
371  * the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
372  * interrupt pending.
373  ******************************************************************************/
arm_gic_get_pending_interrupt_id(void)374 uint32_t arm_gic_get_pending_interrupt_id(void)
375 {
376 	uint32_t id;
377 
378 	assert(g_gicc_base);
379 	id = gicc_read_hppir(g_gicc_base) & INT_ID_MASK;
380 
381 	if (id < 1022)
382 		return id;
383 
384 	if (id == 1023)
385 		return INTR_ID_UNAVAILABLE;
386 
387 	/*
388 	 * Find out which non-secure interrupt it is under the assumption that
389 	 * the GICC_CTLR.AckCtl bit is 0.
390 	 */
391 	return gicc_read_ahppir(g_gicc_base) & INT_ID_MASK;
392 }
393 
394 /*******************************************************************************
395  * This functions reads the GIC cpu interface Interrupt Acknowledge register
396  * to start handling the pending interrupt. It returns the contents of the IAR.
397  ******************************************************************************/
arm_gic_acknowledge_interrupt(void)398 uint32_t arm_gic_acknowledge_interrupt(void)
399 {
400 	assert(g_gicc_base);
401 	return gicc_read_IAR(g_gicc_base);
402 }
403 
404 /*******************************************************************************
405  * This functions writes the GIC cpu interface End Of Interrupt register with
406  * the passed value to finish handling the active interrupt
407  ******************************************************************************/
arm_gic_end_of_interrupt(uint32_t id)408 void arm_gic_end_of_interrupt(uint32_t id)
409 {
410 	assert(g_gicc_base);
411 	gicc_write_EOIR(g_gicc_base, id);
412 }
413 
414 /*******************************************************************************
415  * This function returns the type of the interrupt id depending upon the group
416  * this interrupt has been configured under by the interrupt controller i.e.
417  * group0 or group1.
418  ******************************************************************************/
arm_gic_get_interrupt_type(uint32_t id)419 uint32_t arm_gic_get_interrupt_type(uint32_t id)
420 {
421 	uint32_t group;
422 
423 	assert(g_gicd_base);
424 	group = gicd_get_igroupr(g_gicd_base, id);
425 
426 	/* Assume that all secure interrupts are S-EL1 interrupts */
427 	if (group == GRP0)
428 		return INTR_TYPE_S_EL1;
429 	else
430 		return INTR_TYPE_NS;
431 }
432 
433 #else
434 #error "Invalid ARM GIC architecture version specified for platform port"
435 #endif /* ARM_GIC_ARCH */
436