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1/*
2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8
9/memreserve/ 0x80000000 0x00010000;
10
11/ {
12};
13
14/ {
15	model = "FVP Foundation";
16	compatible = "arm,fvp-base", "arm,vexpress";
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	chosen { };
22
23	aliases {
24		serial0 = &v2m_serial0;
25		serial1 = &v2m_serial1;
26		serial2 = &v2m_serial2;
27		serial3 = &v2m_serial3;
28	};
29
30	psci {
31		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
32		method = "smc";
33		cpu_suspend = <0xc4000001>;
34		cpu_off = <0x84000002>;
35		cpu_on = <0xc4000003>;
36		sys_poweroff = <0x84000008>;
37		sys_reset = <0x84000009>;
38	};
39
40	cpus {
41		#address-cells = <2>;
42		#size-cells = <0>;
43
44		cpu-map {
45			cluster0 {
46				core0 {
47					cpu = <&CPU0>;
48				};
49				core1 {
50					cpu = <&CPU1>;
51				};
52				core2 {
53					cpu = <&CPU2>;
54				};
55				core3 {
56					cpu = <&CPU3>;
57				};
58			};
59		};
60
61		idle-states {
62			entry-method = "arm,psci";
63
64			CPU_SLEEP_0: cpu-sleep-0 {
65				compatible = "arm,idle-state";
66				local-timer-stop;
67				arm,psci-suspend-param = <0x0010000>;
68				entry-latency-us = <40>;
69				exit-latency-us = <100>;
70				min-residency-us = <150>;
71			};
72
73			CLUSTER_SLEEP_0: cluster-sleep-0 {
74				compatible = "arm,idle-state";
75				local-timer-stop;
76				arm,psci-suspend-param = <0x1010000>;
77				entry-latency-us = <500>;
78				exit-latency-us = <1000>;
79				min-residency-us = <2500>;
80			};
81		};
82
83		CPU0:cpu@0 {
84			device_type = "cpu";
85			compatible = "arm,armv8";
86			reg = <0x0 0x0>;
87			enable-method = "psci";
88			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
89			next-level-cache = <&L2_0>;
90		};
91
92		CPU1:cpu@1 {
93			device_type = "cpu";
94			compatible = "arm,armv8";
95			reg = <0x0 0x1>;
96			enable-method = "psci";
97			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
98			next-level-cache = <&L2_0>;
99		};
100
101		CPU2:cpu@2 {
102			device_type = "cpu";
103			compatible = "arm,armv8";
104			reg = <0x0 0x2>;
105			enable-method = "psci";
106			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
107			next-level-cache = <&L2_0>;
108		};
109
110		CPU3:cpu@3 {
111			device_type = "cpu";
112			compatible = "arm,armv8";
113			reg = <0x0 0x3>;
114			enable-method = "psci";
115			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
116			next-level-cache = <&L2_0>;
117		};
118
119		L2_0: l2-cache0 {
120			compatible = "cache";
121		};
122	};
123
124	memory@80000000 {
125		device_type = "memory";
126		reg = <0x00000000 0x80000000 0 0x7F000000>,
127		      <0x00000008 0x80000000 0 0x80000000>;
128	};
129
130	gic: interrupt-controller@2f000000 {
131		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
132		#interrupt-cells = <3>;
133		#address-cells = <0>;
134		interrupt-controller;
135		reg = <0x0 0x2f000000 0 0x10000>,
136		      <0x0 0x2c000000 0 0x2000>,
137		      <0x0 0x2c010000 0 0x2000>,
138		      <0x0 0x2c02F000 0 0x2000>;
139		interrupts = <1 9 0xf04>;
140	};
141
142	timer {
143		compatible = "arm,armv8-timer";
144		interrupts = <1 13 0xff01>,
145			     <1 14 0xff01>,
146			     <1 11 0xff01>,
147			     <1 10 0xff01>;
148		clock-frequency = <100000000>;
149	};
150
151	timer@2a810000 {
152			compatible = "arm,armv7-timer-mem";
153			reg = <0x0 0x2a810000 0x0 0x10000>;
154			clock-frequency = <100000000>;
155			#address-cells = <2>;
156			#size-cells = <2>;
157			ranges;
158			frame@2a830000 {
159				frame-number = <1>;
160				interrupts = <0 26 4>;
161				reg = <0x0 0x2a830000 0x0 0x10000>;
162			};
163	};
164
165	pmu {
166		compatible = "arm,armv8-pmuv3";
167		interrupts = <0 60 4>,
168			     <0 61 4>,
169			     <0 62 4>,
170			     <0 63 4>;
171	};
172
173	smb {
174		compatible = "simple-bus";
175
176		#address-cells = <2>;
177		#size-cells = <1>;
178		ranges = <0 0 0 0x08000000 0x04000000>,
179			 <1 0 0 0x14000000 0x04000000>,
180			 <2 0 0 0x18000000 0x04000000>,
181			 <3 0 0 0x1c000000 0x04000000>,
182			 <4 0 0 0x0c000000 0x04000000>,
183			 <5 0 0 0x10000000 0x04000000>;
184
185		/include/ "fvp-foundation-motherboard.dtsi"
186	};
187};
188