1/* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 10OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 11ENTRY(bl31_entrypoint) 12 13 14MEMORY { 15 RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_TZRAM_SIZE 16 RAM2 (rwx): ORIGIN = TZRAM2_BASE, LENGTH = TZRAM2_SIZE 17} 18 19 20SECTIONS 21{ 22 . = BL31_BASE; 23 24 ASSERT(. == ALIGN(2048), 25 "vector base is not aligned on a 2K boundary.") 26 27 __RO_START__ = .; 28 vector . : { 29 *(.vectors) 30 } >RAM 31 32 ASSERT(. == ALIGN(4096), 33 "BL31_BASE address is not aligned on a page boundary.") 34 35 ro . : { 36 *bl31_entrypoint.o(.text*) 37 *(.text*) 38 *(.rodata*) 39 40 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 41 . = ALIGN(8); 42 __RT_SVC_DESCS_START__ = .; 43 KEEP(*(rt_svc_descs)) 44 __RT_SVC_DESCS_END__ = .; 45 46 /* 47 * Ensure 8-byte alignment for cpu_ops so that its fields are also 48 * aligned. Also ensure cpu_ops inclusion. 49 */ 50 . = ALIGN(8); 51 __CPU_OPS_START__ = .; 52 KEEP(*(cpu_ops)) 53 __CPU_OPS_END__ = .; 54 55 __RO_END_UNALIGNED__ = .; 56 /* 57 * Memory page(s) mapped to this section will be marked as read-only, 58 * executable. No RW data from the next section must creep in. 59 * Ensure the rest of the current memory page is unused. 60 */ 61 . = NEXT(4096); 62 __RO_END__ = .; 63 } >RAM 64 65 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 66 "cpu_ops not defined for this platform.") 67 68 /* 69 * Define a linker symbol to mark start of the RW memory area for this 70 * image. 71 */ 72 __RW_START__ = . ; 73 74 /* 75 * .data must be placed at a lower address than the stacks if the stack 76 * protector is enabled. Alternatively, the .data.stack_protector_canary 77 * section can be placed independently of the main .data section. 78 */ 79 .data . : { 80 __DATA_START__ = .; 81 *(.data*) 82 __DATA_END__ = .; 83 } >RAM 84 85#ifdef BL31_PROGBITS_LIMIT 86 ASSERT(. <= BL31_PROGBITS_LIMIT, "BL3-1 progbits has exceeded its limit.") 87#endif 88 89 stacks (NOLOAD) : { 90 __STACKS_START__ = .; 91 *(tzfw_normal_stacks) 92 __STACKS_END__ = .; 93 } >RAM 94 95 /* 96 * The .bss section gets initialised to 0 at runtime. 97 * Its base address should be 16-byte aligned for better performance of the 98 * zero-initialization code. 99 */ 100 .bss (NOLOAD) : ALIGN(16) { 101 __BSS_START__ = .; 102 *(.bss*) 103 *(COMMON) 104#if !USE_COHERENT_MEM 105 /* 106 * Bakery locks are stored in normal .bss memory 107 * 108 * Each lock's data is spread across multiple cache lines, one per CPU, 109 * but multiple locks can share the same cache line. 110 * The compiler will allocate enough memory for one CPU's bakery locks, 111 * the remaining cache lines are allocated by the linker script 112 */ 113 . = ALIGN(CACHE_WRITEBACK_GRANULE); 114 __BAKERY_LOCK_START__ = .; 115 *(bakery_lock) 116 . = ALIGN(CACHE_WRITEBACK_GRANULE); 117 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__); 118 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 119 __BAKERY_LOCK_END__ = .; 120#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 121 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, 122 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); 123#endif 124#endif 125 __BSS_END__ = .; 126 __RW_END__ = .; 127 } >RAM 128 129 ASSERT(. <= BL31_LIMIT, "BL3-1 image has exceeded its limit.") 130 131 /* 132 * The xlat_table section is for full, aligned page tables (4K). 133 * Removing them from .bss avoids forcing 4K alignment on 134 * the .bss section and eliminates the unecessary zero init 135 */ 136 xlat_table (NOLOAD) : { 137 *(xlat_table) 138 } >RAM2 139 140#if USE_COHERENT_MEM 141 /* 142 * The base address of the coherent memory section must be page-aligned (4K) 143 * to guarantee that the coherent data are stored on their own pages and 144 * are not mixed with normal data. This is required to set up the correct 145 * memory attributes for the coherent data page tables. 146 */ 147 coherent_ram (NOLOAD) : ALIGN(4096) { 148 __COHERENT_RAM_START__ = .; 149 /* 150 * Bakery locks are stored in coherent memory 151 * 152 * Each lock's data is contiguous and fully allocated by the compiler 153 */ 154 *(bakery_lock) 155 *(tzfw_coherent_mem) 156 __COHERENT_RAM_END_UNALIGNED__ = .; 157 /* 158 * Memory page(s) mapped to this section will be marked 159 * as device memory. No other unexpected data must creep in. 160 * Ensure the rest of the current memory page is unused. 161 */ 162 . = NEXT(4096); 163 __COHERENT_RAM_END__ = .; 164 } >RAM2 165#endif 166 167 /* 168 * Define a linker symbol to mark end of the RW memory area for this 169 * image. 170 */ 171 __BL31_END__ = .; 172 173 __BSS_SIZE__ = SIZEOF(.bss); 174#if USE_COHERENT_MEM 175 __COHERENT_RAM_UNALIGNED_SIZE__ = 176 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 177#endif 178 179 ASSERT(. <= TZRAM2_LIMIT, "TZRAM2 image has exceeded its limit.") 180} 181