1 /*
2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_helpers.h>
8 #include <assert.h>
9 #include <bl31.h>
10 #include <bl_common.h>
11 #include <console.h>
12 #include <context.h>
13 #include <context_mgmt.h>
14 #include <cortex_a57.h>
15 #include <debug.h>
16 #include <denver.h>
17 #include <interrupt_mgmt.h>
18 #include <mce.h>
19 #include <platform.h>
20 #include <tegra_def.h>
21 #include <tegra_platform.h>
22 #include <tegra_private.h>
23 #include <xlat_tables.h>
24
25 DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1)
26 extern uint64_t tegra_enable_l2_ecc_parity_prot;
27
28 /*******************************************************************************
29 * Tegra186 CPU numbers in cluster #0
30 *******************************************************************************
31 */
32 #define TEGRA186_CLUSTER0_CORE2 2
33 #define TEGRA186_CLUSTER0_CORE3 3
34
35 /*******************************************************************************
36 * The Tegra power domain tree has a single system level power domain i.e. a
37 * single root node. The first entry in the power domain descriptor specifies
38 * the number of power domains at the highest power level.
39 *******************************************************************************
40 */
41 const unsigned char tegra_power_domain_tree_desc[] = {
42 /* No of root nodes */
43 1,
44 /* No of clusters */
45 PLATFORM_CLUSTER_COUNT,
46 /* No of CPU cores - cluster0 */
47 PLATFORM_MAX_CPUS_PER_CLUSTER,
48 /* No of CPU cores - cluster1 */
49 PLATFORM_MAX_CPUS_PER_CLUSTER
50 };
51
52 /*
53 * Table of regions to map using the MMU.
54 */
55 static const mmap_region_t tegra_mmap[] = {
56 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */
57 MT_DEVICE | MT_RW | MT_SECURE),
58 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */
59 MT_DEVICE | MT_RW | MT_SECURE),
60 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */
61 MT_DEVICE | MT_RW | MT_SECURE),
62 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */
63 MT_DEVICE | MT_RW | MT_SECURE),
64 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/
65 MT_DEVICE | MT_RW | MT_SECURE),
66 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */
67 MT_DEVICE | MT_RW | MT_SECURE),
68 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */
69 MT_DEVICE | MT_RW | MT_SECURE),
70 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */
71 MT_DEVICE | MT_RW | MT_SECURE),
72 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */
73 MT_DEVICE | MT_RW | MT_SECURE),
74 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */
75 MT_DEVICE | MT_RW | MT_SECURE),
76 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */
77 MT_DEVICE | MT_RW | MT_SECURE),
78 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */
79 MT_DEVICE | MT_RW | MT_SECURE),
80 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */
81 MT_DEVICE | MT_RW | MT_SECURE),
82 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */
83 MT_DEVICE | MT_RW | MT_SECURE),
84 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */
85 MT_DEVICE | MT_RW | MT_SECURE),
86 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */
87 MT_DEVICE | MT_RW | MT_SECURE),
88 MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000, /* 128KB - ARM/Denver */
89 MT_DEVICE | MT_RW | MT_SECURE),
90 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */
91 MT_DEVICE | MT_RW | MT_SECURE),
92 {0}
93 };
94
95 /*******************************************************************************
96 * Set up the pagetables as per the platform memory map & initialize the MMU
97 ******************************************************************************/
plat_get_mmio_map(void)98 const mmap_region_t *plat_get_mmio_map(void)
99 {
100 /* MMIO space */
101 return tegra_mmap;
102 }
103
104 /*******************************************************************************
105 * Handler to get the System Counter Frequency
106 ******************************************************************************/
plat_get_syscnt_freq2(void)107 unsigned int plat_get_syscnt_freq2(void)
108 {
109 return 31250000;
110 }
111
112 /*******************************************************************************
113 * Maximum supported UART controllers
114 ******************************************************************************/
115 #define TEGRA186_MAX_UART_PORTS 7
116
117 /*******************************************************************************
118 * This variable holds the UART port base addresses
119 ******************************************************************************/
120 static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
121 0, /* undefined - treated as an error case */
122 TEGRA_UARTA_BASE,
123 TEGRA_UARTB_BASE,
124 TEGRA_UARTC_BASE,
125 TEGRA_UARTD_BASE,
126 TEGRA_UARTE_BASE,
127 TEGRA_UARTF_BASE,
128 TEGRA_UARTG_BASE,
129 };
130
131 /*******************************************************************************
132 * Retrieve the UART controller base to be used as the console
133 ******************************************************************************/
plat_get_console_from_id(int id)134 uint32_t plat_get_console_from_id(int id)
135 {
136 if (id > TEGRA186_MAX_UART_PORTS)
137 return 0;
138
139 return tegra186_uart_addresses[id];
140 }
141
142 /* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */
143 #define TEGRA186_VER_A02P 0x1201
144
145 /*******************************************************************************
146 * Handler for early platform setup
147 ******************************************************************************/
plat_early_platform_setup(void)148 void plat_early_platform_setup(void)
149 {
150 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
151 uint32_t chip_subrev, val;
152
153 /* sanity check MCE firmware compatibility */
154 mce_verify_firmware_version();
155
156 /*
157 * Enable ECC and Parity Protection for Cortex-A57 CPUs
158 * for Tegra A02p SKUs
159 */
160 if (impl != DENVER_IMPL) {
161
162 /* get the major, minor and sub-version values */
163 chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) &
164 SUBREVISION_MASK;
165
166 /* prepare chip version number */
167 val = (tegra_get_chipid_major() << 12) |
168 (tegra_get_chipid_minor() << 8) |
169 chip_subrev;
170
171 /* enable L2 ECC for Tegra186 A02P and beyond */
172 if (val >= TEGRA186_VER_A02P) {
173
174 val = read_l2ctlr_el1();
175 val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
176 write_l2ctlr_el1(val);
177
178 /*
179 * Set the flag to enable ECC/Parity Protection
180 * when we exit System Suspend or Cluster Powerdn
181 */
182 tegra_enable_l2_ecc_parity_prot = 1;
183 }
184 }
185 }
186
187 /* Secure IRQs for Tegra186 */
188 static const irq_sec_cfg_t tegra186_sec_irqs[] = {
189 {
190 TEGRA186_TOP_WDT_IRQ,
191 TEGRA186_SEC_IRQ_TARGET_MASK,
192 INTR_TYPE_EL3,
193 },
194 {
195 TEGRA186_AON_WDT_IRQ,
196 TEGRA186_SEC_IRQ_TARGET_MASK,
197 INTR_TYPE_EL3,
198 },
199 };
200
201 /*******************************************************************************
202 * Initialize the GIC and SGIs
203 ******************************************************************************/
plat_gic_setup(void)204 void plat_gic_setup(void)
205 {
206 tegra_gic_setup(tegra186_sec_irqs,
207 sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0]));
208
209 /*
210 * Initialize the FIQ handler only if the platform supports any
211 * FIQ interrupt sources.
212 */
213 if (sizeof(tegra186_sec_irqs) > 0)
214 tegra_fiq_handler_setup();
215 }
216
217 /*******************************************************************************
218 * Return pointer to the BL31 params from previous bootloader
219 ******************************************************************************/
plat_get_bl31_params(void)220 bl31_params_t *plat_get_bl31_params(void)
221 {
222 uint32_t val;
223
224 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO);
225
226 return (bl31_params_t *)(uintptr_t)val;
227 }
228
229 /*******************************************************************************
230 * Return pointer to the BL31 platform params from previous bootloader
231 ******************************************************************************/
plat_get_bl31_plat_params(void)232 plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
233 {
234 uint32_t val;
235
236 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI);
237
238 return (plat_params_from_bl2_t *)(uintptr_t)val;
239 }
240
241 /*******************************************************************************
242 * This function implements a part of the critical interface between the psci
243 * generic layer and the platform that allows the former to query the platform
244 * to convert an MPIDR to a unique linear index. An error code (-1) is returned
245 * in case the MPIDR is invalid.
246 ******************************************************************************/
plat_core_pos_by_mpidr(u_register_t mpidr)247 int plat_core_pos_by_mpidr(u_register_t mpidr)
248 {
249 unsigned int cluster_id, cpu_id, pos;
250
251 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
252 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
253
254 /*
255 * Validate cluster_id by checking whether it represents
256 * one of the two clusters present on the platform.
257 */
258 if (cluster_id >= PLATFORM_CLUSTER_COUNT)
259 return PSCI_E_NOT_PRESENT;
260
261 /*
262 * Validate cpu_id by checking whether it represents a CPU in
263 * one of the two clusters present on the platform.
264 */
265 if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
266 return PSCI_E_NOT_PRESENT;
267
268 /* calculate the core position */
269 pos = cpu_id + (cluster_id << 2);
270
271 /* check for non-existent CPUs */
272 if (pos == TEGRA186_CLUSTER0_CORE2 || pos == TEGRA186_CLUSTER0_CORE3)
273 return PSCI_E_NOT_PRESENT;
274
275 return pos;
276 }
277